[name] Top solution Lines - 837951602 [puzzle] Sz001 [production-cost] 2600 [power-usage] 2059 [lines-of-code] 1 [traces] ...................... ...................... ...................... ...................... ...................... ..........954......... ....1C9554A.94........ .....AA9496169554..... .....AA34A.15615C..... ....16A.16954...A..... .....1E1C.A.9554A..... ......2.2.3421556..... ...................... ...................... [chip] [type] NOTE [x] 1 [y] -1 [code] PGA mapping a:_--------- -_________ _-_------- -_________ _-_------- -_________ _-_-_----- -_________ _-_------- -_________ _-_-_-_-_----- * b:* c b:_-________ __________ _-_-______ __________ _-_-______ __________ _-_-_-____ __________ _-_-______ __________ _-_-_-_-_-____ a(a')~a:c(c')~c * c:* d c:_--------- --________ _--------- --________ _--------- --________ _--------- --________ _--------- --________ _------------- * e:g h d:---------- --_------- ---------- --_------- ---------- --_------- ---------- --_------- ---------- --_------- -------------- b(e') f:f (h) i * *:* j e:_--------- ---------- -__------- ---------- -__------- ---------- -__--_____ __________ _--_______ __________ _--__--__----- [chip] [type] NOTE [x] 1 [y] -3 [code] Here, f:_--------- ---------- --_------- ---------- --_------- ---------- --_---____ __________ _---______ __________ _---_---_----- * means no input, and g:---------- ---------- ---------- ---------- ---------- ---------- ---------- --_------- ---------- --_------- -------------- letter mean the matched diagram h:__________ __________ __________ __________ __________ __________ __________ __________ __________ __-_______ ______________ shown right, separated by i:-_________ __________ __-_______ __________ __-_______ __________ __-___---- ---_______ __________ ___------- -___-___-_____ space per cycle. ' is delay 1c. j:__________ __________ __________ __________ __________ __________ __________ ___------- ---------- ---_______ ______________ [chip] [type] NOT [x] 6 [y] 3 [chip] [type] PGA [x] 9 [y] 3 [array-switch] True [array-data] 0,0,0,0,0,0,1,1,1,0,0,0,0,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,1,0,1,0,0,0,0,0,1,0,0,0,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 [chip] [type] PGA [x] 12 [y] 3 [array-switch] True [array-data] 0,0,0,0,0,1,1,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,1,1,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,1,1,0,0,0,0,0,0,0,0,0,0 [chip] [type] BANK [x] 5 [y] 4 [rom] 1,-837,1,-951,1,-602,0,1,0,1,0,0,0,0 [chip] [type] UC4 [x] 5 [y] 6 [code] gen p1 x0 x1 # 3LoC -ROM -PGA # 2LoC +ROM -PGA # 2LoC -ROM +PGA # 1Loc +ROM +PGA # So ROM and PGA # each save 1LoC:> # See below for # timing diagram [chip] [type] PGA [x] 9 [y] 6 [array-switch] False [array-data] 0,0,0,0,1,1,0,1,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0 [chip] [type] PGA [x] 13 [y] 6 [array-switch] False [array-data] 0,0,1,1,0,0,0,1,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,1,1,0,0,0,1,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0