// !!!!!! This generated VQM is intended for Academic use or Internal Altera use only !!!!!! // Functionality may not be correct on the programmed device or in simulation // Copyright (C) 1991-2015 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, the Altera Quartus II License Agreement, // the Altera MegaCore Function License Agreement, or other // applicable license agreement, including, without limitation, // that your use is for the sole purpose of programming logic // devices manufactured by Altera and sold by Altera or its // authorized distributors. Please refer to the applicable // agreement for further details. // VENDOR "Altera" // PROGRAM "Quartus II 64-Bit" // VERSION "Version 15.0.0 Build 145 04/22/2015 SJ Full Version" // DATE "03/09/2017 17:45:12" module fp_pow ( clk, areset, a, b, q); input clk; input areset; input [31:0] a; input [31:0] b; output [31:0] q; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_p[0][35] ; wire \fp_pow_0002:fp_pow_inst|Mult16~8 ; wire \fp_pow_0002:fp_pow_inst|Mult16~9 ; wire \fp_pow_0002:fp_pow_inst|Mult16~10 ; wire \fp_pow_0002:fp_pow_inst|Mult16~11 ; wire \fp_pow_0002:fp_pow_inst|Mult16~12 ; wire \fp_pow_0002:fp_pow_inst|Mult16~13 ; wire \fp_pow_0002:fp_pow_inst|Mult16~14 ; wire \fp_pow_0002:fp_pow_inst|Mult16~15 ; wire \fp_pow_0002:fp_pow_inst|Mult16~16 ; wire \fp_pow_0002:fp_pow_inst|Mult16~17 ; wire \fp_pow_0002:fp_pow_inst|Mult16~18 ; wire \fp_pow_0002:fp_pow_inst|Mult16~19 ; wire \fp_pow_0002:fp_pow_inst|Mult16~20 ; wire \fp_pow_0002:fp_pow_inst|Mult16~21 ; wire \fp_pow_0002:fp_pow_inst|Mult16~22 ; wire \fp_pow_0002:fp_pow_inst|Mult16~23 ; wire \fp_pow_0002:fp_pow_inst|Mult16~24 ; wire \fp_pow_0002:fp_pow_inst|Mult16~25 ; wire \fp_pow_0002:fp_pow_inst|Mult16~26 ; wire \fp_pow_0002:fp_pow_inst|Mult16~27 ; wire \fp_pow_0002:fp_pow_inst|Mult16~28 ; wire \fp_pow_0002:fp_pow_inst|Mult16~29 ; wire \fp_pow_0002:fp_pow_inst|Mult16~30 ; wire \fp_pow_0002:fp_pow_inst|Mult16~31 ; wire \fp_pow_0002:fp_pow_inst|Mult16~32 ; wire \fp_pow_0002:fp_pow_inst|Mult16~33 ; wire \fp_pow_0002:fp_pow_inst|Mult16~34 ; wire \fp_pow_0002:fp_pow_inst|Mult16~35 ; wire \fp_pow_0002:fp_pow_inst|Add44~8 ; wire \fp_pow_0002:fp_pow_inst|Add44~9 ; wire \fp_pow_0002:fp_pow_inst|Add44~10 ; wire \fp_pow_0002:fp_pow_inst|Add44~11 ; wire \fp_pow_0002:fp_pow_inst|Add44~12 ; wire \fp_pow_0002:fp_pow_inst|Add44~13 ; wire \fp_pow_0002:fp_pow_inst|Add44~14 ; wire \fp_pow_0002:fp_pow_inst|Add44~15 ; wire \fp_pow_0002:fp_pow_inst|Add44~16 ; wire \fp_pow_0002:fp_pow_inst|Add44~17 ; wire \fp_pow_0002:fp_pow_inst|Add44~18 ; wire \fp_pow_0002:fp_pow_inst|Add44~19 ; wire \fp_pow_0002:fp_pow_inst|Add44~20 ; wire \fp_pow_0002:fp_pow_inst|Add44~21 ; wire \fp_pow_0002:fp_pow_inst|Add44~22 ; wire \fp_pow_0002:fp_pow_inst|Add44~23 ; wire \fp_pow_0002:fp_pow_inst|Add44~24 ; wire \fp_pow_0002:fp_pow_inst|Add44~25 ; wire \fp_pow_0002:fp_pow_inst|Add44~26 ; wire \fp_pow_0002:fp_pow_inst|Add44~27 ; wire \fp_pow_0002:fp_pow_inst|Add44~28 ; wire \fp_pow_0002:fp_pow_inst|Add44~29 ; wire \fp_pow_0002:fp_pow_inst|Add44~30 ; wire \fp_pow_0002:fp_pow_inst|Add44~31 ; wire \fp_pow_0002:fp_pow_inst|Add44~32 ; wire \fp_pow_0002:fp_pow_inst|Add44~33 ; wire \fp_pow_0002:fp_pow_inst|Add44~34 ; wire \fp_pow_0002:fp_pow_inst|Add44~35 ; wire \fp_pow_0002:fp_pow_inst|Add44~36 ; wire \fp_pow_0002:fp_pow_inst|Add44~37 ; wire \fp_pow_0002:fp_pow_inst|Add44~38 ; wire \fp_pow_0002:fp_pow_inst|Add44~39 ; wire \fp_pow_0002:fp_pow_inst|Add44~40 ; wire \fp_pow_0002:fp_pow_inst|Add44~41 ; wire \fp_pow_0002:fp_pow_inst|Add44~42 ; wire \fp_pow_0002:fp_pow_inst|Add44~43 ; wire \fp_pow_0002:fp_pow_inst|Add44~44 ; wire \fp_pow_0002:fp_pow_inst|Add44~45 ; wire \fp_pow_0002:fp_pow_inst|Add44~46 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|Mult13~8 ; wire \fp_pow_0002:fp_pow_inst|Mult13~9 ; wire \fp_pow_0002:fp_pow_inst|Mult13~10 ; wire \fp_pow_0002:fp_pow_inst|Mult13~11 ; wire \fp_pow_0002:fp_pow_inst|Mult13~12 ; wire \fp_pow_0002:fp_pow_inst|Mult13~13 ; wire \fp_pow_0002:fp_pow_inst|Mult13~14 ; wire \fp_pow_0002:fp_pow_inst|Mult13~15 ; wire \fp_pow_0002:fp_pow_inst|Mult13~16 ; wire \fp_pow_0002:fp_pow_inst|Mult13~17 ; wire \fp_pow_0002:fp_pow_inst|Mult13~18 ; wire \fp_pow_0002:fp_pow_inst|Mult13~19 ; wire \fp_pow_0002:fp_pow_inst|Mult13~20 ; wire \fp_pow_0002:fp_pow_inst|Mult13~21 ; wire \fp_pow_0002:fp_pow_inst|Mult13~22 ; wire \fp_pow_0002:fp_pow_inst|Mult13~23 ; wire \fp_pow_0002:fp_pow_inst|Mult13~24 ; wire \fp_pow_0002:fp_pow_inst|Mult13~25 ; wire \fp_pow_0002:fp_pow_inst|Mult13~26 ; wire \fp_pow_0002:fp_pow_inst|Mult13~27 ; wire \fp_pow_0002:fp_pow_inst|Mult13~28 ; wire \fp_pow_0002:fp_pow_inst|Mult13~29 ; wire \fp_pow_0002:fp_pow_inst|Mult13~30 ; wire \fp_pow_0002:fp_pow_inst|Mult13~31 ; wire \fp_pow_0002:fp_pow_inst|Mult13~32 ; wire \fp_pow_0002:fp_pow_inst|Mult13~33 ; wire \fp_pow_0002:fp_pow_inst|Mult13~34 ; wire \fp_pow_0002:fp_pow_inst|Mult13~35 ; wire \fp_pow_0002:fp_pow_inst|Mult13~36 ; wire \fp_pow_0002:fp_pow_inst|Mult13~37 ; wire \fp_pow_0002:fp_pow_inst|Mult13~38 ; wire \fp_pow_0002:fp_pow_inst|Mult13~39 ; wire \fp_pow_0002:fp_pow_inst|Mult13~40 ; wire \fp_pow_0002:fp_pow_inst|Mult13~41 ; wire \fp_pow_0002:fp_pow_inst|Mult13~42 ; wire \fp_pow_0002:fp_pow_inst|Mult13~43 ; wire \fp_pow_0002:fp_pow_inst|Mult13~44 ; wire \fp_pow_0002:fp_pow_inst|Mult13~45 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|Mult12~8 ; wire \fp_pow_0002:fp_pow_inst|Mult12~9 ; wire \fp_pow_0002:fp_pow_inst|Mult12~10 ; wire \fp_pow_0002:fp_pow_inst|Mult12~11 ; wire \fp_pow_0002:fp_pow_inst|Mult12~12 ; wire \fp_pow_0002:fp_pow_inst|Mult12~13 ; wire \fp_pow_0002:fp_pow_inst|Mult12~14 ; wire \fp_pow_0002:fp_pow_inst|Mult12~15 ; wire \fp_pow_0002:fp_pow_inst|Mult12~16 ; wire \fp_pow_0002:fp_pow_inst|Mult12~17 ; wire \fp_pow_0002:fp_pow_inst|Mult12~18 ; wire \fp_pow_0002:fp_pow_inst|Mult12~19 ; wire \fp_pow_0002:fp_pow_inst|Mult12~20 ; wire \fp_pow_0002:fp_pow_inst|Mult12~21 ; wire \fp_pow_0002:fp_pow_inst|Mult12~22 ; wire \fp_pow_0002:fp_pow_inst|Mult12~23 ; wire \fp_pow_0002:fp_pow_inst|Mult12~24 ; wire \fp_pow_0002:fp_pow_inst|Mult12~25 ; wire \fp_pow_0002:fp_pow_inst|Mult12~26 ; wire \fp_pow_0002:fp_pow_inst|Mult12~27 ; wire \fp_pow_0002:fp_pow_inst|Mult12~28 ; wire \fp_pow_0002:fp_pow_inst|Mult12~29 ; wire \fp_pow_0002:fp_pow_inst|Mult12~30 ; wire \fp_pow_0002:fp_pow_inst|Mult12~31 ; wire \fp_pow_0002:fp_pow_inst|Mult12~32 ; wire \fp_pow_0002:fp_pow_inst|Mult12~33 ; wire \fp_pow_0002:fp_pow_inst|Mult12~34 ; wire \fp_pow_0002:fp_pow_inst|Mult12~35 ; wire \fp_pow_0002:fp_pow_inst|Mult12~36 ; wire \fp_pow_0002:fp_pow_inst|Mult12~37 ; wire \fp_pow_0002:fp_pow_inst|Mult12~38 ; wire \fp_pow_0002:fp_pow_inst|Mult12~39 ; wire \fp_pow_0002:fp_pow_inst|Mult12~40 ; wire \fp_pow_0002:fp_pow_inst|Mult12~41 ; wire \fp_pow_0002:fp_pow_inst|Mult12~42 ; wire \fp_pow_0002:fp_pow_inst|Mult12~43 ; wire \fp_pow_0002:fp_pow_inst|Mult12~44 ; wire \fp_pow_0002:fp_pow_inst|Mult12~45 ; wire \fp_pow_0002:fp_pow_inst|Mult12~46 ; wire \fp_pow_0002:fp_pow_inst|Mult12~47 ; wire \fp_pow_0002:fp_pow_inst|Mult12~48 ; wire \fp_pow_0002:fp_pow_inst|Mult12~49 ; wire \fp_pow_0002:fp_pow_inst|Mult12~50 ; wire \fp_pow_0002:fp_pow_inst|Mult12~51 ; wire \fp_pow_0002:fp_pow_inst|Mult12~52 ; wire \fp_pow_0002:fp_pow_inst|Mult12~53 ; wire \fp_pow_0002:fp_pow_inst|Mult12~54 ; wire \fp_pow_0002:fp_pow_inst|Mult12~55 ; wire \fp_pow_0002:fp_pow_inst|Mult12~56 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|Mult10~8 ; wire \fp_pow_0002:fp_pow_inst|Mult10~9 ; wire \fp_pow_0002:fp_pow_inst|Mult10~10 ; wire \fp_pow_0002:fp_pow_inst|Mult10~11 ; wire \fp_pow_0002:fp_pow_inst|Mult10~12 ; wire \fp_pow_0002:fp_pow_inst|Mult10~13 ; wire \fp_pow_0002:fp_pow_inst|Mult10~14 ; wire \fp_pow_0002:fp_pow_inst|Mult10~15 ; wire \fp_pow_0002:fp_pow_inst|Mult10~16 ; wire \fp_pow_0002:fp_pow_inst|Mult10~17 ; wire \fp_pow_0002:fp_pow_inst|Mult10~18 ; wire \fp_pow_0002:fp_pow_inst|Mult10~19 ; wire \fp_pow_0002:fp_pow_inst|Mult10~20 ; wire \fp_pow_0002:fp_pow_inst|Mult10~21 ; wire \fp_pow_0002:fp_pow_inst|Mult10~22 ; wire \fp_pow_0002:fp_pow_inst|Mult10~23 ; wire \fp_pow_0002:fp_pow_inst|Mult10~24 ; wire \fp_pow_0002:fp_pow_inst|Mult10~25 ; wire \fp_pow_0002:fp_pow_inst|Mult10~26 ; wire \fp_pow_0002:fp_pow_inst|Mult10~27 ; wire \fp_pow_0002:fp_pow_inst|Mult10~28 ; wire \fp_pow_0002:fp_pow_inst|Mult10~29 ; wire \fp_pow_0002:fp_pow_inst|Mult10~30 ; wire \fp_pow_0002:fp_pow_inst|Mult10~31 ; wire \fp_pow_0002:fp_pow_inst|Mult10~32 ; wire \fp_pow_0002:fp_pow_inst|Mult10~33 ; wire \fp_pow_0002:fp_pow_inst|Mult10~34 ; wire \fp_pow_0002:fp_pow_inst|Mult10~35 ; wire \fp_pow_0002:fp_pow_inst|Mult10~36 ; wire \fp_pow_0002:fp_pow_inst|Mult10~37 ; wire \fp_pow_0002:fp_pow_inst|Mult10~38 ; wire \fp_pow_0002:fp_pow_inst|Mult10~39 ; wire \fp_pow_0002:fp_pow_inst|Mult10~40 ; wire \fp_pow_0002:fp_pow_inst|Mult10~41 ; wire \fp_pow_0002:fp_pow_inst|Mult10~42 ; wire \fp_pow_0002:fp_pow_inst|Mult10~43 ; wire \fp_pow_0002:fp_pow_inst|Mult10~44 ; wire \fp_pow_0002:fp_pow_inst|Mult10~45 ; wire \fp_pow_0002:fp_pow_inst|Mult10~46 ; wire \fp_pow_0002:fp_pow_inst|Mult10~47 ; wire \fp_pow_0002:fp_pow_inst|Mult10~48 ; wire \fp_pow_0002:fp_pow_inst|Mult10~49 ; wire \fp_pow_0002:fp_pow_inst|Add24~8 ; wire \fp_pow_0002:fp_pow_inst|Add24~9 ; wire \fp_pow_0002:fp_pow_inst|Add24~10 ; wire \fp_pow_0002:fp_pow_inst|Add24~11 ; wire \fp_pow_0002:fp_pow_inst|Add24~12 ; wire \fp_pow_0002:fp_pow_inst|Add24~13 ; wire \fp_pow_0002:fp_pow_inst|Add24~14 ; wire \fp_pow_0002:fp_pow_inst|Add24~15 ; wire \fp_pow_0002:fp_pow_inst|Add24~16 ; wire \fp_pow_0002:fp_pow_inst|Add24~17 ; wire \fp_pow_0002:fp_pow_inst|Add24~18 ; wire \fp_pow_0002:fp_pow_inst|Add24~19 ; wire \fp_pow_0002:fp_pow_inst|Add24~20 ; wire \fp_pow_0002:fp_pow_inst|Add24~21 ; wire \fp_pow_0002:fp_pow_inst|Add24~22 ; wire \fp_pow_0002:fp_pow_inst|Add24~23 ; wire \fp_pow_0002:fp_pow_inst|Add24~24 ; wire \fp_pow_0002:fp_pow_inst|Add24~25 ; wire \fp_pow_0002:fp_pow_inst|Add24~26 ; wire \fp_pow_0002:fp_pow_inst|Add24~27 ; wire \fp_pow_0002:fp_pow_inst|Add24~28 ; wire \fp_pow_0002:fp_pow_inst|Add24~29 ; wire \fp_pow_0002:fp_pow_inst|Add24~30 ; wire \fp_pow_0002:fp_pow_inst|Add24~31 ; wire \fp_pow_0002:fp_pow_inst|Add24~32 ; wire \fp_pow_0002:fp_pow_inst|Add24~33 ; wire \fp_pow_0002:fp_pow_inst|Add24~34 ; wire \fp_pow_0002:fp_pow_inst|Add24~35 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][0] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][1] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][2] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][3] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][4] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][5] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][6] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][7] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][8] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][9] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][10] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][11] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][12] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][13] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][14] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][15] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][16] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][17] ; wire \fp_pow_0002:fp_pow_inst|Mult11~8 ; wire \fp_pow_0002:fp_pow_inst|Mult11~9 ; wire \fp_pow_0002:fp_pow_inst|Mult11~10 ; wire \fp_pow_0002:fp_pow_inst|Mult11~11 ; wire \fp_pow_0002:fp_pow_inst|Mult11~12 ; wire \fp_pow_0002:fp_pow_inst|Mult11~13 ; wire \fp_pow_0002:fp_pow_inst|Mult11~14 ; wire \fp_pow_0002:fp_pow_inst|Mult11~15 ; wire \fp_pow_0002:fp_pow_inst|Mult11~16 ; wire \fp_pow_0002:fp_pow_inst|Mult11~17 ; wire \fp_pow_0002:fp_pow_inst|Mult11~18 ; wire \fp_pow_0002:fp_pow_inst|Mult11~19 ; wire \fp_pow_0002:fp_pow_inst|Mult11~20 ; wire \fp_pow_0002:fp_pow_inst|Mult11~21 ; wire \fp_pow_0002:fp_pow_inst|Mult11~22 ; wire \fp_pow_0002:fp_pow_inst|Mult11~23 ; wire \fp_pow_0002:fp_pow_inst|Mult11~24 ; wire \fp_pow_0002:fp_pow_inst|Mult11~25 ; wire \fp_pow_0002:fp_pow_inst|Mult11~26 ; wire \fp_pow_0002:fp_pow_inst|Mult11~27 ; wire \fp_pow_0002:fp_pow_inst|Mult11~28 ; wire \fp_pow_0002:fp_pow_inst|Mult11~29 ; wire \fp_pow_0002:fp_pow_inst|Mult11~30 ; wire \fp_pow_0002:fp_pow_inst|Mult11~31 ; wire \fp_pow_0002:fp_pow_inst|Mult11~32 ; wire \fp_pow_0002:fp_pow_inst|Mult11~33 ; wire \fp_pow_0002:fp_pow_inst|Mult11~34 ; wire \fp_pow_0002:fp_pow_inst|Mult11~35 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|Mult7~8 ; wire \fp_pow_0002:fp_pow_inst|Mult7~9 ; wire \fp_pow_0002:fp_pow_inst|Mult7~10 ; wire \fp_pow_0002:fp_pow_inst|Mult7~11 ; wire \fp_pow_0002:fp_pow_inst|Mult7~12 ; wire \fp_pow_0002:fp_pow_inst|Mult7~13 ; wire \fp_pow_0002:fp_pow_inst|Mult7~14 ; wire \fp_pow_0002:fp_pow_inst|Mult7~15 ; wire \fp_pow_0002:fp_pow_inst|Mult7~16 ; wire \fp_pow_0002:fp_pow_inst|Mult7~17 ; wire \fp_pow_0002:fp_pow_inst|Mult7~18 ; wire \fp_pow_0002:fp_pow_inst|Mult7~19 ; wire \fp_pow_0002:fp_pow_inst|Mult7~20 ; wire \fp_pow_0002:fp_pow_inst|Mult7~21 ; wire \fp_pow_0002:fp_pow_inst|Mult7~22 ; wire \fp_pow_0002:fp_pow_inst|Mult7~23 ; wire \fp_pow_0002:fp_pow_inst|Mult7~24 ; wire \fp_pow_0002:fp_pow_inst|Mult7~25 ; wire \fp_pow_0002:fp_pow_inst|Mult7~26 ; wire \fp_pow_0002:fp_pow_inst|Mult7~27 ; wire \fp_pow_0002:fp_pow_inst|Mult7~28 ; wire \fp_pow_0002:fp_pow_inst|Mult7~29 ; wire \fp_pow_0002:fp_pow_inst|Mult7~30 ; wire \fp_pow_0002:fp_pow_inst|Mult7~31 ; wire \fp_pow_0002:fp_pow_inst|Mult7~32 ; wire \fp_pow_0002:fp_pow_inst|Mult7~33 ; wire \fp_pow_0002:fp_pow_inst|Mult7~34 ; wire \fp_pow_0002:fp_pow_inst|Mult7~35 ; wire \fp_pow_0002:fp_pow_inst|Mult6~8 ; wire \fp_pow_0002:fp_pow_inst|Mult6~9 ; wire \fp_pow_0002:fp_pow_inst|Mult6~10 ; wire \fp_pow_0002:fp_pow_inst|Mult6~11 ; wire \fp_pow_0002:fp_pow_inst|Mult6~12 ; wire \fp_pow_0002:fp_pow_inst|Mult6~13 ; wire \fp_pow_0002:fp_pow_inst|Mult6~14 ; wire \fp_pow_0002:fp_pow_inst|Mult6~15 ; wire \fp_pow_0002:fp_pow_inst|Mult6~16 ; wire \fp_pow_0002:fp_pow_inst|Mult6~17 ; wire \fp_pow_0002:fp_pow_inst|Mult6~18 ; wire \fp_pow_0002:fp_pow_inst|Mult6~19 ; wire \fp_pow_0002:fp_pow_inst|Mult6~20 ; wire \fp_pow_0002:fp_pow_inst|Mult6~21 ; wire \fp_pow_0002:fp_pow_inst|Mult6~22 ; wire \fp_pow_0002:fp_pow_inst|Mult6~23 ; wire \fp_pow_0002:fp_pow_inst|Mult6~24 ; wire \fp_pow_0002:fp_pow_inst|Mult6~25 ; wire \fp_pow_0002:fp_pow_inst|Mult6~26 ; wire \fp_pow_0002:fp_pow_inst|Mult6~27 ; wire \fp_pow_0002:fp_pow_inst|Mult6~28 ; wire \fp_pow_0002:fp_pow_inst|Mult6~29 ; wire \fp_pow_0002:fp_pow_inst|Mult6~30 ; wire \fp_pow_0002:fp_pow_inst|Mult6~31 ; wire \fp_pow_0002:fp_pow_inst|Mult6~32 ; wire \fp_pow_0002:fp_pow_inst|Mult6~33 ; wire \fp_pow_0002:fp_pow_inst|Mult6~34 ; wire \fp_pow_0002:fp_pow_inst|Mult6~35 ; wire \fp_pow_0002:fp_pow_inst|Mult6~36 ; wire \fp_pow_0002:fp_pow_inst|Mult6~37 ; wire \fp_pow_0002:fp_pow_inst|Mult6~38 ; wire \fp_pow_0002:fp_pow_inst|Mult6~39 ; wire \fp_pow_0002:fp_pow_inst|Mult6~40 ; wire \fp_pow_0002:fp_pow_inst|Mult6~41 ; wire \fp_pow_0002:fp_pow_inst|Mult6~42 ; wire \fp_pow_0002:fp_pow_inst|Mult6~43 ; wire \fp_pow_0002:fp_pow_inst|Mult6~44 ; wire \fp_pow_0002:fp_pow_inst|Mult6~45 ; wire \fp_pow_0002:fp_pow_inst|Mult6~46 ; wire \fp_pow_0002:fp_pow_inst|Mult6~47 ; wire \fp_pow_0002:fp_pow_inst|Add8~8 ; wire \fp_pow_0002:fp_pow_inst|Add8~9 ; wire \fp_pow_0002:fp_pow_inst|Add8~10 ; wire \fp_pow_0002:fp_pow_inst|Add8~11 ; wire \fp_pow_0002:fp_pow_inst|Add8~12 ; wire \fp_pow_0002:fp_pow_inst|Add8~13 ; wire \fp_pow_0002:fp_pow_inst|Add8~14 ; wire \fp_pow_0002:fp_pow_inst|Add8~15 ; wire \fp_pow_0002:fp_pow_inst|Add8~16 ; wire \fp_pow_0002:fp_pow_inst|Add8~17 ; wire \fp_pow_0002:fp_pow_inst|Add8~18 ; wire \fp_pow_0002:fp_pow_inst|Add8~19 ; wire \fp_pow_0002:fp_pow_inst|Add8~20 ; wire \fp_pow_0002:fp_pow_inst|Add8~21 ; wire \fp_pow_0002:fp_pow_inst|Add8~22 ; wire \fp_pow_0002:fp_pow_inst|Add8~23 ; wire \fp_pow_0002:fp_pow_inst|Add8~24 ; wire \fp_pow_0002:fp_pow_inst|Add8~25 ; wire \fp_pow_0002:fp_pow_inst|Add8~26 ; wire \fp_pow_0002:fp_pow_inst|Add8~27 ; wire \fp_pow_0002:fp_pow_inst|Add8~28 ; wire \fp_pow_0002:fp_pow_inst|Add8~29 ; wire \fp_pow_0002:fp_pow_inst|Add8~30 ; wire \fp_pow_0002:fp_pow_inst|Add8~31 ; wire \fp_pow_0002:fp_pow_inst|Add8~32 ; wire \fp_pow_0002:fp_pow_inst|Add8~33 ; wire \fp_pow_0002:fp_pow_inst|Add8~34 ; wire \fp_pow_0002:fp_pow_inst|Add8~35 ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_p[0][35] ; wire \fp_pow_0002:fp_pow_inst|Mult3~8 ; wire \fp_pow_0002:fp_pow_inst|Mult3~9 ; wire \fp_pow_0002:fp_pow_inst|Mult3~10 ; wire \fp_pow_0002:fp_pow_inst|Mult3~11 ; wire \fp_pow_0002:fp_pow_inst|Mult3~12 ; wire \fp_pow_0002:fp_pow_inst|Mult3~13 ; wire \fp_pow_0002:fp_pow_inst|Mult3~14 ; wire \fp_pow_0002:fp_pow_inst|Mult3~15 ; wire \fp_pow_0002:fp_pow_inst|Mult3~16 ; wire \fp_pow_0002:fp_pow_inst|Mult3~17 ; wire \fp_pow_0002:fp_pow_inst|Mult3~18 ; wire \fp_pow_0002:fp_pow_inst|Mult3~19 ; wire \fp_pow_0002:fp_pow_inst|Mult3~20 ; wire \fp_pow_0002:fp_pow_inst|Mult3~21 ; wire \fp_pow_0002:fp_pow_inst|Mult3~22 ; wire \fp_pow_0002:fp_pow_inst|Mult3~23 ; wire \fp_pow_0002:fp_pow_inst|Mult3~24 ; wire \fp_pow_0002:fp_pow_inst|Mult3~25 ; wire \fp_pow_0002:fp_pow_inst|Mult3~26 ; wire \fp_pow_0002:fp_pow_inst|Mult3~27 ; wire \fp_pow_0002:fp_pow_inst|Mult3~28 ; wire \fp_pow_0002:fp_pow_inst|Mult3~29 ; wire \fp_pow_0002:fp_pow_inst|Mult3~30 ; wire \fp_pow_0002:fp_pow_inst|Mult3~31 ; wire \fp_pow_0002:fp_pow_inst|Mult3~32 ; wire \fp_pow_0002:fp_pow_inst|Mult3~33 ; wire \fp_pow_0002:fp_pow_inst|Mult3~34 ; wire \fp_pow_0002:fp_pow_inst|Mult3~35 ; wire \fp_pow_0002:fp_pow_inst|Mult2~8 ; wire \fp_pow_0002:fp_pow_inst|Mult2~9 ; wire \fp_pow_0002:fp_pow_inst|Mult2~10 ; wire \fp_pow_0002:fp_pow_inst|Mult2~11 ; wire \fp_pow_0002:fp_pow_inst|Mult2~12 ; wire \fp_pow_0002:fp_pow_inst|Mult2~13 ; wire \fp_pow_0002:fp_pow_inst|Mult2~14 ; wire \fp_pow_0002:fp_pow_inst|Mult2~15 ; wire \fp_pow_0002:fp_pow_inst|Mult2~16 ; wire \fp_pow_0002:fp_pow_inst|Mult2~17 ; wire \fp_pow_0002:fp_pow_inst|Mult2~18 ; wire \fp_pow_0002:fp_pow_inst|Mult2~19 ; wire \fp_pow_0002:fp_pow_inst|Mult2~20 ; wire \fp_pow_0002:fp_pow_inst|Mult2~21 ; wire \fp_pow_0002:fp_pow_inst|Mult2~22 ; wire \fp_pow_0002:fp_pow_inst|Mult2~23 ; wire \fp_pow_0002:fp_pow_inst|Mult2~24 ; wire \fp_pow_0002:fp_pow_inst|Mult2~25 ; wire \fp_pow_0002:fp_pow_inst|Mult2~26 ; wire \fp_pow_0002:fp_pow_inst|Mult2~27 ; wire \fp_pow_0002:fp_pow_inst|Mult2~28 ; wire \fp_pow_0002:fp_pow_inst|Mult2~29 ; wire \fp_pow_0002:fp_pow_inst|Mult2~30 ; wire \fp_pow_0002:fp_pow_inst|Mult2~31 ; wire \fp_pow_0002:fp_pow_inst|Mult2~32 ; wire \fp_pow_0002:fp_pow_inst|Mult2~33 ; wire \fp_pow_0002:fp_pow_inst|Mult2~34 ; wire \fp_pow_0002:fp_pow_inst|Mult2~35 ; wire \fp_pow_0002:fp_pow_inst|Mult2~36 ; wire \fp_pow_0002:fp_pow_inst|Mult2~37 ; wire \fp_pow_0002:fp_pow_inst|Mult2~38 ; wire \fp_pow_0002:fp_pow_inst|Mult2~39 ; wire \fp_pow_0002:fp_pow_inst|Mult2~40 ; wire \fp_pow_0002:fp_pow_inst|Mult2~41 ; wire \fp_pow_0002:fp_pow_inst|Mult2~42 ; wire \fp_pow_0002:fp_pow_inst|Mult2~43 ; wire \fp_pow_0002:fp_pow_inst|Mult2~44 ; wire \fp_pow_0002:fp_pow_inst|Mult2~45 ; wire \fp_pow_0002:fp_pow_inst|Mult2~46 ; wire \fp_pow_0002:fp_pow_inst|Mult2~47 ; wire \fp_pow_0002:fp_pow_inst|Mult2~48 ; wire \fp_pow_0002:fp_pow_inst|Mult2~49 ; wire \fp_pow_0002:fp_pow_inst|Mult2~50 ; wire \fp_pow_0002:fp_pow_inst|Mult2~51 ; wire \fp_pow_0002:fp_pow_inst|Mult2~52 ; wire \fp_pow_0002:fp_pow_inst|Mult2~53 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT2 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT4 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT5 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT6 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT8 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT10 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT11 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT12 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT13 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT14 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT15 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT16 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT17 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT18 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT19 ; wire \fp_pow_0002:fp_pow_inst|Mult1~8 ; wire \fp_pow_0002:fp_pow_inst|Mult1~9 ; wire \fp_pow_0002:fp_pow_inst|Mult1~10 ; wire \fp_pow_0002:fp_pow_inst|Mult1~11 ; wire \fp_pow_0002:fp_pow_inst|Mult1~12 ; wire \fp_pow_0002:fp_pow_inst|Mult1~13 ; wire \fp_pow_0002:fp_pow_inst|Mult1~14 ; wire \fp_pow_0002:fp_pow_inst|Mult1~15 ; wire \fp_pow_0002:fp_pow_inst|Mult1~16 ; wire \fp_pow_0002:fp_pow_inst|Mult1~17 ; wire \fp_pow_0002:fp_pow_inst|Mult1~18 ; wire \fp_pow_0002:fp_pow_inst|Mult1~19 ; wire \fp_pow_0002:fp_pow_inst|Mult1~20 ; wire \fp_pow_0002:fp_pow_inst|Mult1~21 ; wire \fp_pow_0002:fp_pow_inst|Mult1~22 ; wire \fp_pow_0002:fp_pow_inst|Mult1~23 ; wire \fp_pow_0002:fp_pow_inst|Mult1~24 ; wire \fp_pow_0002:fp_pow_inst|Mult1~25 ; wire \fp_pow_0002:fp_pow_inst|Mult1~26 ; wire \fp_pow_0002:fp_pow_inst|Mult1~27 ; wire \fp_pow_0002:fp_pow_inst|Mult1~28 ; wire \fp_pow_0002:fp_pow_inst|Mult1~29 ; wire \fp_pow_0002:fp_pow_inst|Mult1~30 ; wire \fp_pow_0002:fp_pow_inst|Mult1~31 ; wire \fp_pow_0002:fp_pow_inst|Mult1~32 ; wire \fp_pow_0002:fp_pow_inst|Mult1~33 ; wire \fp_pow_0002:fp_pow_inst|Mult1~34 ; wire \fp_pow_0002:fp_pow_inst|Mult1~35 ; wire \fp_pow_0002:fp_pow_inst|Mult1~36 ; wire \fp_pow_0002:fp_pow_inst|Mult1~37 ; wire \fp_pow_0002:fp_pow_inst|Mult1~38 ; wire \fp_pow_0002:fp_pow_inst|Mult1~39 ; wire \fp_pow_0002:fp_pow_inst|Mult1~40 ; wire \fp_pow_0002:fp_pow_inst|Mult1~41 ; wire \fp_pow_0002:fp_pow_inst|Mult1~42 ; wire \fp_pow_0002:fp_pow_inst|Mult1~43 ; wire \fp_pow_0002:fp_pow_inst|Mult1~44 ; wire \fp_pow_0002:fp_pow_inst|Mult1~45 ; wire \fp_pow_0002:fp_pow_inst|Mult1~46 ; wire \fp_pow_0002:fp_pow_inst|Mult1~47 ; wire \fp_pow_0002:fp_pow_inst|Mult0~8 ; wire \fp_pow_0002:fp_pow_inst|Mult0~9 ; wire \fp_pow_0002:fp_pow_inst|Mult0~10 ; wire \fp_pow_0002:fp_pow_inst|Mult0~11 ; wire \fp_pow_0002:fp_pow_inst|Mult0~12 ; wire \fp_pow_0002:fp_pow_inst|Mult0~13 ; wire \fp_pow_0002:fp_pow_inst|Mult0~14 ; wire \fp_pow_0002:fp_pow_inst|Mult0~15 ; wire \fp_pow_0002:fp_pow_inst|Mult0~16 ; wire \fp_pow_0002:fp_pow_inst|Mult0~17 ; wire \fp_pow_0002:fp_pow_inst|Mult0~18 ; wire \fp_pow_0002:fp_pow_inst|Mult0~19 ; wire \fp_pow_0002:fp_pow_inst|Mult0~20 ; wire \fp_pow_0002:fp_pow_inst|Mult0~21 ; wire \fp_pow_0002:fp_pow_inst|Mult0~22 ; wire \fp_pow_0002:fp_pow_inst|Mult0~23 ; wire \fp_pow_0002:fp_pow_inst|Mult0~24 ; wire \fp_pow_0002:fp_pow_inst|Mult0~25 ; wire \fp_pow_0002:fp_pow_inst|Mult0~26 ; wire \fp_pow_0002:fp_pow_inst|Mult0~27 ; wire \fp_pow_0002:fp_pow_inst|Mult0~28 ; wire \fp_pow_0002:fp_pow_inst|Mult0~29 ; wire \fp_pow_0002:fp_pow_inst|Mult0~30 ; wire \fp_pow_0002:fp_pow_inst|Mult0~31 ; wire \fp_pow_0002:fp_pow_inst|Mult0~32 ; wire \fp_pow_0002:fp_pow_inst|Mult0~33 ; wire \fp_pow_0002:fp_pow_inst|Mult0~34 ; wire \fp_pow_0002:fp_pow_inst|Mult0~35 ; wire \fp_pow_0002:fp_pow_inst|Mult0~36 ; wire \fp_pow_0002:fp_pow_inst|Mult0~37 ; wire \fp_pow_0002:fp_pow_inst|Mult0~38 ; wire \fp_pow_0002:fp_pow_inst|Mult0~39 ; wire \fp_pow_0002:fp_pow_inst|Mult0~40 ; wire \fp_pow_0002:fp_pow_inst|Mult0~41 ; wire \fp_pow_0002:fp_pow_inst|Mult0~42 ; wire \fp_pow_0002:fp_pow_inst|Mult0~43 ; wire \fp_pow_0002:fp_pow_inst|Mult0~44 ; wire \fp_pow_0002:fp_pow_inst|Mult0~45 ; wire \fp_pow_0002:fp_pow_inst|Mult0~46 ; wire \fp_pow_0002:fp_pow_inst|Mult0~47 ; wire \fp_pow_0002:fp_pow_inst|Mult0~48 ; wire \fp_pow_0002:fp_pow_inst|Mult0~49 ; wire \fp_pow_0002:fp_pow_inst|Mult0~50 ; wire \fp_pow_0002:fp_pow_inst|Mult0~51 ; wire \fp_pow_0002:fp_pow_inst|Mult0~52 ; wire \fp_pow_0002:fp_pow_inst|Mult0~53 ; wire \fp_pow_0002:fp_pow_inst|Mult0~54 ; wire \fp_pow_0002:fp_pow_inst|Mult0~55 ; wire \fp_pow_0002:fp_pow_inst|Mult0~56 ; wire \fp_pow_0002:fp_pow_inst|Mult0~57 ; wire \clk~input0 ; wire \clk~CLKENA0 ; wire \fp_pow_0002:fp_pow_inst|redist130_sticky_ena_q[0]~feeder ; wire \areset~input0 ; wire \areset~CLKENA0 ; wire \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i~1 ; wire \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[1] ; wire \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[2]~2 ; wire \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[2] ; wire \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~3 ; wire \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3] ; wire \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[4]~4 ; wire \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[4] ; wire \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Equal28~0 ; wire \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_eq ; wire \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[0]~0 ; wire \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[0] ; wire \fp_pow_0002:fp_pow_inst|Equal27~0 ; wire \fp_pow_0002:fp_pow_inst|redist78_cmpReg_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist130_sticky_ena_q[0] ; wire \b[31]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[35][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[34][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[33][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[32][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[31][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[30][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[29][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[29][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[28][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[27][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[26][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[26][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[25][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[24][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[23][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[22][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[21][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[20][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[19][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[19][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[18][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[17][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[17][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[16][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[15][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[14][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[14][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[13][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[12][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[11][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[10][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[9][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[8][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[7][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[7][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[6][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[5][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[4][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[3][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[0]~0 ; wire \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[2] ; wire \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[3] ; wire \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[4]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist130_outputreg|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|redist118_sticky_ena_q[0]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0]~0 ; wire \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[1] ; wire \fp_pow_0002:fp_pow_inst|redist102_replace_rdcnt_i[1]~0 ; wire \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Add54~0 ; wire \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[2]~0 ; wire \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[2] ; wire \fp_pow_0002:fp_pow_inst|Equal25~0 ; wire \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_eq ; wire \fp_pow_0002:fp_pow_inst|Add54~1 ; wire \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[3] ; wire \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[4]~1 ; wire \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[4] ; wire \fp_pow_0002:fp_pow_inst|Equal24~0 ; wire \fp_pow_0002:fp_pow_inst|redist77_cmpReg_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist118_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist131_sticky_ena_q[0]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[0]~3 ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[0] ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[1] ; wire \fp_pow_0002:fp_pow_inst|Add17~0 ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i~0 ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[2] ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4]~2 ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4] ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Equal8~0 ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_eq ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[3]~1 ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[3] ; wire \fp_pow_0002:fp_pow_inst|Equal7~0 ; wire \fp_pow_0002:fp_pow_inst|redist131_cmpReg_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist131_sticky_ena_q[0] ; wire \b[23]~input0 ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0]~0 ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[2]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][0] ; wire \b[26]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][3] ; wire \b[28]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][5] ; wire \b[30]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][7] ; wire \b[27]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][4] ; wire \b[29]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|Equal26~0 ; wire \b[24]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][1] ; wire \b[25]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][2]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|Equal26~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expXIsMax_uid42_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[3][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[2][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ; wire \b[22]~input0 ; wire \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][22] ; wire \b[21]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][21] ; wire \b[20]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][20] ; wire \b[19]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][19] ; wire \b[18]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][18] ; wire \b[17]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][17] ; wire \b[16]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][16] ; wire \b[15]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][15] ; wire \b[14]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][14]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][14]~DUPLICATE ; wire \b[13]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][13] ; wire \b[12]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][12]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][12] ; wire \b[11]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][11]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][11] ; wire \b[10]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][10]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][10]~DUPLICATE ; wire \b[9]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][9]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][9]~DUPLICATE ; wire \b[8]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][8] ; wire \b[7]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][7] ; wire \b[6]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][6] ; wire \b[5]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][5] ; wire \b[4]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][4]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][4] ; wire \b[3]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][3]~DUPLICATE ; wire \b[2]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][2]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][2] ; wire \b[1]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][1]~DUPLICATE ; wire \b[0]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add55~94 ; wire \fp_pow_0002:fp_pow_inst|Add55~90 ; wire \fp_pow_0002:fp_pow_inst|Add55~86 ; wire \fp_pow_0002:fp_pow_inst|Add55~82 ; wire \fp_pow_0002:fp_pow_inst|Add55~78 ; wire \fp_pow_0002:fp_pow_inst|Add55~74 ; wire \fp_pow_0002:fp_pow_inst|Add55~70 ; wire \fp_pow_0002:fp_pow_inst|Add55~66 ; wire \fp_pow_0002:fp_pow_inst|Add55~62 ; wire \fp_pow_0002:fp_pow_inst|Add55~58 ; wire \fp_pow_0002:fp_pow_inst|Add55~54 ; wire \fp_pow_0002:fp_pow_inst|Add55~50 ; wire \fp_pow_0002:fp_pow_inst|Add55~46 ; wire \fp_pow_0002:fp_pow_inst|Add55~42 ; wire \fp_pow_0002:fp_pow_inst|Add55~38 ; wire \fp_pow_0002:fp_pow_inst|Add55~34 ; wire \fp_pow_0002:fp_pow_inst|Add55~30 ; wire \fp_pow_0002:fp_pow_inst|Add55~26 ; wire \fp_pow_0002:fp_pow_inst|Add55~22 ; wire \fp_pow_0002:fp_pow_inst|Add55~18 ; wire \fp_pow_0002:fp_pow_inst|Add55~14 ; wire \fp_pow_0002:fp_pow_inst|Add55~10 ; wire \fp_pow_0002:fp_pow_inst|Add55~6 ; wire \fp_pow_0002:fp_pow_inst|Add55~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:fracXIsZero_uid45_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[3][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|redist118_replace_mem_ia[0] ; wire \fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ; wire \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[2] ; wire \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[3] ; wire \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[1]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[3]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|redist127_sticky_ena_q[0]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist127_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_eq ; wire \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[3]~0 ; wire \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[3] ; wire \fp_pow_0002:fp_pow_inst|Equal4~0 ; wire \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_eq~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Add12~0 ; wire \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[2] ; wire \fp_pow_0002:fp_pow_inst|Equal3~0 ; wire \fp_pow_0002:fp_pow_inst|redist134_cmpReg_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist134_sticky_ena_q[0]~0 ; wire \fp_pow_0002:fp_pow_inst|redist134_sticky_ena_q[0] ; wire \a[25]~input0 ; wire \fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[2]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[2] ; wire \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[3]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[3]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[1]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[3]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][2] ; wire \a[24]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][1] ; wire \a[29]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][6] ; wire \a[27]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][4]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][4] ; wire \a[30]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][7] ; wire \a[28]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|Equal6~0 ; wire \a[26]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][3] ; wire \a[23]~input0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Equal6~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expXIsZero_uid24_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[17][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[16][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[16][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[15][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[15][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[14][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[13][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[13][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[12][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[12][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[11][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[11][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[10][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[9][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[9][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[8][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[8][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[7][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[6][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[5][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[4][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[3][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[3][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[0][0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist127_inputreg|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_eq ; wire \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[2]~0 ; wire \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[2] ; wire \fp_pow_0002:fp_pow_inst|Add60~1 ; wire \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[3] ; wire \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[4]~1 ; wire \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[4] ; wire \fp_pow_0002:fp_pow_inst|Equal30~0 ; wire \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_eq~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Add60~0 ; wire \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[1] ; wire \fp_pow_0002:fp_pow_inst|Equal29~0 ; wire \fp_pow_0002:fp_pow_inst|redist117_cmpReg_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist117_sticky_ena_q[0]~0 ; wire \fp_pow_0002:fp_pow_inst|redist117_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|Equal23~0 ; wire \fp_pow_0002:fp_pow_inst|Equal23~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expXIsZero_uid40_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[3][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|exc_R_uid51_fpPowrTest_q_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:exc_R_uid51_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[1]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[1] ; wire \fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[2] ; wire \fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[3] ; wire \fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[1]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[1] ; wire \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[2]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist117_outputreg|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|zeroCase0_uid179_fpPowrTest_q_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|delay_signals[0][0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|redist77_sticky_ena_q[0]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist77_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Equal5~0 ; wire \fp_pow_0002:fp_pow_inst|Equal5~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expXIsMax_uid26_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[17][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[16][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[16][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[15][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[14][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[13][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[12][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[12][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[11][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[10][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[9][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[8][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[7][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[6][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[5][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[4][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[4][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[3][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|exc_R_uid35_fpPowrTest_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[3] ; wire \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2]~0 ; wire \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2] ; wire \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i~1 ; wire \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[3]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Equal2~0 ; wire \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_eq ; wire \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[0] ; wire \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[0]~2 ; wire \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Add6~0 ; wire \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[1] ; wire \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Equal1~0 ; wire \fp_pow_0002:fp_pow_inst|redist137_cmpReg_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0]~0 ; wire \fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ; wire \a[10]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][10]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0]~0 ; wire \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] ; wire \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ; wire \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][10] ; wire \a[11]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][11]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][11] ; wire \a[9]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][9]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][9]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][9]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][9] ; wire \a[8]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][8]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|Equal22~2 ; wire \a[6]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][6] ; wire \a[12]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][12]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][12]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][12] ; wire \a[18]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][18] ; wire \a[13]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][13]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][13]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][13]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][13] ; wire \a[22]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][22]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][22] ; wire \a[20]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][20]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][20] ; wire \a[19]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][19]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][19] ; wire \a[21]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][21]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][21] ; wire \a[0]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[0] ; wire \fp_pow_0002:fp_pow_inst|Equal22~3 ; wire \a[16]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][16]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][16] ; wire \a[17]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][17]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][17] ; wire \a[15]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][15] ; wire \a[14]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][14]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][14]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|Equal22~4 ; wire \fp_pow_0002:fp_pow_inst|Equal22~5 ; wire \a[7]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][7]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Equal22~6 ; wire \fp_pow_0002:fp_pow_inst|Equal22~1 ; wire \a[1]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][1] ; wire \a[5]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][5] ; wire \a[2]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][2]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][2]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][2]~DUPLICATE ; wire \a[3]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][3]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][3] ; wire \a[4]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][4]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Equal22~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Equal22~7 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:xEQOneAbs_uid19_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128_inputreg|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[19][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[18][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[17][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[16][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[16][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[15][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[14][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[14][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[13][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[12][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[12][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[11][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[10][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[10][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[9][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[9][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[8][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[8][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[7][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[7][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[6][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[6][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[5][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[5][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[4][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[4][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[3][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[0][0]~DUPLICATE ; wire \a[31]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[35][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[34][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[33][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[33][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[32][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[31][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[30][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[29][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[28][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[27][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[26][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[25][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[24][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[23][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[22][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[21][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[20][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[19][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[19][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[18][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[18][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[17][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[16][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[15][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[14][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[13][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[12][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[11][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[10][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[9][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[8][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[7][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[6][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[5][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[5][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[4][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[3][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[2][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add56~94 ; wire \fp_pow_0002:fp_pow_inst|Add56~90 ; wire \fp_pow_0002:fp_pow_inst|Add56~86 ; wire \fp_pow_0002:fp_pow_inst|Add56~82 ; wire \fp_pow_0002:fp_pow_inst|Add56~78 ; wire \fp_pow_0002:fp_pow_inst|Add56~74 ; wire \fp_pow_0002:fp_pow_inst|Add56~70 ; wire \fp_pow_0002:fp_pow_inst|Add56~66 ; wire \fp_pow_0002:fp_pow_inst|Add56~62 ; wire \fp_pow_0002:fp_pow_inst|Add56~58 ; wire \fp_pow_0002:fp_pow_inst|Add56~54 ; wire \fp_pow_0002:fp_pow_inst|Add56~50 ; wire \fp_pow_0002:fp_pow_inst|Add56~46 ; wire \fp_pow_0002:fp_pow_inst|Add56~42 ; wire \fp_pow_0002:fp_pow_inst|Add56~38 ; wire \fp_pow_0002:fp_pow_inst|Add56~34 ; wire \fp_pow_0002:fp_pow_inst|Add56~30 ; wire \fp_pow_0002:fp_pow_inst|Add56~26 ; wire \fp_pow_0002:fp_pow_inst|Add56~22 ; wire \fp_pow_0002:fp_pow_inst|Add56~18 ; wire \fp_pow_0002:fp_pow_inst|Add56~14 ; wire \fp_pow_0002:fp_pow_inst|Add56~10 ; wire \fp_pow_0002:fp_pow_inst|Add56~6 ; wire \fp_pow_0002:fp_pow_inst|Add56~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:fracXIsZero_uid29_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[19][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[18][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[18][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[17][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[16][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[15][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[14][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[13][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[12][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[11][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[10][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[10][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[9][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[9][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[8][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[7][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[6][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[5][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[4][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[3][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124_outputreg|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|excRNaN_uid204_fpPowrTest_q_i[0]~1 ; wire \fp_pow_0002:fp_pow_inst|excRNaN_uid204_fpPowrTest_q_i[0]~0 ; wire \fp_pow_0002:fp_pow_inst|excRNaN_uid204_fpPowrTest_q_i[0]~2 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:excRNaN_uid204_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|redist82_sticky_ena_q[0]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist82_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[0][0]~_wirecell ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist82_outputreg|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|zeroCase1_uid177_fpPowrTest_q_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|redist122_sticky_ena_q[0]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist122_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist122_inputreg|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|redist79_sticky_ena_q[0]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist79_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|Add62~30 ; wire \fp_pow_0002:fp_pow_inst|Add62~26 ; wire \fp_pow_0002:fp_pow_inst|Add62~22 ; wire \fp_pow_0002:fp_pow_inst|Add62~18 ; wire \fp_pow_0002:fp_pow_inst|Add62~14 ; wire \fp_pow_0002:fp_pow_inst|Add62~10 ; wire \fp_pow_0002:fp_pow_inst|Add62~6 ; wire \fp_pow_0002:fp_pow_inst|Add62~1 ; wire \fp_pow_0002:fp_pow_inst|xInZO_uid159_fpPowrTest_o[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[17][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[17][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[16][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[15][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[14][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[13][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[12][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[11][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[10][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[9][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[8][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[7][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[6][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[5][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[4][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[4][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[3][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|xInZOZPos_uid161_fpPowrTest_q_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:xInZOZPos_uid161_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|infCase2_uid192_fpPowrTest_q_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:infCase2_uid192_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|redist97_sticky_ena_q[0]~feeder ; wire \fp_pow_0002:fp_pow_inst|Add52~0 ; wire \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[1] ; wire \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i~0 ; wire \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[2] ; wire \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i~1 ; wire \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[3] ; wire \fp_pow_0002:fp_pow_inst|Equal21~0 ; wire \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_eq ; wire \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[0] ; wire \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[0]~3 ; wire \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[3]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4]~2 ; wire \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4] ; wire \fp_pow_0002:fp_pow_inst|Equal20~0 ; wire \fp_pow_0002:fp_pow_inst|redist75_cmpReg_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist97_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q[0]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[0] ; wire \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[0]~0 ; wire \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Equal16~0 ; wire \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_eq ; wire \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i~1 ; wire \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[1] ; wire \fp_pow_0002:fp_pow_inst|Equal15~0 ; wire \fp_pow_0002:fp_pow_inst|redist9_cmpReg_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Add13~2 ; wire \fp_pow_0002:fp_pow_inst|Add13~6 ; wire \fp_pow_0002:fp_pow_inst|Add13~10 ; wire \fp_pow_0002:fp_pow_inst|Add13~14 ; wire \fp_pow_0002:fp_pow_inst|Add13~18 ; wire \fp_pow_0002:fp_pow_inst|Add13~22 ; wire \fp_pow_0002:fp_pow_inst|Add13~30 ; wire \fp_pow_0002:fp_pow_inst|Add13~34 ; wire \fp_pow_0002:fp_pow_inst|Add13~25 ; wire \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[46] ; wire \fp_pow_0002:fp_pow_inst|Add13~33 ; wire \fp_pow_0002:fp_pow_inst|Add13~29 ; wire \fp_pow_0002:fp_pow_inst|Mux0~0 ; wire \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[45] ; wire \fp_pow_0002:fp_pow_inst|Mux1~0 ; wire \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[44] ; wire \fp_pow_0002:fp_pow_inst|Add13~5 ; wire \fp_pow_0002:fp_pow_inst|Add13~1 ; wire \fp_pow_0002:fp_pow_inst|Add13~17 ; wire \fp_pow_0002:fp_pow_inst|Add13~9 ; wire \fp_pow_0002:fp_pow_inst|Add13~13 ; wire \fp_pow_0002:fp_pow_inst|Ram0~31 ; wire \fp_pow_0002:fp_pow_inst|Add13~21 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|Mux2~0 ; wire \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[43] ; wire \fp_pow_0002:fp_pow_inst|Ram0~28 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|Mux3~0 ; wire \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[42] ; wire \fp_pow_0002:fp_pow_inst|Ram0~32 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|Mux4~0 ; wire \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[41] ; wire \fp_pow_0002:fp_pow_inst|Ram0~33 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|Mux5~0 ; wire \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[40] ; wire \fp_pow_0002:fp_pow_inst|Ram0~34 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|Ram0~35 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|Ram0~29 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|Ram0~30 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|Ram0~23 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|Mux6~0 ; wire \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[34] ; wire \fp_pow_0002:fp_pow_inst|Ram0~24 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|Ram0~25 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|Ram0~26 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|Ram0~27 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|Mux7~0 ; wire \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[31] ; wire \fp_pow_0002:fp_pow_inst|Ram0~16 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|Mux8~0 ; wire \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[30] ; wire \fp_pow_0002:fp_pow_inst|Ram0~18 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|Ram0~19 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|Ram0~20 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|Ram0~21 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|Ram0~22 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|Ram0~17 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|Ram0~10 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|Ram0~11 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|Ram0~12 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|Ram0~13 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|Ram0~14 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|Ram0~15 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|Ram0~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|Mux9~0 ; wire \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[17] ; wire \fp_pow_0002:fp_pow_inst|Ram0~6 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|Ram0~7 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|Ram0~8 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|Ram0~9 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|Ram0~36 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|Mux10~0 ; wire \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[10] ; wire \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[9] ; wire \fp_pow_0002:fp_pow_inst|Add14~150 ; wire \fp_pow_0002:fp_pow_inst|Add14~146 ; wire \fp_pow_0002:fp_pow_inst|Add14~142 ; wire \fp_pow_0002:fp_pow_inst|Add14~26 ; wire \fp_pow_0002:fp_pow_inst|Add14~22 ; wire \fp_pow_0002:fp_pow_inst|Add14~18 ; wire \fp_pow_0002:fp_pow_inst|Add14~14 ; wire \fp_pow_0002:fp_pow_inst|Add14~10 ; wire \fp_pow_0002:fp_pow_inst|Add14~6 ; wire \fp_pow_0002:fp_pow_inst|Add14~50 ; wire \fp_pow_0002:fp_pow_inst|Add14~46 ; wire \fp_pow_0002:fp_pow_inst|Add14~42 ; wire \fp_pow_0002:fp_pow_inst|Add14~38 ; wire \fp_pow_0002:fp_pow_inst|Add14~34 ; wire \fp_pow_0002:fp_pow_inst|Add14~30 ; wire \fp_pow_0002:fp_pow_inst|Add14~58 ; wire \fp_pow_0002:fp_pow_inst|Add14~78 ; wire \fp_pow_0002:fp_pow_inst|Add14~74 ; wire \fp_pow_0002:fp_pow_inst|Add14~70 ; wire \fp_pow_0002:fp_pow_inst|Add14~66 ; wire \fp_pow_0002:fp_pow_inst|Add14~62 ; wire \fp_pow_0002:fp_pow_inst|Add14~54 ; wire \fp_pow_0002:fp_pow_inst|Add14~98 ; wire \fp_pow_0002:fp_pow_inst|Add14~94 ; wire \fp_pow_0002:fp_pow_inst|Add14~90 ; wire \fp_pow_0002:fp_pow_inst|Add14~86 ; wire \fp_pow_0002:fp_pow_inst|Add14~82 ; wire \fp_pow_0002:fp_pow_inst|Add14~110 ; wire \fp_pow_0002:fp_pow_inst|Add14~106 ; wire \fp_pow_0002:fp_pow_inst|Add14~138 ; wire \fp_pow_0002:fp_pow_inst|Add14~134 ; wire \fp_pow_0002:fp_pow_inst|Add14~130 ; wire \fp_pow_0002:fp_pow_inst|Add14~126 ; wire \fp_pow_0002:fp_pow_inst|Add14~102 ; wire \fp_pow_0002:fp_pow_inst|Add14~122 ; wire \fp_pow_0002:fp_pow_inst|Add14~118 ; wire \fp_pow_0002:fp_pow_inst|Add14~114 ; wire \fp_pow_0002:fp_pow_inst|Add14~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][44] ; wire \fp_pow_0002:fp_pow_inst|Equal0~0 ; wire \fp_pow_0002:fp_pow_inst|Equal0~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][2]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][2]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][4]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][8]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][0]~0 ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][1]~1 ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][2]~2 ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][3]~3 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[8] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[10] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[11] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[12] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[13] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist68|delay_signals[0][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist68|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[0] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][15] ; wire \fp_pow_0002:fp_pow_inst|Add1~1 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[1] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][16] ; wire \fp_pow_0002:fp_pow_inst|Add1~2 ; wire \fp_pow_0002:fp_pow_inst|Add1~5 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[1] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][17] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[2] ; wire \fp_pow_0002:fp_pow_inst|Add1~6 ; wire \fp_pow_0002:fp_pow_inst|Add1~9 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[3] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][18] ; wire \fp_pow_0002:fp_pow_inst|Add1~10 ; wire \fp_pow_0002:fp_pow_inst|Add1~13 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[3] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][19] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[4] ; wire \fp_pow_0002:fp_pow_inst|Add1~14 ; wire \fp_pow_0002:fp_pow_inst|Add1~17 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[4] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][20] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[5] ; wire \fp_pow_0002:fp_pow_inst|Add1~18 ; wire \fp_pow_0002:fp_pow_inst|Add1~21 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[6] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][21] ; wire \fp_pow_0002:fp_pow_inst|Add1~22 ; wire \fp_pow_0002:fp_pow_inst|Add1~25 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[7] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][22] ; wire \fp_pow_0002:fp_pow_inst|Add1~26 ; wire \fp_pow_0002:fp_pow_inst|Add1~29 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[8] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][23] ; wire \fp_pow_0002:fp_pow_inst|Add1~30 ; wire \fp_pow_0002:fp_pow_inst|Add1~33 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[8] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][24] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[9] ; wire \fp_pow_0002:fp_pow_inst|Add1~34 ; wire \fp_pow_0002:fp_pow_inst|Add1~37 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[9] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][25] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[10] ; wire \fp_pow_0002:fp_pow_inst|Add1~38 ; wire \fp_pow_0002:fp_pow_inst|Add1~41 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[10] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[11] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][26] ; wire \fp_pow_0002:fp_pow_inst|Add1~42 ; wire \fp_pow_0002:fp_pow_inst|Add1~45 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[11] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][27] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[12] ; wire \fp_pow_0002:fp_pow_inst|Add1~46 ; wire \fp_pow_0002:fp_pow_inst|Add1~49 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[12] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[13] ; wire \fp_pow_0002:fp_pow_inst|Add1~50 ; wire \fp_pow_0002:fp_pow_inst|Add1~53 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[13] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[14] ; wire \fp_pow_0002:fp_pow_inst|Add1~54 ; wire \fp_pow_0002:fp_pow_inst|Add1~57 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[14] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[15] ; wire \fp_pow_0002:fp_pow_inst|Add1~58 ; wire \fp_pow_0002:fp_pow_inst|Add1~61 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[15] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[16] ; wire \fp_pow_0002:fp_pow_inst|Add1~62 ; wire \fp_pow_0002:fp_pow_inst|Add1~65 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[16] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[17] ; wire \fp_pow_0002:fp_pow_inst|Add1~66 ; wire \fp_pow_0002:fp_pow_inst|Add1~69 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[17] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[18] ; wire \fp_pow_0002:fp_pow_inst|Add1~70 ; wire \fp_pow_0002:fp_pow_inst|Add1~73 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[18] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[19] ; wire \fp_pow_0002:fp_pow_inst|Add1~74 ; wire \fp_pow_0002:fp_pow_inst|Add1~77 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[19] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|q_b[0] ; wire \fp_pow_0002:fp_pow_inst|Add1~78 ; wire \fp_pow_0002:fp_pow_inst|Add1~81 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[20] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|q_b[1] ; wire \fp_pow_0002:fp_pow_inst|Add1~82 ; wire \fp_pow_0002:fp_pow_inst|Add1~85 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[21] ; wire \fp_pow_0002:fp_pow_inst|Add1~86 ; wire \fp_pow_0002:fp_pow_inst|Add1~89 ; wire \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][3]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][4]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][5]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][8]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][9]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][9]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][11]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][11]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][12]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][13]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][14]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist67|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add2~73 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Add2~74 ; wire \fp_pow_0002:fp_pow_inst|Add2~77 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|Add2~78 ; wire \fp_pow_0002:fp_pow_inst|Add2~81 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Add2~82 ; wire \fp_pow_0002:fp_pow_inst|Add2~85 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Add2~86 ; wire \fp_pow_0002:fp_pow_inst|Add2~89 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|Add2~90 ; wire \fp_pow_0002:fp_pow_inst|Add2~93 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|Add2~94 ; wire \fp_pow_0002:fp_pow_inst|Add2~97 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|Add2~98 ; wire \fp_pow_0002:fp_pow_inst|Add2~101 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][8]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|Add2~102 ; wire \fp_pow_0002:fp_pow_inst|Add2~105 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][9]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|Add2~106 ; wire \fp_pow_0002:fp_pow_inst|Add2~109 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][10]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|Add2~110 ; wire \fp_pow_0002:fp_pow_inst|Add2~113 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][11]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][11]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|Add2~114 ; wire \fp_pow_0002:fp_pow_inst|Add2~117 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][12]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][12]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|Add2~118 ; wire \fp_pow_0002:fp_pow_inst|Add2~121 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_a0[0][0]~0 ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_a0[0][1]~1 ; wire \fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist88_cmpReg_q[0]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist88_cmpReg_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][4]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][11]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][14]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[14] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_a0[0][17]~2 ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][17]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][13]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][13]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|Add2~122 ; wire \fp_pow_0002:fp_pow_inst|Add2~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|Add2~2 ; wire \fp_pow_0002:fp_pow_inst|Add2~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][15]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][15]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|Add2~6 ; wire \fp_pow_0002:fp_pow_inst|Add2~9 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][16]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][16]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|Add2~10 ; wire \fp_pow_0002:fp_pow_inst|Add2~13 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][17]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|Add2~14 ; wire \fp_pow_0002:fp_pow_inst|Add2~17 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][18]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|Add2~18 ; wire \fp_pow_0002:fp_pow_inst|Add2~21 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|Add2~22 ; wire \fp_pow_0002:fp_pow_inst|Add2~25 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][20]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|Add2~26 ; wire \fp_pow_0002:fp_pow_inst|Add2~29 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][21]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][21]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|Add2~30 ; wire \fp_pow_0002:fp_pow_inst|Add2~33 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][22]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|Add2~34 ; wire \fp_pow_0002:fp_pow_inst|Add2~37 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][23]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|Add2~38 ; wire \fp_pow_0002:fp_pow_inst|Add2~41 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][24]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|Add2~42 ; wire \fp_pow_0002:fp_pow_inst|Add2~45 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][25]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|Add2~46 ; wire \fp_pow_0002:fp_pow_inst|Add2~49 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][26]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|Add2~50 ; wire \fp_pow_0002:fp_pow_inst|Add2~53 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|Add2~54 ; wire \fp_pow_0002:fp_pow_inst|Add2~57 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][28]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|Add2~58 ; wire \fp_pow_0002:fp_pow_inst|Add2~61 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][29]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|Add2~62 ; wire \fp_pow_0002:fp_pow_inst|Add2~65 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|Add2~66 ; wire \fp_pow_0002:fp_pow_inst|Add2~69 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_a0[0][0]~0 ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_a0[0][1]~1 ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_a0[0][17]~2 ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][26]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][24]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][22]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][20]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][16]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][16]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][15]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][14]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][14]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][12]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][12]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][10]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][9]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][8]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][4]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][4]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][2]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add3~138 ; wire \fp_pow_0002:fp_pow_inst|Add3~134 ; wire \fp_pow_0002:fp_pow_inst|Add3~130 ; wire \fp_pow_0002:fp_pow_inst|Add3~126 ; wire \fp_pow_0002:fp_pow_inst|Add3~122 ; wire \fp_pow_0002:fp_pow_inst|Add3~118 ; wire \fp_pow_0002:fp_pow_inst|Add3~114 ; wire \fp_pow_0002:fp_pow_inst|Add3~110 ; wire \fp_pow_0002:fp_pow_inst|Add3~106 ; wire \fp_pow_0002:fp_pow_inst|Add3~2 ; wire \fp_pow_0002:fp_pow_inst|Add3~6 ; wire \fp_pow_0002:fp_pow_inst|Add3~10 ; wire \fp_pow_0002:fp_pow_inst|Add3~14 ; wire \fp_pow_0002:fp_pow_inst|Add3~18 ; wire \fp_pow_0002:fp_pow_inst|Add3~22 ; wire \fp_pow_0002:fp_pow_inst|Add3~26 ; wire \fp_pow_0002:fp_pow_inst|Add3~30 ; wire \fp_pow_0002:fp_pow_inst|Add3~34 ; wire \fp_pow_0002:fp_pow_inst|Add3~38 ; wire \fp_pow_0002:fp_pow_inst|Add3~42 ; wire \fp_pow_0002:fp_pow_inst|Add3~46 ; wire \fp_pow_0002:fp_pow_inst|Add3~50 ; wire \fp_pow_0002:fp_pow_inst|Add3~54 ; wire \fp_pow_0002:fp_pow_inst|Add3~58 ; wire \fp_pow_0002:fp_pow_inst|Add3~62 ; wire \fp_pow_0002:fp_pow_inst|Add3~66 ; wire \fp_pow_0002:fp_pow_inst|Add3~70 ; wire \fp_pow_0002:fp_pow_inst|Add3~73 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|Add3~69 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][21]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|Add3~65 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][20]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|Add3~61 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][19]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|Add3~57 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][18]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|Add3~53 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|Add3~49 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][16]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|Add3~45 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|Add3~41 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|Add3~37 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][14]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|Add3~33 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][13]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|Add3~29 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|Add3~25 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|Add3~21 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|Add3~17 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][8]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|Add3~13 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|Add3~9 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|Add3~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|Add3~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|Add3~105 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Add3~109 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Add3~113 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|Add3~117 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Add3~121 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add4~158 ; wire \fp_pow_0002:fp_pow_inst|Add4~154 ; wire \fp_pow_0002:fp_pow_inst|Add4~150 ; wire \fp_pow_0002:fp_pow_inst|Add4~146 ; wire \fp_pow_0002:fp_pow_inst|Add4~142 ; wire \fp_pow_0002:fp_pow_inst|Add4~2 ; wire \fp_pow_0002:fp_pow_inst|Add4~6 ; wire \fp_pow_0002:fp_pow_inst|Add4~10 ; wire \fp_pow_0002:fp_pow_inst|Add4~14 ; wire \fp_pow_0002:fp_pow_inst|Add4~18 ; wire \fp_pow_0002:fp_pow_inst|Add4~22 ; wire \fp_pow_0002:fp_pow_inst|Add4~26 ; wire \fp_pow_0002:fp_pow_inst|Add4~30 ; wire \fp_pow_0002:fp_pow_inst|Add4~34 ; wire \fp_pow_0002:fp_pow_inst|Add4~38 ; wire \fp_pow_0002:fp_pow_inst|Add4~42 ; wire \fp_pow_0002:fp_pow_inst|Add4~46 ; wire \fp_pow_0002:fp_pow_inst|Add4~50 ; wire \fp_pow_0002:fp_pow_inst|Add4~54 ; wire \fp_pow_0002:fp_pow_inst|Add4~58 ; wire \fp_pow_0002:fp_pow_inst|Add4~62 ; wire \fp_pow_0002:fp_pow_inst|Add4~66 ; wire \fp_pow_0002:fp_pow_inst|Add4~70 ; wire \fp_pow_0002:fp_pow_inst|Add4~73 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][24]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][28]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|Add3~74 ; wire \fp_pow_0002:fp_pow_inst|Add3~77 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|Add4~74 ; wire \fp_pow_0002:fp_pow_inst|Add4~77 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][29]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|Add3~78 ; wire \fp_pow_0002:fp_pow_inst|Add3~81 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|Add4~78 ; wire \fp_pow_0002:fp_pow_inst|Add4~81 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][30]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|Add3~82 ; wire \fp_pow_0002:fp_pow_inst|Add3~85 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|Add4~82 ; wire \fp_pow_0002:fp_pow_inst|Add4~85 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][27]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][31]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|Add3~86 ; wire \fp_pow_0002:fp_pow_inst|Add3~89 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|Add4~86 ; wire \fp_pow_0002:fp_pow_inst|Add4~89 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][28]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|Add3~90 ; wire \fp_pow_0002:fp_pow_inst|Add3~93 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|Add4~90 ; wire \fp_pow_0002:fp_pow_inst|Add4~93 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][29]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][33]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|Add3~94 ; wire \fp_pow_0002:fp_pow_inst|Add3~97 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|Add4~94 ; wire \fp_pow_0002:fp_pow_inst|Add4~97 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][30]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][34]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|Add3~98 ; wire \fp_pow_0002:fp_pow_inst|Add3~101 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|Add4~98 ; wire \fp_pow_0002:fp_pow_inst|Add4~101 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|Add4~102 ; wire \fp_pow_0002:fp_pow_inst|Add4~105 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|Add4~106 ; wire \fp_pow_0002:fp_pow_inst|Add4~109 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][33]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|Add4~110 ; wire \fp_pow_0002:fp_pow_inst|Add4~113 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][34]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|Add4~114 ; wire \fp_pow_0002:fp_pow_inst|Add4~117 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|Add4~118 ; wire \fp_pow_0002:fp_pow_inst|Add4~121 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|Add4~122 ; wire \fp_pow_0002:fp_pow_inst|Add4~125 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][37]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|Add4~126 ; wire \fp_pow_0002:fp_pow_inst|Add4~129 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|Add4~130 ; wire \fp_pow_0002:fp_pow_inst|Add4~133 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][39]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|Add4~134 ; wire \fp_pow_0002:fp_pow_inst|Add4~137 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[3][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Add7~1 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[1] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[1]~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|Add7~2 ; wire \fp_pow_0002:fp_pow_inst|Add7~5 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[2] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[2]~1 ; wire \fp_pow_0002:fp_pow_inst|Add7~6 ; wire \fp_pow_0002:fp_pow_inst|Add7~9 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[3] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[3]~2 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][4]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Add7~10 ; wire \fp_pow_0002:fp_pow_inst|Add7~13 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[4] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[4]~3 ; wire \fp_pow_0002:fp_pow_inst|Add7~14 ; wire \fp_pow_0002:fp_pow_inst|Add7~17 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[5] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[5]~4 ; wire \fp_pow_0002:fp_pow_inst|Add7~18 ; wire \fp_pow_0002:fp_pow_inst|Add7~21 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[6] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[6]~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|Add7~22 ; wire \fp_pow_0002:fp_pow_inst|Add7~25 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[7] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[7]~6 ; wire \fp_pow_0002:fp_pow_inst|Add7~26 ; wire \fp_pow_0002:fp_pow_inst|Add7~29 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[8] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[8]~7 ; wire \fp_pow_0002:fp_pow_inst|Add7~30 ; wire \fp_pow_0002:fp_pow_inst|Add7~33 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[9] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[9]~8 ; wire \fp_pow_0002:fp_pow_inst|Add7~34 ; wire \fp_pow_0002:fp_pow_inst|Add7~37 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[10] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[10]~9 ; wire \fp_pow_0002:fp_pow_inst|Add7~38 ; wire \fp_pow_0002:fp_pow_inst|Add7~41 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[11] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[11]~10 ; wire \fp_pow_0002:fp_pow_inst|Add7~42 ; wire \fp_pow_0002:fp_pow_inst|Add7~45 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[12] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[12]~11 ; wire \fp_pow_0002:fp_pow_inst|Add7~46 ; wire \fp_pow_0002:fp_pow_inst|Add7~49 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[13] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[13]~12 ; wire \fp_pow_0002:fp_pow_inst|Add7~50 ; wire \fp_pow_0002:fp_pow_inst|Add7~53 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[14] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[14]~13 ; wire \fp_pow_0002:fp_pow_inst|Add7~54 ; wire \fp_pow_0002:fp_pow_inst|Add7~57 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[15] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[15]~14 ; wire \fp_pow_0002:fp_pow_inst|Add7~58 ; wire \fp_pow_0002:fp_pow_inst|Add7~61 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[16] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[16]~15 ; wire \fp_pow_0002:fp_pow_inst|Add7~62 ; wire \fp_pow_0002:fp_pow_inst|Add7~65 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[17] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[17]~16 ; wire \fp_pow_0002:fp_pow_inst|Add7~66 ; wire \fp_pow_0002:fp_pow_inst|Add7~69 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[18] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[18]~17 ; wire \fp_pow_0002:fp_pow_inst|Add7~70 ; wire \fp_pow_0002:fp_pow_inst|Add7~73 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[19] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[19]~18 ; wire \fp_pow_0002:fp_pow_inst|Add7~74 ; wire \fp_pow_0002:fp_pow_inst|Add7~77 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[20] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[20]~19 ; wire \fp_pow_0002:fp_pow_inst|Add7~78 ; wire \fp_pow_0002:fp_pow_inst|Add7~81 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[21] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[21]~20 ; wire \fp_pow_0002:fp_pow_inst|Add7~82 ; wire \fp_pow_0002:fp_pow_inst|Add7~85 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[22] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[22]~21 ; wire \fp_pow_0002:fp_pow_inst|Add7~86 ; wire \fp_pow_0002:fp_pow_inst|Add7~89 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[23] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[23]~22 ; wire \fp_pow_0002:fp_pow_inst|Add7~90 ; wire \fp_pow_0002:fp_pow_inst|Add7~93 ; wire \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[24] ; wire \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 ; wire \fp_pow_0002:fp_pow_inst|Add4~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add4~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Add4~9 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|Add4~13 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Add4~17 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Add4~21 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|Add4~25 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|Add4~29 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|Add4~33 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|Add4~37 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|Add4~41 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|Add4~45 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|Add4~49 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|Add4~53 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|Add4~57 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|Add4~61 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|Add4~65 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|Add4~69 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][35]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][59]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][59] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][58]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][58] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][57]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][57] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][56]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][56] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][4]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][55]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][55] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][54]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][54] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][53]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][53] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][52]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][52] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][51]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][51] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][33]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][32]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][50]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][50] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][49] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][31]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][30]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][48]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][48] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][47]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][47] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][29]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][46]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][46] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][45]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][45] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][44] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][43]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][25]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][42]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][24]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][41]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][22]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][40]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][39]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][21]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][19]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][36]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][35]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][16]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][34]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][33]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][14]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][32]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][31]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][30]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][11]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][10]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][28]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][27]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][26]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][8]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][25]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][24]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][23]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][4]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][2]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][20]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][18]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|Add9~94 ; wire \fp_pow_0002:fp_pow_inst|Add9~134 ; wire \fp_pow_0002:fp_pow_inst|Add9~130 ; wire \fp_pow_0002:fp_pow_inst|Add9~126 ; wire \fp_pow_0002:fp_pow_inst|Add9~122 ; wire \fp_pow_0002:fp_pow_inst|Add9~118 ; wire \fp_pow_0002:fp_pow_inst|Add9~90 ; wire \fp_pow_0002:fp_pow_inst|Add9~114 ; wire \fp_pow_0002:fp_pow_inst|Add9~110 ; wire \fp_pow_0002:fp_pow_inst|Add9~106 ; wire \fp_pow_0002:fp_pow_inst|Add9~102 ; wire \fp_pow_0002:fp_pow_inst|Add9~98 ; wire \fp_pow_0002:fp_pow_inst|Add9~22 ; wire \fp_pow_0002:fp_pow_inst|Add9~18 ; wire \fp_pow_0002:fp_pow_inst|Add9~14 ; wire \fp_pow_0002:fp_pow_inst|Add9~10 ; wire \fp_pow_0002:fp_pow_inst|Add9~6 ; wire \fp_pow_0002:fp_pow_inst|Add9~2 ; wire \fp_pow_0002:fp_pow_inst|Add9~46 ; wire \fp_pow_0002:fp_pow_inst|Add9~42 ; wire \fp_pow_0002:fp_pow_inst|Add9~38 ; wire \fp_pow_0002:fp_pow_inst|Add9~34 ; wire \fp_pow_0002:fp_pow_inst|Add9~30 ; wire \fp_pow_0002:fp_pow_inst|Add9~26 ; wire \fp_pow_0002:fp_pow_inst|Add9~54 ; wire \fp_pow_0002:fp_pow_inst|Add9~74 ; wire \fp_pow_0002:fp_pow_inst|Add9~70 ; wire \fp_pow_0002:fp_pow_inst|Add9~66 ; wire \fp_pow_0002:fp_pow_inst|Add9~62 ; wire \fp_pow_0002:fp_pow_inst|Add9~58 ; wire \fp_pow_0002:fp_pow_inst|Add9~50 ; wire \fp_pow_0002:fp_pow_inst|Add9~86 ; wire \fp_pow_0002:fp_pow_inst|Add9~82 ; wire \fp_pow_0002:fp_pow_inst|Add9~78 ; wire \fp_pow_0002:fp_pow_inst|Add9~137 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[53] ; wire \fp_pow_0002:fp_pow_inst|Add10~34 ; wire \fp_pow_0002:fp_pow_inst|Add10~10 ; wire \fp_pow_0002:fp_pow_inst|Add10~6 ; wire \fp_pow_0002:fp_pow_inst|Add10~18 ; wire \fp_pow_0002:fp_pow_inst|Add10~14 ; wire \fp_pow_0002:fp_pow_inst|Add10~30 ; wire \fp_pow_0002:fp_pow_inst|Add10~26 ; wire \fp_pow_0002:fp_pow_inst|Add10~22 ; wire \fp_pow_0002:fp_pow_inst|Add10~1 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[8] ; wire \fp_pow_0002:fp_pow_inst|Add14~113 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|Add14~117 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|Add14~121 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|Add14~101 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|Add14~125 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|Add10~21 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[7] ; wire \fp_pow_0002:fp_pow_inst|Add14~129 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|Add14~133 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|Add10~25 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[6] ; wire \fp_pow_0002:fp_pow_inst|Add14~137 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|Add10~29 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[5] ; wire \fp_pow_0002:fp_pow_inst|Add14~105 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|Add10~13 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[4] ; wire \fp_pow_0002:fp_pow_inst|Add14~109 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|Add10~17 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[3] ; wire \fp_pow_0002:fp_pow_inst|Add14~81 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|Add10~5 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[2] ; wire \fp_pow_0002:fp_pow_inst|Add14~85 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|Add10~9 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[1] ; wire \fp_pow_0002:fp_pow_inst|Add14~89 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|Add9~77 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[52] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][51] ; wire \fp_pow_0002:fp_pow_inst|Add9~81 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[51] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][50] ; wire \fp_pow_0002:fp_pow_inst|Add14~93 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|Add9~85 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[50] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][49]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][49]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Add14~97 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|Add14~53 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|Add9~49 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[49] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][48]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][48] ; wire \fp_pow_0002:fp_pow_inst|Add9~57 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[48] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][47] ; wire \fp_pow_0002:fp_pow_inst|Add14~61 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|Add14~65 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|Add9~61 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[47] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][46] ; wire \fp_pow_0002:fp_pow_inst|Add9~65 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[46] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][45]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][45] ; wire \fp_pow_0002:fp_pow_inst|Add14~69 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|Add9~69 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[45] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][44]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][44] ; wire \fp_pow_0002:fp_pow_inst|Add14~73 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|Add9~73 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[44] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|Add14~77 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|Add14~57 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|Add9~53 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[43] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][42]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Add14~29 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|Add9~25 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[42] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][41]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|Add14~33 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|Add9~29 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[41] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|Add9~33 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[40] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|Add14~37 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|Add9~37 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|Add14~41 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|Add14~45 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|Add9~41 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][37]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|Add9~45 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|Add14~49 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|Add9~1 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|Add14~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|Add9~5 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][34]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|Add14~9 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|Add14~13 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|Add9~9 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|Add9~13 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][32]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|Add14~17 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|Add14~21 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|Add9~17 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|Add14~25 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|Add9~21 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|Add9~97 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|Add14~141 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|Add14~145 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|Add9~101 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][28]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|Add14~149 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|Add9~105 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|Ram0~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|Add9~109 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][26]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|Add9~113 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][25]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|Ram0~2 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|Ram0~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Add9~89 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|Add9~117 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][23]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|Ram0~3 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Add9~121 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|Ram0~4 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][2]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|Add9~125 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Add15~178 ; wire \fp_pow_0002:fp_pow_inst|Add15~174 ; wire \fp_pow_0002:fp_pow_inst|Add15~170 ; wire \fp_pow_0002:fp_pow_inst|Add15~146 ; wire \fp_pow_0002:fp_pow_inst|Add15~166 ; wire \fp_pow_0002:fp_pow_inst|Add15~162 ; wire \fp_pow_0002:fp_pow_inst|Add15~158 ; wire \fp_pow_0002:fp_pow_inst|Add15~154 ; wire \fp_pow_0002:fp_pow_inst|Add15~150 ; wire \fp_pow_0002:fp_pow_inst|Add15~26 ; wire \fp_pow_0002:fp_pow_inst|Add15~22 ; wire \fp_pow_0002:fp_pow_inst|Add15~18 ; wire \fp_pow_0002:fp_pow_inst|Add15~14 ; wire \fp_pow_0002:fp_pow_inst|Add15~10 ; wire \fp_pow_0002:fp_pow_inst|Add15~6 ; wire \fp_pow_0002:fp_pow_inst|Add15~50 ; wire \fp_pow_0002:fp_pow_inst|Add15~46 ; wire \fp_pow_0002:fp_pow_inst|Add15~42 ; wire \fp_pow_0002:fp_pow_inst|Add15~38 ; wire \fp_pow_0002:fp_pow_inst|Add15~34 ; wire \fp_pow_0002:fp_pow_inst|Add15~30 ; wire \fp_pow_0002:fp_pow_inst|Add15~58 ; wire \fp_pow_0002:fp_pow_inst|Add15~78 ; wire \fp_pow_0002:fp_pow_inst|Add15~74 ; wire \fp_pow_0002:fp_pow_inst|Add15~70 ; wire \fp_pow_0002:fp_pow_inst|Add15~66 ; wire \fp_pow_0002:fp_pow_inst|Add15~62 ; wire \fp_pow_0002:fp_pow_inst|Add15~54 ; wire \fp_pow_0002:fp_pow_inst|Add15~98 ; wire \fp_pow_0002:fp_pow_inst|Add15~94 ; wire \fp_pow_0002:fp_pow_inst|Add15~90 ; wire \fp_pow_0002:fp_pow_inst|Add15~86 ; wire \fp_pow_0002:fp_pow_inst|Add15~82 ; wire \fp_pow_0002:fp_pow_inst|Add15~110 ; wire \fp_pow_0002:fp_pow_inst|Add15~106 ; wire \fp_pow_0002:fp_pow_inst|Add15~142 ; wire \fp_pow_0002:fp_pow_inst|Add15~138 ; wire \fp_pow_0002:fp_pow_inst|Add15~134 ; wire \fp_pow_0002:fp_pow_inst|Add15~130 ; wire \fp_pow_0002:fp_pow_inst|Add15~102 ; wire \fp_pow_0002:fp_pow_inst|Add15~126 ; wire \fp_pow_0002:fp_pow_inst|Add15~122 ; wire \fp_pow_0002:fp_pow_inst|Add15~118 ; wire \fp_pow_0002:fp_pow_inst|Add15~114 ; wire \fp_pow_0002:fp_pow_inst|Add15~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[4][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[3][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ; wire \fp_pow_0002:fp_pow_inst|Add15~37 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[19]~feeder ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[19] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|Add15~41 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[18]~feeder ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[18] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|Add15~45 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[17]~feeder ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[17] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|Add15~49 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[16]~feeder ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[16] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|Add15~5 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[15]~feeder ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[15] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|Add15~9 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[14]~feeder ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[14] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|Add15~13 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[13]~feeder ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[13] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|Add15~17 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[12]~feeder ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[12] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|Add15~21 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[11]~feeder ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[11] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|Add15~25 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[10] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|Add15~149 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[9] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|Add15~153 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[8] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|Add15~157 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[7] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|Add15~161 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[6] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|Add15~165 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[5] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|Add15~145 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[4] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|Add15~169 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[3] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|Add15~173 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[2] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|Add15~177 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[1] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|Add9~129 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[0] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|Add9~133 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|Add9~93 ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][15]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][13]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[14]~feeder ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][10]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][10]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist107|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add18~206 ; wire \fp_pow_0002:fp_pow_inst|Add18~202 ; wire \fp_pow_0002:fp_pow_inst|Add18~198 ; wire \fp_pow_0002:fp_pow_inst|Add18~102 ; wire \fp_pow_0002:fp_pow_inst|Add18~98 ; wire \fp_pow_0002:fp_pow_inst|Add18~94 ; wire \fp_pow_0002:fp_pow_inst|Add18~90 ; wire \fp_pow_0002:fp_pow_inst|Add18~122 ; wire \fp_pow_0002:fp_pow_inst|Add18~118 ; wire \fp_pow_0002:fp_pow_inst|Add18~114 ; wire \fp_pow_0002:fp_pow_inst|Add18~110 ; wire \fp_pow_0002:fp_pow_inst|Add18~106 ; wire \fp_pow_0002:fp_pow_inst|Add18~134 ; wire \fp_pow_0002:fp_pow_inst|Add18~154 ; wire \fp_pow_0002:fp_pow_inst|Add18~150 ; wire \fp_pow_0002:fp_pow_inst|Add18~146 ; wire \fp_pow_0002:fp_pow_inst|Add18~142 ; wire \fp_pow_0002:fp_pow_inst|Add18~138 ; wire \fp_pow_0002:fp_pow_inst|Add18~130 ; wire \fp_pow_0002:fp_pow_inst|Add18~194 ; wire \fp_pow_0002:fp_pow_inst|Add18~190 ; wire \fp_pow_0002:fp_pow_inst|Add18~186 ; wire \fp_pow_0002:fp_pow_inst|Add18~182 ; wire \fp_pow_0002:fp_pow_inst|Add18~178 ; wire \fp_pow_0002:fp_pow_inst|Add18~126 ; wire \fp_pow_0002:fp_pow_inst|Add18~174 ; wire \fp_pow_0002:fp_pow_inst|Add18~170 ; wire \fp_pow_0002:fp_pow_inst|Add18~166 ; wire \fp_pow_0002:fp_pow_inst|Add18~162 ; wire \fp_pow_0002:fp_pow_inst|Add18~158 ; wire \fp_pow_0002:fp_pow_inst|Add18~22 ; wire \fp_pow_0002:fp_pow_inst|Add18~18 ; wire \fp_pow_0002:fp_pow_inst|Add18~14 ; wire \fp_pow_0002:fp_pow_inst|Add18~10 ; wire \fp_pow_0002:fp_pow_inst|Add18~6 ; wire \fp_pow_0002:fp_pow_inst|Add18~2 ; wire \fp_pow_0002:fp_pow_inst|Add18~46 ; wire \fp_pow_0002:fp_pow_inst|Add18~42 ; wire \fp_pow_0002:fp_pow_inst|Add18~38 ; wire \fp_pow_0002:fp_pow_inst|Add18~33 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[40] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][39]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|Add18~41 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|Add18~37 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][38]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][38]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Add15~33 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[20]~feeder ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[20] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[40] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|Add18~34 ; wire \fp_pow_0002:fp_pow_inst|Add18~29 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[41] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|Add18~45 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|Add15~29 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[21]~feeder ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[21] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[41] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|Add18~30 ; wire \fp_pow_0002:fp_pow_inst|Add18~25 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[42] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][41]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|Equal9~1 ; wire \fp_pow_0002:fp_pow_inst|Add18~149 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][14]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|Add18~153 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][13]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|Add18~137 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][17]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][17]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Add18~141 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|Add18~145 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][15]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|Equal9~9 ; wire \fp_pow_0002:fp_pow_inst|Add18~185 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|Add18~193 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][19]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|Add18~177 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|Add18~181 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|Add18~189 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|Equal9~11 ; wire \fp_pow_0002:fp_pow_inst|Add18~133 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|Add18~125 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|Add18~129 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|Add18~169 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][26]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|Add18~157 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][29]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|Add18~165 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][27]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|Add18~161 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|Add18~173 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|Equal9~10 ; wire \fp_pow_0002:fp_pow_inst|Equal9~12 ; wire \fp_pow_0002:fp_pow_inst|Add18~101 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Add18~97 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Add18~121 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|Add18~113 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|Add18~117 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|Add18~109 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|Add18~105 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|Equal9~8 ; wire \fp_pow_0002:fp_pow_inst|Add18~93 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|Add18~89 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|Equal9~13 ; wire \fp_pow_0002:fp_pow_inst|Add18~21 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][30]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|Add18~9 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|Add18~17 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|Add18~13 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][32]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|Add18~5 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|Add18~1 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|Equal9~0 ; wire \fp_pow_0002:fp_pow_inst|Add15~105 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[35] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[55] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][55] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Add15~109 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[34] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[54] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][54] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|Add15~81 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[33] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[53] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][53] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Add15~85 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[32] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[52] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][52] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add15~89 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[31] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[51] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][51] ; wire \fp_pow_0002:fp_pow_inst|Add15~93 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[30]~feeder ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[30] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[50] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][50] ; wire \fp_pow_0002:fp_pow_inst|Add15~97 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[29]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][49] ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[29] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[49] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][49] ; wire \fp_pow_0002:fp_pow_inst|Add15~53 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[28]~feeder ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[28] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[48] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][48] ; wire \fp_pow_0002:fp_pow_inst|Add15~61 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[27]~feeder ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[27] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[47] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][47] ; wire \fp_pow_0002:fp_pow_inst|Add15~65 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[26]~feeder ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[26] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[46] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][46] ; wire \fp_pow_0002:fp_pow_inst|Add15~69 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[25]~feeder ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[25] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[45] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][45] ; wire \fp_pow_0002:fp_pow_inst|Add15~73 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[24]~feeder ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[24] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[44] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][44] ; wire \fp_pow_0002:fp_pow_inst|Add15~77 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[23]~feeder ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[23] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[43] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|Add15~57 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[22]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[22] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[42] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|Add18~26 ; wire \fp_pow_0002:fp_pow_inst|Add18~54 ; wire \fp_pow_0002:fp_pow_inst|Add18~74 ; wire \fp_pow_0002:fp_pow_inst|Add18~70 ; wire \fp_pow_0002:fp_pow_inst|Add18~66 ; wire \fp_pow_0002:fp_pow_inst|Add18~62 ; wire \fp_pow_0002:fp_pow_inst|Add18~58 ; wire \fp_pow_0002:fp_pow_inst|Add18~50 ; wire \fp_pow_0002:fp_pow_inst|Add18~86 ; wire \fp_pow_0002:fp_pow_inst|Add18~82 ; wire \fp_pow_0002:fp_pow_inst|Add18~78 ; wire \fp_pow_0002:fp_pow_inst|Add18~209 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[53] ; wire \fp_pow_0002:fp_pow_inst|Add19~6 ; wire \fp_pow_0002:fp_pow_inst|Add19~2 ; wire \fp_pow_0002:fp_pow_inst|Add19~18 ; wire \fp_pow_0002:fp_pow_inst|Add19~13 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[4] ; wire \fp_pow_0002:fp_pow_inst|Add15~101 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[40] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[60] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][60] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|Add15~129 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[39] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[59] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][59] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|Add15~133 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[38] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[58] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][58] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|Add15~137 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[37] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[57] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][57] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|Add15~141 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[36] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[56] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][56] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Add19~14 ; wire \fp_pow_0002:fp_pow_inst|Add19~54 ; wire \fp_pow_0002:fp_pow_inst|Add19~50 ; wire \fp_pow_0002:fp_pow_inst|Add19~46 ; wire \fp_pow_0002:fp_pow_inst|Add19~42 ; wire \fp_pow_0002:fp_pow_inst|Add19~9 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[9] ; wire \fp_pow_0002:fp_pow_inst|Add15~117 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[43] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[63] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][63] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|Add15~121 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[42] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[62] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][62] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|Add15~125 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[41] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[61] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][61] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|Add19~10 ; wire \fp_pow_0002:fp_pow_inst|Add19~38 ; wire \fp_pow_0002:fp_pow_inst|Add19~34 ; wire \fp_pow_0002:fp_pow_inst|Add19~29 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[12] ; wire \fp_pow_0002:fp_pow_inst|Add19~33 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[11] ; wire \fp_pow_0002:fp_pow_inst|Add19~37 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[10] ; wire \fp_pow_0002:fp_pow_inst|Add15~113 ; wire \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[44] ; wire \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[64] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][64] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|Add19~30 ; wire \fp_pow_0002:fp_pow_inst|Add19~25 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[13] ; wire \fp_pow_0002:fp_pow_inst|Add19~26 ; wire \fp_pow_0002:fp_pow_inst|Add19~21 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[14]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Equal9~4 ; wire \fp_pow_0002:fp_pow_inst|Add19~17 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[3] ; wire \fp_pow_0002:fp_pow_inst|Add19~45 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[7] ; wire \fp_pow_0002:fp_pow_inst|Add19~41 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[8] ; wire \fp_pow_0002:fp_pow_inst|Add19~53 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[5]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Add19~49 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[6] ; wire \fp_pow_0002:fp_pow_inst|Equal9~5 ; wire \fp_pow_0002:fp_pow_inst|Equal9~6 ; wire \fp_pow_0002:fp_pow_inst|Add18~69 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[45] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][44] ; wire \fp_pow_0002:fp_pow_inst|Add18~57 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[48] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][47] ; wire \fp_pow_0002:fp_pow_inst|Add18~73 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[44] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][43]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|Add18~65 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[46] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][45]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Add18~61 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[47] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][46] ; wire \fp_pow_0002:fp_pow_inst|Equal9~2 ; wire \fp_pow_0002:fp_pow_inst|Add19~5 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[1] ; wire \fp_pow_0002:fp_pow_inst|Add19~1 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[2] ; wire \fp_pow_0002:fp_pow_inst|Add18~77 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[52] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][51] ; wire \fp_pow_0002:fp_pow_inst|Add18~81 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[51] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][50]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][50] ; wire \fp_pow_0002:fp_pow_inst|Add18~85 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[50] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][49] ; wire \fp_pow_0002:fp_pow_inst|Equal9~3 ; wire \fp_pow_0002:fp_pow_inst|Add18~53 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[43] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|Add18~49 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[49] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][48]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Equal9~7 ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[20]~21 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[27]~26 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[14] ; wire \fp_pow_0002:fp_pow_inst|Add18~201 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[30]~23 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|Add18~197 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][2]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[31]~22 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|Add18~205 ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[29]~24 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[28]~25 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|Equal10~3 ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[24]~28 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][24]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[22]~30 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[25]~27 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][25]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[5] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[21]~31 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[23]~29 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|Equal10~4 ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[26]~20 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|Equal10~5 ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[12]~16 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[13]~15 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[9]~19 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][9]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][45] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[10]~18 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[11]~17 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|Equal10~2 ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[8]~9 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[14]~8 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[15]~14 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[16]~13 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][16]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[19]~10 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[18]~11 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[17]~12 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|Equal10~1 ; wire \fp_pow_0002:fp_pow_inst|Equal10~6 ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[1]~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][40]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[5]~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[7]~3 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[4]~6 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][41]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[6]~4 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[3]~7 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Equal10~0 ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[0]~2 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[2]~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|Equal10~7 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[31]~2 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][31]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[15]~2 ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[17]~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[1]~0 ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[27]~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][27]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][27]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[11]~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][29]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[29]~3 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][29]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[13]~3 ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[30]~15 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[14]~14 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][21]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[21]~13 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[5]~12 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[28]~14 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[12]~13 ; wire \fp_pow_0002:fp_pow_inst|Equal11~2 ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[18]~7 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[2]~7 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][24]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[24]~4 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][24]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[8]~4 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[19]~6 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[3]~6 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][20]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[20]~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][20]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[4]~5 ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[26]~10 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[10]~10 ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[23]~8 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[7]~8 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[25]~11 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[9]~11 ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[16]~12 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[22]~9 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[6]~9 ; wire \fp_pow_0002:fp_pow_inst|Equal11~0 ; wire \fp_pow_0002:fp_pow_inst|Equal11~1 ; wire \fp_pow_0002:fp_pow_inst|Equal11~3 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid300_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[7]~26 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][15]~feeder ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[15]~20 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][10]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][10]~feeder ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[10]~17 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][14]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][14]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[14]~21 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][12]~feeder ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[12]~23 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][12]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][13]~feeder ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[13]~22 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][13]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Equal12~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][8]~feeder ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[8]~19 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][9]~feeder ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[9]~18 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|Equal12~1 ; wire \fp_pow_0002:fp_pow_inst|Equal12~2 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][11]~feeder ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[11]~16 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|Equal12~3 ; wire \rtl~140 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[6]~27 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][6] ; wire \rtl~141 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][4]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][4]~feeder ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[4]~25 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][4]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][4] ; wire \rtl~143 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[5]~24 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][5] ; wire \rtl~142 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Equal13~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][2]~feeder ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[2]~29 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][2] ; wire \rtl~145 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][3]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[3]~28 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][3] ; wire \rtl~144 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][3]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Equal14~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist52|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist54|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist56|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist56|delay_signals[0][0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist58|delay_signals[1][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist58|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist58|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Add20~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist61|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist61|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist61|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|Equal9~14 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[4][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[3][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|Add20~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|Add20~2 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|Add20~3 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|Add20~4 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|Add20~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|Add20~6 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[1]~30 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][1] ; wire \rtl~234 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][1] ; wire \rtl~148 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid324_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][34]~3 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist56|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~1 ; wire \fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0]~0 ; wire \fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[42] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|Mux34~0 ; wire \rtl~288 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[58] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][58] ; wire \rtl~295 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][18]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[50] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][50] ; wire \rtl~294 ; wire \rtl~296 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[58] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[56] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][56] ; wire \fp_pow_0002:fp_pow_inst|Mux20~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][48] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[48] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][48] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|Mux28~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[40] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|Mux36~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[4][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[3][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[64] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][64] ; wire \rtl~286 ; wire \rtl~179 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[64] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[44] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][44] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|Mux32~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[60] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][60] ; wire \rtl~289 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][20]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[52] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][52] ; wire \rtl~287 ; wire \rtl~290 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[54] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][54] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][6] ; wire \rtl~291 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[62] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][62] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[46] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][46] ; wire \fp_pow_0002:fp_pow_inst|Mux30~0 ; wire \rtl~292 ; wire \rtl~293 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[62] ; wire \rtl~147 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[57] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][57] ; wire \fp_pow_0002:fp_pow_inst|Mux19~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[49] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][49] ; wire \fp_pow_0002:fp_pow_inst|Mux27~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[4][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[4][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[3][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[2][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[65] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][65] ; wire \rtl~297 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[41] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|Mux35~0 ; wire \rtl~153 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[65] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[45] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][45] ; wire \fp_pow_0002:fp_pow_inst|Mux31~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[61] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][61] ; wire \rtl~299 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[53] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][53] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][21] ; wire \rtl~298 ; wire \rtl~300 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[61] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[51] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][51] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][19] ; wire \rtl~304 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[59] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][59] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[43] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|Mux33~0 ; wire \rtl~305 ; wire \rtl~306 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[59] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[47] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][47] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|Mux29~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[63] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][63] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][31] ; wire \rtl~302 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[55] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][55] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][23] ; wire \rtl~301 ; wire \rtl~303 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[63] ; wire \rtl~146 ; wire \fp_pow_0002:fp_pow_inst|expFracConc_uid87_fpPowrTest_q[33]~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][1] ; wire \rtl~307 ; wire \rtl~237 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[57] ; wire \rtl~201 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][0] ; wire \rtl~308 ; wire \rtl~252 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[56] ; wire \rtl~214 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|Mux37~0 ; wire \fp_pow_0002:fp_pow_inst|Mux45~0 ; wire \fp_pow_0002:fp_pow_inst|Mux21~0 ; wire \rtl~251 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[55] ; wire \rtl~213 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|Mux46~0 ; wire \fp_pow_0002:fp_pow_inst|Mux38~0 ; wire \fp_pow_0002:fp_pow_inst|Mux22~0 ; wire \rtl~250 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[54] ; wire \rtl~212 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|Mux23~0 ; wire \fp_pow_0002:fp_pow_inst|Mux47~0 ; wire \fp_pow_0002:fp_pow_inst|Mux39~0 ; wire \rtl~249 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[53] ; wire \rtl~211 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|Mux48~0 ; wire \fp_pow_0002:fp_pow_inst|Mux24~0 ; wire \fp_pow_0002:fp_pow_inst|Mux40~0 ; wire \rtl~248 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[52] ; wire \rtl~210 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|Mux25~0 ; wire \fp_pow_0002:fp_pow_inst|Mux41~0 ; wire \fp_pow_0002:fp_pow_inst|Mux49~0 ; wire \rtl~238 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[51] ; wire \rtl~209 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|Mux42~0 ; wire \fp_pow_0002:fp_pow_inst|Mux26~0 ; wire \fp_pow_0002:fp_pow_inst|Mux50~0 ; wire \rtl~242 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[50] ; wire \rtl~208 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|Mux51~0 ; wire \rtl~240 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[49] ; wire \rtl~207 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|Mux52~0 ; wire \rtl~246 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[48] ; wire \rtl~206 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|Mux53~0 ; wire \rtl~239 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[47] ; wire \rtl~205 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|Mux54~0 ; wire \rtl~243 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[46] ; wire \rtl~204 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|Mux55~0 ; wire \rtl~241 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[45] ; wire \rtl~202 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|Mux56~0 ; wire \rtl~247 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[44] ; wire \rtl~203 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|Mux57~0 ; wire \rtl~272 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[43] ; wire \rtl~233 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|Mux58~0 ; wire \rtl~271 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[42] ; wire \rtl~232 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|Mux59~0 ; wire \rtl~270 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[41] ; wire \rtl~231 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][16]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Mux60~0 ; wire \rtl~269 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[40] ; wire \rtl~230 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][15] ; wire \rtl~311 ; wire \fp_pow_0002:fp_pow_inst|Mux102~0 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[39] ; wire \rtl~229 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][14] ; wire \rtl~314 ; wire \fp_pow_0002:fp_pow_inst|Mux103~0 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[38] ; wire \rtl~228 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][13] ; wire \rtl~310 ; wire \fp_pow_0002:fp_pow_inst|Mux104~0 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[37] ; wire \rtl~227 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][12] ; wire \rtl~313 ; wire \fp_pow_0002:fp_pow_inst|Mux105~0 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[36] ; wire \rtl~226 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][11] ; wire \rtl~312 ; wire \fp_pow_0002:fp_pow_inst|Mux106~0 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[35] ; wire \rtl~225 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][10] ; wire \rtl~315 ; wire \fp_pow_0002:fp_pow_inst|Mux107~0 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[34] ; wire \rtl~224 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][9] ; wire \rtl~309 ; wire \fp_pow_0002:fp_pow_inst|Mux108~0 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[33] ; wire \rtl~223 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|Mux109~0 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[32] ; wire \rtl~222 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~3 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~2 ; wire \fp_pow_0002:fp_pow_inst|Mux110~0 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[31] ; wire \rtl~221 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|Mux111~0 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[30] ; wire \rtl~220 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|Mux112~0 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29] ; wire \rtl~219 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Mux113~0 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][2] ; wire \rtl~218 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Mux114~0 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[27] ; wire \rtl~215 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][17]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Mux116~0 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[25] ; wire \rtl~217 ; wire \fp_pow_0002:fp_pow_inst|Mux115~0 ; wire \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[26] ; wire \rtl~216 ; wire \fp_pow_0002:fp_pow_inst|expFracConc_uid87_fpPowrTest_q[0]~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Add23~98 ; wire \fp_pow_0002:fp_pow_inst|Add23~102 ; wire \fp_pow_0002:fp_pow_inst|Add23~106 ; wire \fp_pow_0002:fp_pow_inst|Add23~110 ; wire \fp_pow_0002:fp_pow_inst|Add23~114 ; wire \fp_pow_0002:fp_pow_inst|Add23~118 ; wire \fp_pow_0002:fp_pow_inst|Add23~122 ; wire \fp_pow_0002:fp_pow_inst|Add23~126 ; wire \fp_pow_0002:fp_pow_inst|Add23~130 ; wire \fp_pow_0002:fp_pow_inst|Add23~134 ; wire \fp_pow_0002:fp_pow_inst|Add23~138 ; wire \fp_pow_0002:fp_pow_inst|Add23~142 ; wire \fp_pow_0002:fp_pow_inst|Add23~146 ; wire \fp_pow_0002:fp_pow_inst|Add23~150 ; wire \fp_pow_0002:fp_pow_inst|Add23~154 ; wire \fp_pow_0002:fp_pow_inst|Add23~158 ; wire \fp_pow_0002:fp_pow_inst|Add23~162 ; wire \fp_pow_0002:fp_pow_inst|Add23~166 ; wire \fp_pow_0002:fp_pow_inst|Add23~46 ; wire \fp_pow_0002:fp_pow_inst|Add23~50 ; wire \fp_pow_0002:fp_pow_inst|Add23~54 ; wire \fp_pow_0002:fp_pow_inst|Add23~58 ; wire \fp_pow_0002:fp_pow_inst|Add23~62 ; wire \fp_pow_0002:fp_pow_inst|Add23~66 ; wire \fp_pow_0002:fp_pow_inst|Add23~70 ; wire \fp_pow_0002:fp_pow_inst|Add23~74 ; wire \fp_pow_0002:fp_pow_inst|Add23~78 ; wire \fp_pow_0002:fp_pow_inst|Add23~82 ; wire \fp_pow_0002:fp_pow_inst|Add23~86 ; wire \fp_pow_0002:fp_pow_inst|Add23~90 ; wire \fp_pow_0002:fp_pow_inst|Add23~94 ; wire \fp_pow_0002:fp_pow_inst|Add23~42 ; wire \fp_pow_0002:fp_pow_inst|Add23~30 ; wire \fp_pow_0002:fp_pow_inst|Add23~22 ; wire \fp_pow_0002:fp_pow_inst|Add23~38 ; wire \fp_pow_0002:fp_pow_inst|Add23~34 ; wire \fp_pow_0002:fp_pow_inst|Add23~26 ; wire \fp_pow_0002:fp_pow_inst|Add23~18 ; wire \fp_pow_0002:fp_pow_inst|Add23~14 ; wire \fp_pow_0002:fp_pow_inst|Add23~10 ; wire \fp_pow_0002:fp_pow_inst|Add23~6 ; wire \fp_pow_0002:fp_pow_inst|Add23~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|Add23~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|Add23~9 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|Add23~13 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|Add23~17 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Add23~25 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Add23~33 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|Add23~37 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Add23~21 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add33~22 ; wire \fp_pow_0002:fp_pow_inst|Add33~38 ; wire \fp_pow_0002:fp_pow_inst|Add33~30 ; wire \fp_pow_0002:fp_pow_inst|Add33~34 ; wire \fp_pow_0002:fp_pow_inst|Add33~26 ; wire \fp_pow_0002:fp_pow_inst|Add33~18 ; wire \fp_pow_0002:fp_pow_inst|Add33~14 ; wire \fp_pow_0002:fp_pow_inst|Add33~10 ; wire \fp_pow_0002:fp_pow_inst|Add33~6 ; wire \fp_pow_0002:fp_pow_inst|Add33~1 ; wire \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[9] ; wire \fp_pow_0002:fp_pow_inst|Add33~5 ; wire \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[8] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[8] ; wire \fp_pow_0002:fp_pow_inst|Add33~9 ; wire \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[7] ; wire \fp_pow_0002:fp_pow_inst|Add33~13 ; wire \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[6] ; wire \fp_pow_0002:fp_pow_inst|Add33~17 ; wire \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[5] ; wire \fp_pow_0002:fp_pow_inst|Add33~25 ; wire \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[4] ; wire \fp_pow_0002:fp_pow_inst|Add33~33 ; wire \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[3] ; wire \fp_pow_0002:fp_pow_inst|Add33~29 ; wire \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[2] ; wire \fp_pow_0002:fp_pow_inst|Add33~37 ; wire \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[1] ; wire \fp_pow_0002:fp_pow_inst|Add33~21 ; wire \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][6]~0 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][7]~1 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][8]~2 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][9]~3 ; wire \fp_pow_0002:fp_pow_inst|Add23~45 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|Add23~49 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|Add23~53 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|Add23~57 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|Add23~61 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|Add23~65 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|Add23~69 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|Add23~73 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|Add23~77 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|Add23~81 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|Add23~85 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|Add23~89 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|Add23~93 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|Add23~41 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|Add23~29 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][57] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_c0[1][18]~0 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][6]~0 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][7]~1 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][8]~2 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][9]~3 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][10]~4 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][11]~5 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][12]~6 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][13]~7 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][14]~8 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][15]~9 ; wire \fp_pow_0002:fp_pow_inst|Add23~97 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Add23~101 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Add23~105 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|Add23~109 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Add23~113 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Add23~117 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|Add23~121 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|Add23~125 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|Add23~129 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|Add23~133 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|Add23~137 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|Add23~141 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|Add23~145 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|Add23~149 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|Add23~153 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|Add23~157 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|Add23~161 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|Add23~165 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_c0[0][18]~1 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist4|delay_signals[0][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist4|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][56] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][55] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][54] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][53]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][53] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][34]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist4|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][52] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][33]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][51]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][51] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][50]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][50] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][49] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][48] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][47] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][46]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][46] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][28]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][45] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][44] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][42]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][41]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][37]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][17]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][13]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][35]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][16]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][33]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][15]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][32]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][31]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][13]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][12]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][11]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][28]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][10]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][9]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][27]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][8]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][25]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][24]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][22]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][21]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][18]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add25~138 ; wire \fp_pow_0002:fp_pow_inst|Add25~134 ; wire \fp_pow_0002:fp_pow_inst|Add25~130 ; wire \fp_pow_0002:fp_pow_inst|Add25~126 ; wire \fp_pow_0002:fp_pow_inst|Add25~122 ; wire \fp_pow_0002:fp_pow_inst|Add25~102 ; wire \fp_pow_0002:fp_pow_inst|Add25~106 ; wire \fp_pow_0002:fp_pow_inst|Add25~114 ; wire \fp_pow_0002:fp_pow_inst|Add25~118 ; wire \fp_pow_0002:fp_pow_inst|Add25~110 ; wire \fp_pow_0002:fp_pow_inst|Add25~98 ; wire \fp_pow_0002:fp_pow_inst|Add25~94 ; wire \fp_pow_0002:fp_pow_inst|Add25~90 ; wire \fp_pow_0002:fp_pow_inst|Add25~86 ; wire \fp_pow_0002:fp_pow_inst|Add25~82 ; wire \fp_pow_0002:fp_pow_inst|Add25~78 ; wire \fp_pow_0002:fp_pow_inst|Add25~74 ; wire \fp_pow_0002:fp_pow_inst|Add25~70 ; wire \fp_pow_0002:fp_pow_inst|Add25~66 ; wire \fp_pow_0002:fp_pow_inst|Add25~62 ; wire \fp_pow_0002:fp_pow_inst|Add25~54 ; wire \fp_pow_0002:fp_pow_inst|Add25~50 ; wire \fp_pow_0002:fp_pow_inst|Add25~2 ; wire \fp_pow_0002:fp_pow_inst|Add25~6 ; wire \fp_pow_0002:fp_pow_inst|Add25~26 ; wire \fp_pow_0002:fp_pow_inst|Add25~30 ; wire \fp_pow_0002:fp_pow_inst|Add25~18 ; wire \fp_pow_0002:fp_pow_inst|Add25~22 ; wire \fp_pow_0002:fp_pow_inst|Add25~42 ; wire \fp_pow_0002:fp_pow_inst|Add25~46 ; wire \fp_pow_0002:fp_pow_inst|Add25~10 ; wire \fp_pow_0002:fp_pow_inst|Add25~14 ; wire \fp_pow_0002:fp_pow_inst|Add25~34 ; wire \fp_pow_0002:fp_pow_inst|Add25~38 ; wire \fp_pow_0002:fp_pow_inst|Add25~57 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[53] ; wire \fp_pow_0002:fp_pow_inst|Add26~26 ; wire \fp_pow_0002:fp_pow_inst|Add26~6 ; wire \fp_pow_0002:fp_pow_inst|Add26~10 ; wire \fp_pow_0002:fp_pow_inst|Add26~14 ; wire \fp_pow_0002:fp_pow_inst|Add26~18 ; wire \fp_pow_0002:fp_pow_inst|Add26~22 ; wire \fp_pow_0002:fp_pow_inst|Add26~1 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ; wire \fp_pow_0002:fp_pow_inst|Add34~22 ; wire \fp_pow_0002:fp_pow_inst|Add34~38 ; wire \fp_pow_0002:fp_pow_inst|Add34~30 ; wire \fp_pow_0002:fp_pow_inst|Add34~34 ; wire \fp_pow_0002:fp_pow_inst|Add34~42 ; wire \fp_pow_0002:fp_pow_inst|Add34~26 ; wire \fp_pow_0002:fp_pow_inst|Add34~18 ; wire \fp_pow_0002:fp_pow_inst|Add34~14 ; wire \fp_pow_0002:fp_pow_inst|Add34~10 ; wire \fp_pow_0002:fp_pow_inst|Add34~6 ; wire \fp_pow_0002:fp_pow_inst|Add34~1 ; wire \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[10] ; wire \fp_pow_0002:fp_pow_inst|Add34~5 ; wire \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[9] ; wire \fp_pow_0002:fp_pow_inst|Add34~9 ; wire \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[8] ; wire \fp_pow_0002:fp_pow_inst|Add34~13 ; wire \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[7] ; wire \fp_pow_0002:fp_pow_inst|Add34~17 ; wire \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[6] ; wire \fp_pow_0002:fp_pow_inst|Add34~25 ; wire \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[5] ; wire \fp_pow_0002:fp_pow_inst|Add34~41 ; wire \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[4] ; wire \fp_pow_0002:fp_pow_inst|Add34~33 ; wire \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[3] ; wire \fp_pow_0002:fp_pow_inst|Add34~29 ; wire \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[2] ; wire \fp_pow_0002:fp_pow_inst|Add34~37 ; wire \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[1] ; wire \fp_pow_0002:fp_pow_inst|Add34~21 ; wire \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[0] ; wire \fp_pow_0002:fp_pow_inst|Add35~38 ; wire \fp_pow_0002:fp_pow_inst|Add35~30 ; wire \fp_pow_0002:fp_pow_inst|Add35~34 ; wire \fp_pow_0002:fp_pow_inst|Add35~42 ; wire \fp_pow_0002:fp_pow_inst|Add35~26 ; wire \fp_pow_0002:fp_pow_inst|Add35~22 ; wire \fp_pow_0002:fp_pow_inst|Add35~18 ; wire \fp_pow_0002:fp_pow_inst|Add35~14 ; wire \fp_pow_0002:fp_pow_inst|Add35~10 ; wire \fp_pow_0002:fp_pow_inst|Add35~1 ; wire \fp_pow_0002:fp_pow_inst|Add35~2 ; wire \fp_pow_0002:fp_pow_inst|Add35~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|Add35~9 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|Add35~13 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|Add35~17 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|Add35~21 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|Add35~25 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|Add35~41 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Add35~33 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Add36~50 ; wire \fp_pow_0002:fp_pow_inst|Add36~51 ; wire \fp_pow_0002:fp_pow_inst|Add36~46 ; wire \fp_pow_0002:fp_pow_inst|Add36~47 ; wire \fp_pow_0002:fp_pow_inst|Add36~42 ; wire \fp_pow_0002:fp_pow_inst|Add36~43 ; wire \fp_pow_0002:fp_pow_inst|Add36~38 ; wire \fp_pow_0002:fp_pow_inst|Add36~39 ; wire \fp_pow_0002:fp_pow_inst|Add36~34 ; wire \fp_pow_0002:fp_pow_inst|Add36~35 ; wire \fp_pow_0002:fp_pow_inst|Add36~30 ; wire \fp_pow_0002:fp_pow_inst|Add36~31 ; wire \fp_pow_0002:fp_pow_inst|Add36~26 ; wire \fp_pow_0002:fp_pow_inst|Add36~27 ; wire \fp_pow_0002:fp_pow_inst|Add36~22 ; wire \fp_pow_0002:fp_pow_inst|Add36~23 ; wire \fp_pow_0002:fp_pow_inst|Add36~18 ; wire \fp_pow_0002:fp_pow_inst|Add36~19 ; wire \fp_pow_0002:fp_pow_inst|Add36~14 ; wire \fp_pow_0002:fp_pow_inst|Add36~15 ; wire \fp_pow_0002:fp_pow_inst|Add36~10 ; wire \fp_pow_0002:fp_pow_inst|Add36~11 ; wire \fp_pow_0002:fp_pow_inst|Add36~6 ; wire \fp_pow_0002:fp_pow_inst|Add36~7 ; wire \fp_pow_0002:fp_pow_inst|Add36~1 ; wire \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[12] ; wire \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[0]~0 ; wire \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[1] ; wire \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[2] ; wire \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[3] ; wire \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|redist78_sticky_ena_q[0]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist78_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:InvXEQOneAbs_uid163_fpPowrTest_delay|delay_signals[0][0]~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:InvXEQOneAbs_uid163_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist116|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|signRLog0_uid82_fpPowrTest_q_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:signRLog0_uid82_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[14][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[13][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[13][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[12][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[11][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[10][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[9][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[8][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[7][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[6][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[6][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[5][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[4][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[3][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[2][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|signProd_uid106_fpPowrTest_q_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[4][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[3][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[2][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[1][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[17][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[17][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[16][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[15][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[14][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[13][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[12][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[11][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[10][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[9][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[8][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[7][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[6][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[5][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[4][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[4][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[3][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[2][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|zeroCase6_uid165_fpPowrTest_q_i[0]~0 ; wire \fp_pow_0002:fp_pow_inst|infCase5_uid184_fpPowrTest_q_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:infCase5_uid184_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|redist123_sticky_ena_q[0]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist123_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|exc_I_uid30_fpPowrTest_q[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist123_inputreg|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|infCase3_uid191_fpPowrTest_q_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:infCase3_uid191_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[2]~0 ; wire \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[2] ; wire \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[3]~1 ; wire \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[3] ; wire \fp_pow_0002:fp_pow_inst|Equal19~0 ; wire \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_eq ; wire \fp_pow_0002:fp_pow_inst|Add48~0 ; wire \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[1] ; wire \fp_pow_0002:fp_pow_inst|Equal18~0 ; wire \fp_pow_0002:fp_pow_inst|redist96_cmpReg_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0]~0 ; wire \fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|Add26~17 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[4] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[32]~feeder ; wire \fp_pow_0002:fp_pow_inst|Add26~21 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[5] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[32] ; wire \fp_pow_0002:fp_pow_inst|Add26~13 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[3] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[31]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[31] ; wire \fp_pow_0002:fp_pow_inst|Add26~9 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[2] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[30]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[30] ; wire \fp_pow_0002:fp_pow_inst|Add26~5 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[1] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[29]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[29] ; wire \fp_pow_0002:fp_pow_inst|Add25~37 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[52] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][51] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[28]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[28] ; wire \fp_pow_0002:fp_pow_inst|Add25~33 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[51] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][50] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[27]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[27] ; wire \fp_pow_0002:fp_pow_inst|Add25~13 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[50] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][49] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[26]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[26] ; wire \fp_pow_0002:fp_pow_inst|Add25~9 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[49] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][48] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[25]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[25] ; wire \fp_pow_0002:fp_pow_inst|Add25~45 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[48] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][47]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][47] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[24]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[24] ; wire \fp_pow_0002:fp_pow_inst|Add25~41 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[47] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][46]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][46] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[23]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[23] ; wire \fp_pow_0002:fp_pow_inst|Add25~21 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[46] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][45] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[22]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[22] ; wire \fp_pow_0002:fp_pow_inst|Add25~17 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[45] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][44]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][44] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[21]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[21] ; wire \fp_pow_0002:fp_pow_inst|Add25~29 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[44] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[20]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[20] ; wire \fp_pow_0002:fp_pow_inst|Add25~25 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[43] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][42]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[19]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[19] ; wire \fp_pow_0002:fp_pow_inst|Add25~5 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[42] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][41]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[18]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[18] ; wire \fp_pow_0002:fp_pow_inst|Add25~1 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[41] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[17]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[17] ; wire \fp_pow_0002:fp_pow_inst|Add25~49 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[40] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[16]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[16] ; wire \fp_pow_0002:fp_pow_inst|Add25~53 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][38]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[15]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[15] ; wire \fp_pow_0002:fp_pow_inst|Add25~61 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][37]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[14]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[14] ; wire \fp_pow_0002:fp_pow_inst|Add25~65 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[13]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[13] ; wire \fp_pow_0002:fp_pow_inst|Add25~69 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][35]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[12]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[12] ; wire \fp_pow_0002:fp_pow_inst|Add25~73 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[11]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[11] ; wire \fp_pow_0002:fp_pow_inst|Add25~77 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][33]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[10]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[10] ; wire \fp_pow_0002:fp_pow_inst|Add25~81 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][32]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[9]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[9]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Add25~85 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][31]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[8]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[8] ; wire \fp_pow_0002:fp_pow_inst|Add25~89 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][30]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[7]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[7] ; wire \fp_pow_0002:fp_pow_inst|Add25~93 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[6]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[6] ; wire \fp_pow_0002:fp_pow_inst|Add25~97 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][28]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[5]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[5] ; wire \fp_pow_0002:fp_pow_inst|Add25~109 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][27]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[4]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[4] ; wire \fp_pow_0002:fp_pow_inst|Add25~117 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][26]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[3]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[3] ; wire \fp_pow_0002:fp_pow_inst|Add25~113 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][25]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[2]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[2] ; wire \fp_pow_0002:fp_pow_inst|Add25~105 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][24]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[1]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[1] ; wire \fp_pow_0002:fp_pow_inst|Add25~101 ; wire \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][23]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[0]~feeder ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[0] ; wire \fp_pow_0002:fp_pow_inst|Add27~138 ; wire \fp_pow_0002:fp_pow_inst|Add27~134 ; wire \fp_pow_0002:fp_pow_inst|Add27~130 ; wire \fp_pow_0002:fp_pow_inst|Add27~126 ; wire \fp_pow_0002:fp_pow_inst|Add27~122 ; wire \fp_pow_0002:fp_pow_inst|Add27~118 ; wire \fp_pow_0002:fp_pow_inst|Add27~114 ; wire \fp_pow_0002:fp_pow_inst|Add27~110 ; wire \fp_pow_0002:fp_pow_inst|Add27~106 ; wire \fp_pow_0002:fp_pow_inst|Add27~102 ; wire \fp_pow_0002:fp_pow_inst|Add27~98 ; wire \fp_pow_0002:fp_pow_inst|Add27~94 ; wire \fp_pow_0002:fp_pow_inst|Add27~90 ; wire \fp_pow_0002:fp_pow_inst|Add27~86 ; wire \fp_pow_0002:fp_pow_inst|Add27~82 ; wire \fp_pow_0002:fp_pow_inst|Add27~78 ; wire \fp_pow_0002:fp_pow_inst|Add27~74 ; wire \fp_pow_0002:fp_pow_inst|Add27~70 ; wire \fp_pow_0002:fp_pow_inst|Add27~54 ; wire \fp_pow_0002:fp_pow_inst|Add27~58 ; wire \fp_pow_0002:fp_pow_inst|Add27~62 ; wire \fp_pow_0002:fp_pow_inst|Add27~66 ; wire \fp_pow_0002:fp_pow_inst|Add27~50 ; wire \fp_pow_0002:fp_pow_inst|Add27~46 ; wire \fp_pow_0002:fp_pow_inst|Add27~10 ; wire \fp_pow_0002:fp_pow_inst|Add27~14 ; wire \fp_pow_0002:fp_pow_inst|Add27~18 ; wire \fp_pow_0002:fp_pow_inst|Add27~22 ; wire \fp_pow_0002:fp_pow_inst|Add27~6 ; wire \fp_pow_0002:fp_pow_inst|Add27~26 ; wire \fp_pow_0002:fp_pow_inst|Add27~38 ; wire \fp_pow_0002:fp_pow_inst|Add27~34 ; wire \fp_pow_0002:fp_pow_inst|Add27~42 ; wire \fp_pow_0002:fp_pow_inst|Add27~30 ; wire \fp_pow_0002:fp_pow_inst|Add27~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[41] ; wire \fp_pow_0002:fp_pow_inst|Add27~29 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Add27~33 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Add27~37 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add27~41 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|Ram6~2 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[40] ; wire \fp_pow_0002:fp_pow_inst|Ram6~8 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[39] ; wire \fp_pow_0002:fp_pow_inst|Ram6~3 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[38] ; wire \fp_pow_0002:fp_pow_inst|Ram6~9 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[37] ; wire \fp_pow_0002:fp_pow_inst|Ram6~0 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[36] ; wire \fp_pow_0002:fp_pow_inst|Add27~21 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Add27~13 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Add27~9 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add27~17 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|Add27~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Ram5~40 ; wire \fp_pow_0002:fp_pow_inst|Add27~25 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|Ram5~39 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|Ram6~5 ; wire \fp_pow_0002:fp_pow_inst|Ram6~6 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[35] ; wire \fp_pow_0002:fp_pow_inst|Ram5~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|Ram6~4 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[34] ; wire \fp_pow_0002:fp_pow_inst|Ram6~10 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[33] ; wire \fp_pow_0002:fp_pow_inst|Ram5~3 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|Ram5~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|Ram6~1 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[32] ; wire \fp_pow_0002:fp_pow_inst|Ram5~2 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|Ram6~7 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[31] ; wire \fp_pow_0002:fp_pow_inst|Ram5~38 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|Ram6~11 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[30] ; wire \fp_pow_0002:fp_pow_inst|Ram5~4 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|Ram6~12 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[29] ; wire \fp_pow_0002:fp_pow_inst|Ram5~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|Ram6~13 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[28] ; wire \fp_pow_0002:fp_pow_inst|Ram5~37 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|Ram5~6 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|Ram5~36 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|Ram6~14 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[25] ; wire \fp_pow_0002:fp_pow_inst|Ram6~15 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[24] ; wire \fp_pow_0002:fp_pow_inst|Ram5~35 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|Ram5~34 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|Ram6~16 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[23] ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[22] ; wire \fp_pow_0002:fp_pow_inst|Ram5~33 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|Ram6~17 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[21] ; wire \fp_pow_0002:fp_pow_inst|Ram5~9 ; wire \fp_pow_0002:fp_pow_inst|Ram5~7 ; wire \fp_pow_0002:fp_pow_inst|Ram5~8 ; wire \fp_pow_0002:fp_pow_inst|Ram5~10 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|Ram5~32 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|Ram6~18 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[20] ; wire \fp_pow_0002:fp_pow_inst|Ram6~19 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] ; wire \fp_pow_0002:fp_pow_inst|Ram5~11 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|Ram5~12 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|Ram6~20 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] ; wire \fp_pow_0002:fp_pow_inst|Ram5~13 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|Ram6~21 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] ; wire \fp_pow_0002:fp_pow_inst|Ram5~14 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|Ram6~22 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] ; wire \fp_pow_0002:fp_pow_inst|Ram6~23 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] ; wire \fp_pow_0002:fp_pow_inst|Ram5~31 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|Ram5~15 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|Ram6~24 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] ; wire \fp_pow_0002:fp_pow_inst|Ram6~25 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] ; wire \fp_pow_0002:fp_pow_inst|Ram5~16 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|Ram5~17 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|Ram5~18 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|Ram6~26 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] ; wire \fp_pow_0002:fp_pow_inst|Ram5~19 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|Ram6~27 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] ; wire \fp_pow_0002:fp_pow_inst|Ram5~30 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|Ram5~20 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|Ram6~28 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] ; wire \fp_pow_0002:fp_pow_inst|Ram5~29 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|Ram6~29 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] ; wire \fp_pow_0002:fp_pow_inst|Ram6~30 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] ; wire \fp_pow_0002:fp_pow_inst|Ram5~28 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|Ram5~21 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|Ram6~31 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] ; wire \fp_pow_0002:fp_pow_inst|Ram5~22 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Ram6~32 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] ; wire \fp_pow_0002:fp_pow_inst|Ram5~23 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Ram6~33 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] ; wire \fp_pow_0002:fp_pow_inst|Ram5~27 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|Ram6~34 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] ; wire \fp_pow_0002:fp_pow_inst|Ram6~35 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] ; wire \fp_pow_0002:fp_pow_inst|Ram5~24 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Ram6~36 ; wire \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] ; wire \fp_pow_0002:fp_pow_inst|Ram5~25 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add30~166 ; wire \fp_pow_0002:fp_pow_inst|Add30~162 ; wire \fp_pow_0002:fp_pow_inst|Add30~158 ; wire \fp_pow_0002:fp_pow_inst|Add30~154 ; wire \fp_pow_0002:fp_pow_inst|Add30~150 ; wire \fp_pow_0002:fp_pow_inst|Add30~146 ; wire \fp_pow_0002:fp_pow_inst|Add30~142 ; wire \fp_pow_0002:fp_pow_inst|Add30~138 ; wire \fp_pow_0002:fp_pow_inst|Add30~134 ; wire \fp_pow_0002:fp_pow_inst|Add30~130 ; wire \fp_pow_0002:fp_pow_inst|Add30~126 ; wire \fp_pow_0002:fp_pow_inst|Add30~122 ; wire \fp_pow_0002:fp_pow_inst|Add30~118 ; wire \fp_pow_0002:fp_pow_inst|Add30~114 ; wire \fp_pow_0002:fp_pow_inst|Add30~110 ; wire \fp_pow_0002:fp_pow_inst|Add30~106 ; wire \fp_pow_0002:fp_pow_inst|Add30~102 ; wire \fp_pow_0002:fp_pow_inst|Add30~98 ; wire \fp_pow_0002:fp_pow_inst|Add30~94 ; wire \fp_pow_0002:fp_pow_inst|Add30~90 ; wire \fp_pow_0002:fp_pow_inst|Add30~86 ; wire \fp_pow_0002:fp_pow_inst|Add30~82 ; wire \fp_pow_0002:fp_pow_inst|Add30~78 ; wire \fp_pow_0002:fp_pow_inst|Add30~74 ; wire \fp_pow_0002:fp_pow_inst|Add30~70 ; wire \fp_pow_0002:fp_pow_inst|Add30~66 ; wire \fp_pow_0002:fp_pow_inst|Add30~62 ; wire \fp_pow_0002:fp_pow_inst|Add30~58 ; wire \fp_pow_0002:fp_pow_inst|Add30~54 ; wire \fp_pow_0002:fp_pow_inst|Add30~50 ; wire \fp_pow_0002:fp_pow_inst|Add30~46 ; wire \fp_pow_0002:fp_pow_inst|Add30~30 ; wire \fp_pow_0002:fp_pow_inst|Add30~10 ; wire \fp_pow_0002:fp_pow_inst|Add30~42 ; wire \fp_pow_0002:fp_pow_inst|Add30~22 ; wire \fp_pow_0002:fp_pow_inst|Add30~26 ; wire \fp_pow_0002:fp_pow_inst|Add30~6 ; wire \fp_pow_0002:fp_pow_inst|Add30~38 ; wire \fp_pow_0002:fp_pow_inst|Add30~18 ; wire \fp_pow_0002:fp_pow_inst|Add30~34 ; wire \fp_pow_0002:fp_pow_inst|Add30~14 ; wire \fp_pow_0002:fp_pow_inst|Add30~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|Add30~13 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|Add30~33 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|Add30~17 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|Add30~37 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|Add30~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|Add30~25 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|Add30~21 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|Add30~41 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|Add30~9 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|Add30~29 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|Add27~65 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Add27~57 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Add27~61 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|Add27~49 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Add27~53 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Ram4~34 ; wire \fp_pow_0002:fp_pow_inst|Add27~45 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[31] ; wire \fp_pow_0002:fp_pow_inst|Ram4~33 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[30] ; wire \fp_pow_0002:fp_pow_inst|Ram4~0 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[29] ; wire \fp_pow_0002:fp_pow_inst|Ram4~1 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[28] ; wire \fp_pow_0002:fp_pow_inst|Ram4~2 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[27] ; wire \fp_pow_0002:fp_pow_inst|Ram4~3 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[26] ; wire \fp_pow_0002:fp_pow_inst|Ram4~32 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[25] ; wire \fp_pow_0002:fp_pow_inst|Add27~85 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Add27~77 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Add27~81 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|Add27~73 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Add27~89 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Ram3~25 ; wire \fp_pow_0002:fp_pow_inst|Add27~69 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[25] ; wire \fp_pow_0002:fp_pow_inst|Ram3~24 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[24] ; wire \fp_pow_0002:fp_pow_inst|Ram4~4 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[24] ; wire \fp_pow_0002:fp_pow_inst|Ram4~5 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[23] ; wire \fp_pow_0002:fp_pow_inst|Ram3~0 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[23] ; wire \fp_pow_0002:fp_pow_inst|Ram3~1 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[22] ; wire \fp_pow_0002:fp_pow_inst|Ram4~31 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[22] ; wire \fp_pow_0002:fp_pow_inst|Ram3~2 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[21] ; wire \fp_pow_0002:fp_pow_inst|Ram4~6 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[21] ; wire \fp_pow_0002:fp_pow_inst|Ram3~3 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[20] ; wire \fp_pow_0002:fp_pow_inst|Ram4~30 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[20] ; wire \fp_pow_0002:fp_pow_inst|Ram4~29 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] ; wire \fp_pow_0002:fp_pow_inst|Ram3~23 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] ; wire \fp_pow_0002:fp_pow_inst|Ram3~4 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] ; wire \fp_pow_0002:fp_pow_inst|Ram4~28 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] ; wire \fp_pow_0002:fp_pow_inst|Ram3~5 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] ; wire \fp_pow_0002:fp_pow_inst|Ram4~27 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] ; wire \fp_pow_0002:fp_pow_inst|Ram3~22 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] ; wire \fp_pow_0002:fp_pow_inst|Ram4~8 ; wire \fp_pow_0002:fp_pow_inst|Ram4~9 ; wire \fp_pow_0002:fp_pow_inst|Ram4~7 ; wire \fp_pow_0002:fp_pow_inst|Ram4~10 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] ; wire \fp_pow_0002:fp_pow_inst|Ram4~26 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] ; wire \fp_pow_0002:fp_pow_inst|Ram3~6 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] ; wire \fp_pow_0002:fp_pow_inst|Ram4~11 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] ; wire \fp_pow_0002:fp_pow_inst|Ram3~21 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] ; wire \fp_pow_0002:fp_pow_inst|Ram4~12 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] ; wire \fp_pow_0002:fp_pow_inst|Ram3~20 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] ; wire \fp_pow_0002:fp_pow_inst|Ram4~13 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] ; wire \fp_pow_0002:fp_pow_inst|Ram3~19 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] ; wire \fp_pow_0002:fp_pow_inst|Ram4~14 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] ; wire \fp_pow_0002:fp_pow_inst|Ram3~18 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] ; wire \fp_pow_0002:fp_pow_inst|Ram3~17 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] ; wire \fp_pow_0002:fp_pow_inst|Ram4~25 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] ; wire \fp_pow_0002:fp_pow_inst|Ram3~16 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] ; wire \fp_pow_0002:fp_pow_inst|Ram4~15 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] ; wire \fp_pow_0002:fp_pow_inst|Ram3~7 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] ; wire \fp_pow_0002:fp_pow_inst|Ram4~16 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] ; wire \fp_pow_0002:fp_pow_inst|Ram4~17 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] ; wire \fp_pow_0002:fp_pow_inst|Ram3~8 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] ; wire \fp_pow_0002:fp_pow_inst|Ram3~9 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] ; wire \fp_pow_0002:fp_pow_inst|Ram4~18 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] ; wire \fp_pow_0002:fp_pow_inst|Ram4~19 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] ; wire \fp_pow_0002:fp_pow_inst|Ram3~10 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] ; wire \fp_pow_0002:fp_pow_inst|Ram3~15 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] ; wire \fp_pow_0002:fp_pow_inst|Ram4~24 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] ; wire \fp_pow_0002:fp_pow_inst|Ram4~20 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] ; wire \fp_pow_0002:fp_pow_inst|Ram3~11 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] ; wire \fp_pow_0002:fp_pow_inst|Ram3~12 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] ; wire \fp_pow_0002:fp_pow_inst|Ram4~23 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] ; wire \fp_pow_0002:fp_pow_inst|Ram3~13 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] ; wire \fp_pow_0002:fp_pow_inst|Ram4~22 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] ; wire \fp_pow_0002:fp_pow_inst|Ram4~21 ; wire \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] ; wire \fp_pow_0002:fp_pow_inst|Ram3~14 ; wire \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] ; wire \fp_pow_0002:fp_pow_inst|Add29~130 ; wire \fp_pow_0002:fp_pow_inst|Add29~126 ; wire \fp_pow_0002:fp_pow_inst|Add29~122 ; wire \fp_pow_0002:fp_pow_inst|Add29~118 ; wire \fp_pow_0002:fp_pow_inst|Add29~114 ; wire \fp_pow_0002:fp_pow_inst|Add29~110 ; wire \fp_pow_0002:fp_pow_inst|Add29~106 ; wire \fp_pow_0002:fp_pow_inst|Add29~102 ; wire \fp_pow_0002:fp_pow_inst|Add29~98 ; wire \fp_pow_0002:fp_pow_inst|Add29~94 ; wire \fp_pow_0002:fp_pow_inst|Add29~90 ; wire \fp_pow_0002:fp_pow_inst|Add29~86 ; wire \fp_pow_0002:fp_pow_inst|Add29~82 ; wire \fp_pow_0002:fp_pow_inst|Add29~78 ; wire \fp_pow_0002:fp_pow_inst|Add29~74 ; wire \fp_pow_0002:fp_pow_inst|Add29~70 ; wire \fp_pow_0002:fp_pow_inst|Add29~66 ; wire \fp_pow_0002:fp_pow_inst|Add29~62 ; wire \fp_pow_0002:fp_pow_inst|Add29~58 ; wire \fp_pow_0002:fp_pow_inst|Add29~54 ; wire \fp_pow_0002:fp_pow_inst|Add29~50 ; wire \fp_pow_0002:fp_pow_inst|Add29~46 ; wire \fp_pow_0002:fp_pow_inst|Add29~42 ; wire \fp_pow_0002:fp_pow_inst|Add29~38 ; wire \fp_pow_0002:fp_pow_inst|Add29~34 ; wire \fp_pow_0002:fp_pow_inst|Add29~30 ; wire \fp_pow_0002:fp_pow_inst|Add29~26 ; wire \fp_pow_0002:fp_pow_inst|Add29~22 ; wire \fp_pow_0002:fp_pow_inst|Add29~18 ; wire \fp_pow_0002:fp_pow_inst|Add29~14 ; wire \fp_pow_0002:fp_pow_inst|Add29~10 ; wire \fp_pow_0002:fp_pow_inst|Add29~6 ; wire \fp_pow_0002:fp_pow_inst|Add29~1 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[32] ; wire \fp_pow_0002:fp_pow_inst|Add29~5 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[31] ; wire \fp_pow_0002:fp_pow_inst|Add30~45 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|Add30~49 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|Add29~9 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[30] ; wire \fp_pow_0002:fp_pow_inst|Add30~53 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|Add29~13 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[29] ; wire \fp_pow_0002:fp_pow_inst|Add29~17 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[28] ; wire \fp_pow_0002:fp_pow_inst|Add30~57 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|Add29~21 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[27] ; wire \fp_pow_0002:fp_pow_inst|Add30~61 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|Add30~65 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|Add29~25 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[26] ; wire \fp_pow_0002:fp_pow_inst|Add29~29 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[25] ; wire \fp_pow_0002:fp_pow_inst|Add30~69 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|Add30~73 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|Add29~33 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[24] ; wire \fp_pow_0002:fp_pow_inst|Add30~77 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|Add29~37 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[23] ; wire \fp_pow_0002:fp_pow_inst|Add30~81 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|Add29~41 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[22] ; wire \fp_pow_0002:fp_pow_inst|Add30~85 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|Add29~45 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[21] ; wire \fp_pow_0002:fp_pow_inst|Add30~89 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|Add29~49 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[20] ; wire \fp_pow_0002:fp_pow_inst|Add29~53 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[19] ; wire \fp_pow_0002:fp_pow_inst|Add30~93 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|Add29~57 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[18] ; wire \fp_pow_0002:fp_pow_inst|Add30~97 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|Add29~61 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[17] ; wire \fp_pow_0002:fp_pow_inst|Add30~101 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|Add30~105 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|Add29~65 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[16] ; wire \fp_pow_0002:fp_pow_inst|Add29~69 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[15] ; wire \fp_pow_0002:fp_pow_inst|Add30~109 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|Add30~113 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|Add29~73 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[14] ; wire \fp_pow_0002:fp_pow_inst|Add29~77 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[13] ; wire \fp_pow_0002:fp_pow_inst|Add30~117 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|Add30~121 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|Add29~81 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[12] ; wire \fp_pow_0002:fp_pow_inst|Add30~125 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|Add29~85 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[11] ; wire \fp_pow_0002:fp_pow_inst|Add30~129 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|Add29~89 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[10] ; wire \fp_pow_0002:fp_pow_inst|Add30~133 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|Add29~93 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[9] ; wire \fp_pow_0002:fp_pow_inst|Add29~97 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[8] ; wire \fp_pow_0002:fp_pow_inst|Add30~137 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|Add29~101 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[7] ; wire \fp_pow_0002:fp_pow_inst|Add30~141 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|Add29~105 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[6] ; wire \fp_pow_0002:fp_pow_inst|Add30~145 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|Add29~109 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[5] ; wire \fp_pow_0002:fp_pow_inst|Add30~149 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|Add30~153 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Add29~113 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[4] ; wire \fp_pow_0002:fp_pow_inst|Add30~157 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Add29~117 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[3] ; wire \fp_pow_0002:fp_pow_inst|Add29~121 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[2] ; wire \fp_pow_0002:fp_pow_inst|Add30~161 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|Add30~165 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Add29~125 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[1] ; wire \fp_pow_0002:fp_pow_inst|Add29~129 ; wire \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[0] ; wire \fp_pow_0002:fp_pow_inst|Ram5~26 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist44|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add31~170 ; wire \fp_pow_0002:fp_pow_inst|Add31~166 ; wire \fp_pow_0002:fp_pow_inst|Add31~162 ; wire \fp_pow_0002:fp_pow_inst|Add31~158 ; wire \fp_pow_0002:fp_pow_inst|Add31~154 ; wire \fp_pow_0002:fp_pow_inst|Add31~150 ; wire \fp_pow_0002:fp_pow_inst|Add31~146 ; wire \fp_pow_0002:fp_pow_inst|Add31~142 ; wire \fp_pow_0002:fp_pow_inst|Add31~138 ; wire \fp_pow_0002:fp_pow_inst|Add31~134 ; wire \fp_pow_0002:fp_pow_inst|Add31~130 ; wire \fp_pow_0002:fp_pow_inst|Add31~126 ; wire \fp_pow_0002:fp_pow_inst|Add31~122 ; wire \fp_pow_0002:fp_pow_inst|Add31~118 ; wire \fp_pow_0002:fp_pow_inst|Add31~114 ; wire \fp_pow_0002:fp_pow_inst|Add31~110 ; wire \fp_pow_0002:fp_pow_inst|Add31~106 ; wire \fp_pow_0002:fp_pow_inst|Add31~102 ; wire \fp_pow_0002:fp_pow_inst|Add31~98 ; wire \fp_pow_0002:fp_pow_inst|Add31~94 ; wire \fp_pow_0002:fp_pow_inst|Add31~90 ; wire \fp_pow_0002:fp_pow_inst|Add31~86 ; wire \fp_pow_0002:fp_pow_inst|Add31~82 ; wire \fp_pow_0002:fp_pow_inst|Add31~78 ; wire \fp_pow_0002:fp_pow_inst|Add31~74 ; wire \fp_pow_0002:fp_pow_inst|Add31~70 ; wire \fp_pow_0002:fp_pow_inst|Add31~66 ; wire \fp_pow_0002:fp_pow_inst|Add31~62 ; wire \fp_pow_0002:fp_pow_inst|Add31~58 ; wire \fp_pow_0002:fp_pow_inst|Add31~54 ; wire \fp_pow_0002:fp_pow_inst|Add31~50 ; wire \fp_pow_0002:fp_pow_inst|Add31~46 ; wire \fp_pow_0002:fp_pow_inst|Add31~30 ; wire \fp_pow_0002:fp_pow_inst|Add31~10 ; wire \fp_pow_0002:fp_pow_inst|Add31~42 ; wire \fp_pow_0002:fp_pow_inst|Add31~22 ; wire \fp_pow_0002:fp_pow_inst|Add31~26 ; wire \fp_pow_0002:fp_pow_inst|Add31~6 ; wire \fp_pow_0002:fp_pow_inst|Add31~38 ; wire \fp_pow_0002:fp_pow_inst|Add31~18 ; wire \fp_pow_0002:fp_pow_inst|Add31~34 ; wire \fp_pow_0002:fp_pow_inst|Add31~14 ; wire \fp_pow_0002:fp_pow_inst|Add31~1 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[42] ; wire \fp_pow_0002:fp_pow_inst|Add31~13 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[41] ; wire \fp_pow_0002:fp_pow_inst|Add31~33 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[40] ; wire \fp_pow_0002:fp_pow_inst|Add31~17 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[39] ; wire \fp_pow_0002:fp_pow_inst|Add31~37 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[38] ; wire \fp_pow_0002:fp_pow_inst|Add31~5 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[37] ; wire \fp_pow_0002:fp_pow_inst|Add31~25 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[36] ; wire \fp_pow_0002:fp_pow_inst|Add31~21 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[35] ; wire \fp_pow_0002:fp_pow_inst|Add31~41 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[34] ; wire \fp_pow_0002:fp_pow_inst|Add31~9 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[33] ; wire \fp_pow_0002:fp_pow_inst|Add31~29 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[32] ; wire \fp_pow_0002:fp_pow_inst|Add31~45 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[31] ; wire \fp_pow_0002:fp_pow_inst|Add31~49 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[30] ; wire \fp_pow_0002:fp_pow_inst|Add31~53 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[29] ; wire \fp_pow_0002:fp_pow_inst|Add31~57 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[28] ; wire \fp_pow_0002:fp_pow_inst|Add31~61 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[27] ; wire \fp_pow_0002:fp_pow_inst|Add31~65 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[26] ; wire \fp_pow_0002:fp_pow_inst|Add31~69 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[25] ; wire \fp_pow_0002:fp_pow_inst|Add31~73 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[24] ; wire \fp_pow_0002:fp_pow_inst|Add31~77 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[23] ; wire \fp_pow_0002:fp_pow_inst|Add31~81 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[22] ; wire \fp_pow_0002:fp_pow_inst|Add31~85 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[21] ; wire \fp_pow_0002:fp_pow_inst|Add31~89 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[20] ; wire \fp_pow_0002:fp_pow_inst|Add27~113 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add27~101 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Add27~97 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][4]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Add27~105 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|Add27~109 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Ram2~19 ; wire \fp_pow_0002:fp_pow_inst|Add27~93 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] ; wire \fp_pow_0002:fp_pow_inst|Ram2~18 ; wire \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] ; wire \fp_pow_0002:fp_pow_inst|Ram2~0 ; wire \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] ; wire \fp_pow_0002:fp_pow_inst|Ram2~1 ; wire \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] ; wire \fp_pow_0002:fp_pow_inst|Ram2~2 ; wire \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] ; wire \fp_pow_0002:fp_pow_inst|Ram2~3 ; wire \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] ; wire \fp_pow_0002:fp_pow_inst|Add27~121 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Add27~129 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|Add27~133 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Add27~137 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add27~125 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Ram1~13 ; wire \fp_pow_0002:fp_pow_inst|Add27~117 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] ; wire \fp_pow_0002:fp_pow_inst|Ram2~17 ; wire \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] ; wire \fp_pow_0002:fp_pow_inst|Ram2~4 ; wire \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] ; wire \fp_pow_0002:fp_pow_inst|Ram1~12 ; wire \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] ; wire \fp_pow_0002:fp_pow_inst|Ram2~5 ; wire \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Ram1~0 ; wire \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] ; wire \fp_pow_0002:fp_pow_inst|Ram2~16 ; wire \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] ; wire \fp_pow_0002:fp_pow_inst|Ram1~1 ; wire \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] ; wire \fp_pow_0002:fp_pow_inst|Ram2~6 ; wire \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][4]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Ram1~2 ; wire \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] ; wire \fp_pow_0002:fp_pow_inst|Ram2~15 ; wire \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] ; wire \fp_pow_0002:fp_pow_inst|Ram1~3 ; wire \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] ; wire \fp_pow_0002:fp_pow_inst|Ram2~14 ; wire \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] ; wire \fp_pow_0002:fp_pow_inst|Ram1~11 ; wire \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] ; wire \fp_pow_0002:fp_pow_inst|Ram2~13 ; wire \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] ; wire \fp_pow_0002:fp_pow_inst|Ram1~4 ; wire \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] ; wire \fp_pow_0002:fp_pow_inst|Ram2~12 ; wire \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] ; wire \fp_pow_0002:fp_pow_inst|Ram1~5 ; wire \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] ; wire \fp_pow_0002:fp_pow_inst|Ram1~10 ; wire \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] ; wire \fp_pow_0002:fp_pow_inst|Ram2~11 ; wire \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] ; wire \fp_pow_0002:fp_pow_inst|Ram2~10 ; wire \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] ; wire \fp_pow_0002:fp_pow_inst|Ram1~6 ; wire \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] ; wire \fp_pow_0002:fp_pow_inst|Ram1~9 ; wire \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] ; wire \fp_pow_0002:fp_pow_inst|Ram2~7 ; wire \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] ; wire \fp_pow_0002:fp_pow_inst|Ram2~8 ; wire \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] ; wire \fp_pow_0002:fp_pow_inst|Ram1~8 ; wire \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] ; wire \fp_pow_0002:fp_pow_inst|Ram1~7 ; wire \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] ; wire \fp_pow_0002:fp_pow_inst|Ram2~9 ; wire \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] ; wire \fp_pow_0002:fp_pow_inst|Add28~82 ; wire \fp_pow_0002:fp_pow_inst|Add28~78 ; wire \fp_pow_0002:fp_pow_inst|Add28~74 ; wire \fp_pow_0002:fp_pow_inst|Add28~70 ; wire \fp_pow_0002:fp_pow_inst|Add28~66 ; wire \fp_pow_0002:fp_pow_inst|Add28~62 ; wire \fp_pow_0002:fp_pow_inst|Add28~58 ; wire \fp_pow_0002:fp_pow_inst|Add28~54 ; wire \fp_pow_0002:fp_pow_inst|Add28~50 ; wire \fp_pow_0002:fp_pow_inst|Add28~46 ; wire \fp_pow_0002:fp_pow_inst|Add28~42 ; wire \fp_pow_0002:fp_pow_inst|Add28~38 ; wire \fp_pow_0002:fp_pow_inst|Add28~34 ; wire \fp_pow_0002:fp_pow_inst|Add28~30 ; wire \fp_pow_0002:fp_pow_inst|Add28~26 ; wire \fp_pow_0002:fp_pow_inst|Add28~22 ; wire \fp_pow_0002:fp_pow_inst|Add28~18 ; wire \fp_pow_0002:fp_pow_inst|Add28~14 ; wire \fp_pow_0002:fp_pow_inst|Add28~10 ; wire \fp_pow_0002:fp_pow_inst|Add28~6 ; wire \fp_pow_0002:fp_pow_inst|Add28~1 ; wire \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[20] ; wire \fp_pow_0002:fp_pow_inst|Add31~93 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[19] ; wire \fp_pow_0002:fp_pow_inst|Add28~5 ; wire \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[19] ; wire \fp_pow_0002:fp_pow_inst|Add31~97 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[18] ; wire \fp_pow_0002:fp_pow_inst|Add28~9 ; wire \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[18] ; wire \fp_pow_0002:fp_pow_inst|Add28~13 ; wire \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[17] ; wire \fp_pow_0002:fp_pow_inst|Add31~101 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[17] ; wire \fp_pow_0002:fp_pow_inst|Add31~105 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[16] ; wire \fp_pow_0002:fp_pow_inst|Add28~17 ; wire \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[16] ; wire \fp_pow_0002:fp_pow_inst|Add28~21 ; wire \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[15] ; wire \fp_pow_0002:fp_pow_inst|Add31~109 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[15] ; wire \fp_pow_0002:fp_pow_inst|Add28~25 ; wire \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[14] ; wire \fp_pow_0002:fp_pow_inst|Add31~113 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[14] ; wire \fp_pow_0002:fp_pow_inst|Add31~117 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[13] ; wire \fp_pow_0002:fp_pow_inst|Add28~29 ; wire \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[13] ; wire \fp_pow_0002:fp_pow_inst|Add31~121 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[12] ; wire \fp_pow_0002:fp_pow_inst|Add28~33 ; wire \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[12] ; wire \fp_pow_0002:fp_pow_inst|Add31~125 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[11] ; wire \fp_pow_0002:fp_pow_inst|Add28~37 ; wire \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[11] ; wire \fp_pow_0002:fp_pow_inst|Add31~129 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[10] ; wire \fp_pow_0002:fp_pow_inst|Add28~41 ; wire \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[10] ; wire \fp_pow_0002:fp_pow_inst|Add31~133 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[9] ; wire \fp_pow_0002:fp_pow_inst|Add28~45 ; wire \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[9] ; wire \fp_pow_0002:fp_pow_inst|Add31~137 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[8] ; wire \fp_pow_0002:fp_pow_inst|Add28~49 ; wire \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[8] ; wire \fp_pow_0002:fp_pow_inst|Add31~141 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[7] ; wire \fp_pow_0002:fp_pow_inst|Add28~53 ; wire \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[7] ; wire \fp_pow_0002:fp_pow_inst|Add31~145 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[6] ; wire \fp_pow_0002:fp_pow_inst|Add28~57 ; wire \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[6] ; wire \fp_pow_0002:fp_pow_inst|Add31~149 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[5] ; wire \fp_pow_0002:fp_pow_inst|Add28~61 ; wire \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[5] ; wire \fp_pow_0002:fp_pow_inst|Add31~153 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[4] ; wire \fp_pow_0002:fp_pow_inst|Add28~65 ; wire \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[4] ; wire \fp_pow_0002:fp_pow_inst|Add31~157 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[3] ; wire \fp_pow_0002:fp_pow_inst|Add28~69 ; wire \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[3] ; wire \fp_pow_0002:fp_pow_inst|Add28~73 ; wire \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[2] ; wire \fp_pow_0002:fp_pow_inst|Add31~161 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[2] ; wire \fp_pow_0002:fp_pow_inst|Add31~165 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[1] ; wire \fp_pow_0002:fp_pow_inst|Add28~77 ; wire \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[1] ; wire \fp_pow_0002:fp_pow_inst|Add31~169 ; wire \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[0] ; wire \fp_pow_0002:fp_pow_inst|Add28~81 ; wire \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[0] ; wire \fp_pow_0002:fp_pow_inst|Add32~170 ; wire \fp_pow_0002:fp_pow_inst|Add32~166 ; wire \fp_pow_0002:fp_pow_inst|Add32~162 ; wire \fp_pow_0002:fp_pow_inst|Add32~158 ; wire \fp_pow_0002:fp_pow_inst|Add32~154 ; wire \fp_pow_0002:fp_pow_inst|Add32~150 ; wire \fp_pow_0002:fp_pow_inst|Add32~146 ; wire \fp_pow_0002:fp_pow_inst|Add32~142 ; wire \fp_pow_0002:fp_pow_inst|Add32~138 ; wire \fp_pow_0002:fp_pow_inst|Add32~134 ; wire \fp_pow_0002:fp_pow_inst|Add32~130 ; wire \fp_pow_0002:fp_pow_inst|Add32~126 ; wire \fp_pow_0002:fp_pow_inst|Add32~122 ; wire \fp_pow_0002:fp_pow_inst|Add32~118 ; wire \fp_pow_0002:fp_pow_inst|Add32~114 ; wire \fp_pow_0002:fp_pow_inst|Add32~110 ; wire \fp_pow_0002:fp_pow_inst|Add32~106 ; wire \fp_pow_0002:fp_pow_inst|Add32~102 ; wire \fp_pow_0002:fp_pow_inst|Add32~98 ; wire \fp_pow_0002:fp_pow_inst|Add32~94 ; wire \fp_pow_0002:fp_pow_inst|Add32~90 ; wire \fp_pow_0002:fp_pow_inst|Add32~86 ; wire \fp_pow_0002:fp_pow_inst|Add32~82 ; wire \fp_pow_0002:fp_pow_inst|Add32~78 ; wire \fp_pow_0002:fp_pow_inst|Add32~74 ; wire \fp_pow_0002:fp_pow_inst|Add32~70 ; wire \fp_pow_0002:fp_pow_inst|Add32~66 ; wire \fp_pow_0002:fp_pow_inst|Add32~62 ; wire \fp_pow_0002:fp_pow_inst|Add32~58 ; wire \fp_pow_0002:fp_pow_inst|Add32~54 ; wire \fp_pow_0002:fp_pow_inst|Add32~50 ; wire \fp_pow_0002:fp_pow_inst|Add32~46 ; wire \fp_pow_0002:fp_pow_inst|Add32~30 ; wire \fp_pow_0002:fp_pow_inst|Add32~10 ; wire \fp_pow_0002:fp_pow_inst|Add32~42 ; wire \fp_pow_0002:fp_pow_inst|Add32~22 ; wire \fp_pow_0002:fp_pow_inst|Add32~26 ; wire \fp_pow_0002:fp_pow_inst|Add32~6 ; wire \fp_pow_0002:fp_pow_inst|Add32~38 ; wire \fp_pow_0002:fp_pow_inst|Add32~18 ; wire \fp_pow_0002:fp_pow_inst|Add32~34 ; wire \fp_pow_0002:fp_pow_inst|Add32~14 ; wire \fp_pow_0002:fp_pow_inst|Add32~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1] ; wire \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2] ; wire \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1] ; wire \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|Add36~5 ; wire \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[11] ; wire \fp_pow_0002:fp_pow_inst|Add36~9 ; wire \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[10] ; wire \fp_pow_0002:fp_pow_inst|Add36~13 ; wire \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[9] ; wire \fp_pow_0002:fp_pow_inst|Add36~17 ; wire \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[8] ; wire \fp_pow_0002:fp_pow_inst|Add36~21 ; wire \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[7] ; wire \fp_pow_0002:fp_pow_inst|Add36~25 ; wire \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[6] ; wire \fp_pow_0002:fp_pow_inst|Add36~29 ; wire \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[5] ; wire \fp_pow_0002:fp_pow_inst|Add36~33 ; wire \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[4] ; wire \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[3] ; wire \fp_pow_0002:fp_pow_inst|Add35~29 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[2]~1 ; wire \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[2] ; wire \fp_pow_0002:fp_pow_inst|Add35~37 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[1]~2 ; wire \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[1] ; wire \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[0]~_wirecell ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[0]~0 ; wire \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[0] ; wire \fp_pow_0002:fp_pow_inst|Add37~50 ; wire \fp_pow_0002:fp_pow_inst|Add37~46 ; wire \fp_pow_0002:fp_pow_inst|Add37~42 ; wire \fp_pow_0002:fp_pow_inst|Add37~38 ; wire \fp_pow_0002:fp_pow_inst|Add37~34 ; wire \fp_pow_0002:fp_pow_inst|Add37~30 ; wire \fp_pow_0002:fp_pow_inst|Add37~26 ; wire \fp_pow_0002:fp_pow_inst|Add37~22 ; wire \fp_pow_0002:fp_pow_inst|Add37~18 ; wire \fp_pow_0002:fp_pow_inst|Add37~14 ; wire \fp_pow_0002:fp_pow_inst|Add37~10 ; wire \fp_pow_0002:fp_pow_inst|Add37~6 ; wire \fp_pow_0002:fp_pow_inst|Add37~1 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStageSel1Dto0_uid639_fxpInPostAlignExp_uid123_fpPowrTest_b[0]~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add32~13 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|rightShiftStageSel1Dto0_uid639_fxpInPostAlignExp_uid123_fpPowrTest_b[1]~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[2][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|rightShiftStageSel3Dto2_uid628_fxpInPostAlignExp_uid123_fpPowrTest_b[0]~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|rightShiftStageSel5Dto4_uid617_fxpInPostAlignExp_uid123_fpPowrTest_b[0]~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|rightShiftStageSel5Dto4_uid617_fxpInPostAlignExp_uid123_fpPowrTest_b[1]~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[2][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Mux154~0 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStageSel3Dto2_uid628_fxpInPostAlignExp_uid123_fpPowrTest_b[1]~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[2][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Mux167~0 ; wire \fp_pow_0002:fp_pow_inst|Mux172~0 ; wire \fp_pow_0002:fp_pow_inst|Mux172~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][9]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|Add32~33 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][36] ; wire \rtl~282 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][8]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|Add32~17 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][35]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Mux164~0 ; wire \fp_pow_0002:fp_pow_inst|Mux162~0 ; wire \fp_pow_0002:fp_pow_inst|Mux163~0 ; wire \rtl~40 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|Add32~37 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|Mux165~0 ; wire \rtl~39 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|Add32~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][33]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Mux166~0 ; wire \rtl~38 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|Add32~25 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|Mux168~2 ; wire \fp_pow_0002:fp_pow_inst|Mux167~1 ; wire \rtl~37 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][4]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Add32~21 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][31] ; wire \rtl~281 ; wire \fp_pow_0002:fp_pow_inst|Mux178~0 ; wire \fp_pow_0002:fp_pow_inst|Mux178~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Add32~41 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][30] ; wire \rtl~280 ; wire \fp_pow_0002:fp_pow_inst|Mux179~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|Mux168~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][35] ; wire \rtl~274 ; wire \fp_pow_0002:fp_pow_inst|Add32~9 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][33] ; wire \rtl~273 ; wire \rtl~9 ; wire \fp_pow_0002:fp_pow_inst|Mux180~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Add32~29 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][28] ; wire \rtl~275 ; wire \fp_pow_0002:fp_pow_inst|Mux168~1 ; wire \rtl~276 ; wire \rtl~4 ; wire \fp_pow_0002:fp_pow_inst|Mux181~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add49~34 ; wire \fp_pow_0002:fp_pow_inst|Add49~2 ; wire \fp_pow_0002:fp_pow_inst|Add49~6 ; wire \fp_pow_0002:fp_pow_inst|Add49~10 ; wire \fp_pow_0002:fp_pow_inst|Add49~14 ; wire \fp_pow_0002:fp_pow_inst|Add49~18 ; wire \fp_pow_0002:fp_pow_inst|Add49~22 ; wire \fp_pow_0002:fp_pow_inst|Add49~26 ; wire \fp_pow_0002:fp_pow_inst|Add49~46 ; wire \fp_pow_0002:fp_pow_inst|Add49~42 ; wire \fp_pow_0002:fp_pow_inst|Add49~38 ; wire \fp_pow_0002:fp_pow_inst|Add49~29 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[11] ; wire \fp_pow_0002:fp_pow_inst|Add49~37 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[10] ; wire \fp_pow_0002:fp_pow_inst|Add49~41 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[9] ; wire \fp_pow_0002:fp_pow_inst|Add49~45 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[8] ; wire \fp_pow_0002:fp_pow_inst|Add49~25 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[7] ; wire \fp_pow_0002:fp_pow_inst|Add49~21 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[6] ; wire \fp_pow_0002:fp_pow_inst|Add49~17 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[5] ; wire \fp_pow_0002:fp_pow_inst|Add49~13 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[4] ; wire \fp_pow_0002:fp_pow_inst|Add49~9 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[3] ; wire \fp_pow_0002:fp_pow_inst|Add49~5 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[2] ; wire \fp_pow_0002:fp_pow_inst|Add49~1 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[1] ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[0]~0 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[0] ; wire \fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|Ram8~27 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[12] ; wire \fp_pow_0002:fp_pow_inst|Ram7~18 ; wire \fp_pow_0002:fp_pow_inst|Ram7~36 ; wire \fp_pow_0002:fp_pow_inst|Ram7~19 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|Ram7~29 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|Ram8~31 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[11] ; wire \fp_pow_0002:fp_pow_inst|Ram8~30 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Ram7~30 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|Ram7~28 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|Ram8~29 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[9] ; wire \fp_pow_0002:fp_pow_inst|Ram7~27 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[8] ; wire \fp_pow_0002:fp_pow_inst|Ram7~26 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[7] ; wire \fp_pow_0002:fp_pow_inst|Ram7~9 ; wire \fp_pow_0002:fp_pow_inst|Ram7~10 ; wire \fp_pow_0002:fp_pow_inst|Ram7~25 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|Ram7~24 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|Ram7~13 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Ram7~15 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Add38~182 ; wire \fp_pow_0002:fp_pow_inst|Add38~146 ; wire \fp_pow_0002:fp_pow_inst|Add38~150 ; wire \fp_pow_0002:fp_pow_inst|Add38~154 ; wire \fp_pow_0002:fp_pow_inst|Add38~158 ; wire \fp_pow_0002:fp_pow_inst|Add38~162 ; wire \fp_pow_0002:fp_pow_inst|Add38~166 ; wire \fp_pow_0002:fp_pow_inst|Add38~170 ; wire \fp_pow_0002:fp_pow_inst|Add38~174 ; wire \fp_pow_0002:fp_pow_inst|Add38~178 ; wire \fp_pow_0002:fp_pow_inst|Add38~125 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[0][0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|redist102_cmpReg_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0]~0 ; wire \fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[12] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[11] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[10] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[9] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[8] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[7] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[6] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[5] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[4] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[3] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[2] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[1] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|Add40~122 ; wire \fp_pow_0002:fp_pow_inst|Add40~134 ; wire \fp_pow_0002:fp_pow_inst|Add40~130 ; wire \fp_pow_0002:fp_pow_inst|Add40~138 ; wire \fp_pow_0002:fp_pow_inst|Add40~126 ; wire \fp_pow_0002:fp_pow_inst|Add40~118 ; wire \fp_pow_0002:fp_pow_inst|Add40~114 ; wire \fp_pow_0002:fp_pow_inst|Add40~110 ; wire \fp_pow_0002:fp_pow_inst|Add40~106 ; wire \fp_pow_0002:fp_pow_inst|Add40~102 ; wire \fp_pow_0002:fp_pow_inst|Add40~98 ; wire \fp_pow_0002:fp_pow_inst|Add40~94 ; wire \fp_pow_0002:fp_pow_inst|Add40~89 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[28] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[27] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[26] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[25] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[24] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[23] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[22] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[21] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[20] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[19] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[18] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[17] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[16] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[15] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[14] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[13] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|Add40~90 ; wire \fp_pow_0002:fp_pow_inst|Add40~86 ; wire \fp_pow_0002:fp_pow_inst|Add40~82 ; wire \fp_pow_0002:fp_pow_inst|Add40~78 ; wire \fp_pow_0002:fp_pow_inst|Add40~74 ; wire \fp_pow_0002:fp_pow_inst|Add40~6 ; wire \fp_pow_0002:fp_pow_inst|Add40~42 ; wire \fp_pow_0002:fp_pow_inst|Add40~26 ; wire \fp_pow_0002:fp_pow_inst|Add40~58 ; wire \fp_pow_0002:fp_pow_inst|Add40~18 ; wire \fp_pow_0002:fp_pow_inst|Add40~50 ; wire \fp_pow_0002:fp_pow_inst|Add40~34 ; wire \fp_pow_0002:fp_pow_inst|Add40~66 ; wire \fp_pow_0002:fp_pow_inst|Add40~14 ; wire \fp_pow_0002:fp_pow_inst|Add40~46 ; wire \fp_pow_0002:fp_pow_inst|Add40~30 ; wire \fp_pow_0002:fp_pow_inst|Add40~61 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[33] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[42] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[32] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[41] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[31] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[40] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[30] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[29] ; wire \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|Add40~62 ; wire \fp_pow_0002:fp_pow_inst|Add40~22 ; wire \fp_pow_0002:fp_pow_inst|Add40~54 ; wire \fp_pow_0002:fp_pow_inst|Add40~38 ; wire \fp_pow_0002:fp_pow_inst|Add40~70 ; wire \fp_pow_0002:fp_pow_inst|Add40~2 ; wire \fp_pow_0002:fp_pow_inst|Add40~9 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Mux203~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Add40~125 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|Add40~57 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|Mux211~0 ; wire \fp_pow_0002:fp_pow_inst|Add40~73 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|Add40~69 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|Add40~121 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][9] ; wire \rtl~82 ; wire \fp_pow_0002:fp_pow_inst|Add40~105 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|Add40~65 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|Mux207~0 ; wire \rtl~83 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Add40~97 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|Add40~45 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|Mux205~0 ; wire \fp_pow_0002:fp_pow_inst|Add40~53 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|Add40~81 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|Mux201~0 ; wire \fp_pow_0002:fp_pow_inst|Add40~129 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|Add40~41 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|Mux213~0 ; wire \fp_pow_0002:fp_pow_inst|Add40~113 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|Add40~49 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|Mux209~0 ; wire \rtl~84 ; wire \fp_pow_0002:fp_pow_inst|Add40~37 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|Add40~77 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|Mux200~0 ; wire \fp_pow_0002:fp_pow_inst|Add40~25 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|Add40~137 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|Mux212~0 ; wire \fp_pow_0002:fp_pow_inst|Add40~109 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|Add40~33 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|Mux208~0 ; wire \fp_pow_0002:fp_pow_inst|Add40~29 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|Add40~93 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|Mux204~0 ; wire \rtl~87 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add40~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|Add40~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|Add40~133 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][10] ; wire \rtl~85 ; wire \fp_pow_0002:fp_pow_inst|Add40~17 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|Add40~117 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|Mux210~0 ; wire \fp_pow_0002:fp_pow_inst|Add40~101 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|Add40~13 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|Mux206~0 ; wire \fp_pow_0002:fp_pow_inst|Add40~21 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|Add40~85 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|Mux202~0 ; wire \rtl~86 ; wire \rtl~88 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[9] ; wire \fp_pow_0002:fp_pow_inst|Add38~177 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][9] ; wire \rtl~100 ; wire \rtl~135 ; wire \rtl~139 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[8] ; wire \fp_pow_0002:fp_pow_inst|Add38~173 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][8] ; wire \rtl~124 ; wire \rtl~133 ; wire \rtl~138 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[7] ; wire \rtl~110 ; wire \rtl~131 ; wire \rtl~137 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[6] ; wire \fp_pow_0002:fp_pow_inst|Add38~169 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|Add38~165 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][6] ; wire \rtl~117 ; wire \rtl~129 ; wire \rtl~136 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[5] ; wire \fp_pow_0002:fp_pow_inst|Add38~161 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][5] ; wire \rtl~103 ; wire \rtl~127 ; wire \rtl~134 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[4] ; wire \rtl~121 ; wire \rtl~125 ; wire \rtl~132 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[3] ; wire \fp_pow_0002:fp_pow_inst|Add38~157 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][4] ; wire \rtl~107 ; wire \rtl~111 ; wire \rtl~130 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[2] ; wire \fp_pow_0002:fp_pow_inst|Add38~153 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Add38~149 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][2] ; wire \rtl~114 ; wire \rtl~118 ; wire \rtl~128 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[1] ; wire \fp_pow_0002:fp_pow_inst|Add38~145 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][1] ; wire \rtl~97 ; wire \rtl~104 ; wire \rtl~126 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[0] ; wire \fp_pow_0002:fp_pow_inst|Add38~181 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add41~186 ; wire \fp_pow_0002:fp_pow_inst|Add41~150 ; wire \fp_pow_0002:fp_pow_inst|Add41~154 ; wire \fp_pow_0002:fp_pow_inst|Add41~158 ; wire \fp_pow_0002:fp_pow_inst|Add41~162 ; wire \fp_pow_0002:fp_pow_inst|Add41~166 ; wire \fp_pow_0002:fp_pow_inst|Add41~170 ; wire \fp_pow_0002:fp_pow_inst|Add41~174 ; wire \fp_pow_0002:fp_pow_inst|Add41~178 ; wire \fp_pow_0002:fp_pow_inst|Add41~182 ; wire \fp_pow_0002:fp_pow_inst|Add41~129 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[43] ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[47]~feeder ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[47] ; wire \fp_pow_0002:fp_pow_inst|Ram8~9 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[46] ; wire \fp_pow_0002:fp_pow_inst|Ram8~11 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[45] ; wire \fp_pow_0002:fp_pow_inst|Ram8~13 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[44] ; wire \fp_pow_0002:fp_pow_inst|Ram8~15 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[43] ; wire \fp_pow_0002:fp_pow_inst|Ram8~17 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[42] ; wire \fp_pow_0002:fp_pow_inst|Ram7~6 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|Ram7~7 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|Ram8~19 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[41] ; wire \fp_pow_0002:fp_pow_inst|Ram8~21 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[40] ; wire \fp_pow_0002:fp_pow_inst|Ram7~8 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|Ram7~33 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|Ram8~23 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[39] ; wire \fp_pow_0002:fp_pow_inst|Ram7~11 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|Ram7~31 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|Ram8~24 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[37] ; wire \fp_pow_0002:fp_pow_inst|Ram8~7 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[36] ; wire \fp_pow_0002:fp_pow_inst|Ram7~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|Ram7~43 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|Ram8~6 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[35] ; wire \fp_pow_0002:fp_pow_inst|Ram8~5 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[34] ; wire \fp_pow_0002:fp_pow_inst|Ram7~4 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|Ram7~44 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|Ram8~4 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[33] ; wire \fp_pow_0002:fp_pow_inst|Ram8~3 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[32] ; wire \fp_pow_0002:fp_pow_inst|Ram7~3 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|Ram8~2 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[31] ; wire \fp_pow_0002:fp_pow_inst|Ram7~2 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|Ram8~1 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[30] ; wire \fp_pow_0002:fp_pow_inst|Ram7~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|Ram7~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|Ram8~0 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[29] ; wire \fp_pow_0002:fp_pow_inst|Ram7~42 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|Ram8~8 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[28] ; wire \fp_pow_0002:fp_pow_inst|Ram8~10 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[27] ; wire \fp_pow_0002:fp_pow_inst|Ram7~41 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|Ram8~12 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[26] ; wire \fp_pow_0002:fp_pow_inst|Ram7~40 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|Ram8~14 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[25] ; wire \fp_pow_0002:fp_pow_inst|Ram7~39 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|Ram8~16 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[24] ; wire \fp_pow_0002:fp_pow_inst|Ram7~38 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|Ram8~18 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[23] ; wire \fp_pow_0002:fp_pow_inst|Ram7~37 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|Ram8~20 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[22] ; wire \fp_pow_0002:fp_pow_inst|Ram7~35 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|Ram8~22 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[21] ; wire \fp_pow_0002:fp_pow_inst|Ram7~34 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|Ram7~32 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|Ram7~12 ; wire \fp_pow_0002:fp_pow_inst|Ram7~14 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|Ram8~25 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[18] ; wire \fp_pow_0002:fp_pow_inst|Ram7~16 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|Ram8~26 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[17] ; wire \fp_pow_0002:fp_pow_inst|Ram7~17 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|Ram7~23 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|Ram8~28 ; wire \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[16] ; wire \fp_pow_0002:fp_pow_inst|Ram7~22 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|Ram7~21 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|Ram7~20 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|Add38~126 ; wire \fp_pow_0002:fp_pow_inst|Add38~130 ; wire \fp_pow_0002:fp_pow_inst|Add38~134 ; wire \fp_pow_0002:fp_pow_inst|Add38~138 ; wire \fp_pow_0002:fp_pow_inst|Add38~142 ; wire \fp_pow_0002:fp_pow_inst|Add38~122 ; wire \fp_pow_0002:fp_pow_inst|Add38~118 ; wire \fp_pow_0002:fp_pow_inst|Add38~110 ; wire \fp_pow_0002:fp_pow_inst|Add38~102 ; wire \fp_pow_0002:fp_pow_inst|Add38~94 ; wire \fp_pow_0002:fp_pow_inst|Add38~86 ; wire \fp_pow_0002:fp_pow_inst|Add38~78 ; wire \fp_pow_0002:fp_pow_inst|Add38~70 ; wire \fp_pow_0002:fp_pow_inst|Add38~62 ; wire \fp_pow_0002:fp_pow_inst|Add38~54 ; wire \fp_pow_0002:fp_pow_inst|Add38~46 ; wire \fp_pow_0002:fp_pow_inst|Add38~38 ; wire \fp_pow_0002:fp_pow_inst|Add38~2 ; wire \fp_pow_0002:fp_pow_inst|Add38~10 ; wire \fp_pow_0002:fp_pow_inst|Add38~14 ; wire \fp_pow_0002:fp_pow_inst|Add38~18 ; wire \fp_pow_0002:fp_pow_inst|Add38~22 ; wire \fp_pow_0002:fp_pow_inst|Add38~26 ; wire \fp_pow_0002:fp_pow_inst|Add38~30 ; wire \fp_pow_0002:fp_pow_inst|Add38~34 ; wire \fp_pow_0002:fp_pow_inst|Add38~114 ; wire \fp_pow_0002:fp_pow_inst|Add38~106 ; wire \fp_pow_0002:fp_pow_inst|Add38~98 ; wire \fp_pow_0002:fp_pow_inst|Add38~90 ; wire \fp_pow_0002:fp_pow_inst|Add38~82 ; wire \fp_pow_0002:fp_pow_inst|Add38~74 ; wire \fp_pow_0002:fp_pow_inst|Add38~66 ; wire \fp_pow_0002:fp_pow_inst|Add38~58 ; wire \fp_pow_0002:fp_pow_inst|Add38~50 ; wire \fp_pow_0002:fp_pow_inst|Add38~42 ; wire \fp_pow_0002:fp_pow_inst|Add38~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][45] ; wire \fp_pow_0002:fp_pow_inst|Add38~41 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][44] ; wire \fp_pow_0002:fp_pow_inst|Add38~49 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][43] ; wire \rtl~277 ; wire \fp_pow_0002:fp_pow_inst|Mux228~0 ; wire \fp_pow_0002:fp_pow_inst|Mux268~0 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[42] ; wire \rtl~283 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[41] ; wire \fp_pow_0002:fp_pow_inst|Add38~57 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|Mux227~0 ; wire \fp_pow_0002:fp_pow_inst|Mux225~0 ; wire \fp_pow_0002:fp_pow_inst|Mux226~0 ; wire \rtl~57 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[40] ; wire \fp_pow_0002:fp_pow_inst|Add38~65 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|Mux228~1 ; wire \rtl~60 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[39] ; wire \fp_pow_0002:fp_pow_inst|Add38~73 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|Add38~81 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][39] ; wire \rtl~284 ; wire \rtl~65 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[38] ; wire \fp_pow_0002:fp_pow_inst|Add38~89 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][38] ; wire \rtl~285 ; wire \rtl~70 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[37] ; wire \fp_pow_0002:fp_pow_inst|Add38~97 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][37] ; wire \rtl~279 ; wire \rtl~73 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[36] ; wire \fp_pow_0002:fp_pow_inst|Add38~105 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][36] ; wire \rtl~278 ; wire \rtl~76 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[35] ; wire \fp_pow_0002:fp_pow_inst|Add38~113 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|Mux186~0 ; wire \fp_pow_0002:fp_pow_inst|Mux190~0 ; wire \fp_pow_0002:fp_pow_inst|Mux182~0 ; wire \rtl~23 ; wire \rtl~79 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[34] ; wire \fp_pow_0002:fp_pow_inst|Mux187~0 ; wire \fp_pow_0002:fp_pow_inst|Mux191~0 ; wire \fp_pow_0002:fp_pow_inst|Mux183~0 ; wire \rtl~21 ; wire \rtl~31 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[33] ; wire \fp_pow_0002:fp_pow_inst|Add38~33 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|Mux184~0 ; wire \fp_pow_0002:fp_pow_inst|Mux188~0 ; wire \fp_pow_0002:fp_pow_inst|Mux192~0 ; wire \rtl~19 ; wire \rtl~28 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[32] ; wire \fp_pow_0002:fp_pow_inst|Add38~29 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|Add38~25 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|Mux185~0 ; wire \fp_pow_0002:fp_pow_inst|Mux189~0 ; wire \fp_pow_0002:fp_pow_inst|Mux193~0 ; wire \rtl~17 ; wire \rtl~24 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[31] ; wire \fp_pow_0002:fp_pow_inst|Mux194~0 ; wire \rtl~15 ; wire \rtl~22 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[30] ; wire \fp_pow_0002:fp_pow_inst|Add38~21 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|Add38~17 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|Mux195~0 ; wire \rtl~13 ; wire \rtl~20 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[29] ; wire \fp_pow_0002:fp_pow_inst|Mux196~0 ; wire \rtl~11 ; wire \rtl~18 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[28] ; wire \fp_pow_0002:fp_pow_inst|Add38~13 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|Add38~9 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|Mux197~0 ; wire \rtl~12 ; wire \rtl~16 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[27] ; wire \fp_pow_0002:fp_pow_inst|Add38~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|Mux198~0 ; wire \rtl~10 ; wire \rtl~14 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[26] ; wire \fp_pow_0002:fp_pow_inst|Add38~37 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|Mux199~0 ; wire \rtl~41 ; wire \rtl~42 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[25] ; wire \fp_pow_0002:fp_pow_inst|Add38~45 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][25] ; wire \rtl~43 ; wire \rtl~44 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[24] ; wire \rtl~45 ; wire \rtl~46 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[23] ; wire \fp_pow_0002:fp_pow_inst|Add38~53 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][24] ; wire \rtl~50 ; wire \rtl~51 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[22] ; wire \fp_pow_0002:fp_pow_inst|Add38~61 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|Add38~69 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][22] ; wire \rtl~55 ; wire \rtl~56 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[21] ; wire \rtl~58 ; wire \rtl~59 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[20] ; wire \fp_pow_0002:fp_pow_inst|Add38~77 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|Add38~85 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][20] ; wire \rtl~61 ; wire \rtl~62 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[19] ; wire \rtl~66 ; wire \rtl~67 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[18] ; wire \fp_pow_0002:fp_pow_inst|Add38~93 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|Add38~101 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][18] ; wire \rtl~71 ; wire \rtl~72 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[17] ; wire \rtl~74 ; wire \rtl~75 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[16] ; wire \fp_pow_0002:fp_pow_inst|Add38~109 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|Add38~117 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][16] ; wire \rtl~77 ; wire \rtl~78 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[15] ; wire \fp_pow_0002:fp_pow_inst|Add38~121 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][15] ; wire \rtl~80 ; wire \rtl~81 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[14] ; wire \fp_pow_0002:fp_pow_inst|Add38~141 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][14] ; wire \rtl~89 ; wire \rtl~93 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[13] ; wire \rtl~92 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[12] ; wire \fp_pow_0002:fp_pow_inst|Add38~137 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|Add38~133 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][12] ; wire \rtl~91 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[11] ; wire \rtl~90 ; wire \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[10] ; wire \fp_pow_0002:fp_pow_inst|Add38~129 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|Add41~130 ; wire \fp_pow_0002:fp_pow_inst|Add41~134 ; wire \fp_pow_0002:fp_pow_inst|Add41~138 ; wire \fp_pow_0002:fp_pow_inst|Add41~142 ; wire \fp_pow_0002:fp_pow_inst|Add41~146 ; wire \fp_pow_0002:fp_pow_inst|Add41~126 ; wire \fp_pow_0002:fp_pow_inst|Add41~118 ; wire \fp_pow_0002:fp_pow_inst|Add41~110 ; wire \fp_pow_0002:fp_pow_inst|Add41~102 ; wire \fp_pow_0002:fp_pow_inst|Add41~94 ; wire \fp_pow_0002:fp_pow_inst|Add41~86 ; wire \fp_pow_0002:fp_pow_inst|Add41~78 ; wire \fp_pow_0002:fp_pow_inst|Add41~70 ; wire \fp_pow_0002:fp_pow_inst|Add41~62 ; wire \fp_pow_0002:fp_pow_inst|Add41~54 ; wire \fp_pow_0002:fp_pow_inst|Add41~46 ; wire \fp_pow_0002:fp_pow_inst|Add41~38 ; wire \fp_pow_0002:fp_pow_inst|Add41~2 ; wire \fp_pow_0002:fp_pow_inst|Add41~10 ; wire \fp_pow_0002:fp_pow_inst|Add41~14 ; wire \fp_pow_0002:fp_pow_inst|Add41~18 ; wire \fp_pow_0002:fp_pow_inst|Add41~22 ; wire \fp_pow_0002:fp_pow_inst|Add41~26 ; wire \fp_pow_0002:fp_pow_inst|Add41~30 ; wire \fp_pow_0002:fp_pow_inst|Add41~34 ; wire \fp_pow_0002:fp_pow_inst|Add41~122 ; wire \fp_pow_0002:fp_pow_inst|Add41~114 ; wire \fp_pow_0002:fp_pow_inst|Add41~106 ; wire \fp_pow_0002:fp_pow_inst|Add41~98 ; wire \fp_pow_0002:fp_pow_inst|Add41~90 ; wire \fp_pow_0002:fp_pow_inst|Add41~82 ; wire \fp_pow_0002:fp_pow_inst|Add41~74 ; wire \fp_pow_0002:fp_pow_inst|Add41~66 ; wire \fp_pow_0002:fp_pow_inst|Add41~58 ; wire \fp_pow_0002:fp_pow_inst|Add41~50 ; wire \fp_pow_0002:fp_pow_inst|Add41~42 ; wire \fp_pow_0002:fp_pow_inst|Add41~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[9] ; wire \fp_pow_0002:fp_pow_inst|Add41~133 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][10]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[10] ; wire \fp_pow_0002:fp_pow_inst|Add41~137 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][11]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][11]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[11] ; wire \fp_pow_0002:fp_pow_inst|Add41~141 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[12] ; wire \fp_pow_0002:fp_pow_inst|Add41~145 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][13]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][13]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][13]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][13]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][13]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[13] ; wire \fp_pow_0002:fp_pow_inst|Add41~125 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][14]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][14]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][14]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][14]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[14] ; wire \fp_pow_0002:fp_pow_inst|Add41~117 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][15]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][15]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[15] ; wire \fp_pow_0002:fp_pow_inst|Add41~109 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][16]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][16]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[16] ; wire \fp_pow_0002:fp_pow_inst|Add41~101 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][17]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][17]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[17] ; wire \fp_pow_0002:fp_pow_inst|Add41~93 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][18]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][18]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[18] ; wire \fp_pow_0002:fp_pow_inst|Add41~85 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][19]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][19]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[19] ; wire \fp_pow_0002:fp_pow_inst|Add41~77 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[20] ; wire \fp_pow_0002:fp_pow_inst|Add41~69 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][21]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[21] ; wire \fp_pow_0002:fp_pow_inst|Add41~61 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][22]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][22]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[22] ; wire \fp_pow_0002:fp_pow_inst|Add41~53 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][23]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][23]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][23]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][23]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[23] ; wire \fp_pow_0002:fp_pow_inst|Add41~45 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[24] ; wire \fp_pow_0002:fp_pow_inst|Add41~37 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][25]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][25]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][25]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[25] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_c0[1][17]~0 ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[1][0]~0 ; wire \fp_pow_0002:fp_pow_inst|Add41~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 ; wire \fp_pow_0002:fp_pow_inst|Add41~9 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ; wire \fp_pow_0002:fp_pow_inst|Add41~13 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ; wire \fp_pow_0002:fp_pow_inst|Add41~17 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ; wire \fp_pow_0002:fp_pow_inst|Add41~21 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 ; wire \fp_pow_0002:fp_pow_inst|Add41~25 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ; wire \fp_pow_0002:fp_pow_inst|Add41~29 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ; wire \fp_pow_0002:fp_pow_inst|Add41~33 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[8] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[10] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[11] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[12] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[13] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][14]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][17]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][20]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[0] ; wire \fp_pow_0002:fp_pow_inst|Add42~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][17] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[1] ; wire \fp_pow_0002:fp_pow_inst|Add42~2 ; wire \fp_pow_0002:fp_pow_inst|Add42~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[2] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][18] ; wire \fp_pow_0002:fp_pow_inst|Add42~6 ; wire \fp_pow_0002:fp_pow_inst|Add42~9 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[3] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][19] ; wire \fp_pow_0002:fp_pow_inst|Add42~10 ; wire \fp_pow_0002:fp_pow_inst|Add42~13 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][20] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[4] ; wire \fp_pow_0002:fp_pow_inst|Add42~14 ; wire \fp_pow_0002:fp_pow_inst|Add42~17 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][21] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[5] ; wire \fp_pow_0002:fp_pow_inst|Add42~18 ; wire \fp_pow_0002:fp_pow_inst|Add42~21 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][22] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[6] ; wire \fp_pow_0002:fp_pow_inst|Add42~22 ; wire \fp_pow_0002:fp_pow_inst|Add42~25 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][23] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[7] ; wire \fp_pow_0002:fp_pow_inst|Add42~26 ; wire \fp_pow_0002:fp_pow_inst|Add42~29 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][24] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[8] ; wire \fp_pow_0002:fp_pow_inst|Add42~30 ; wire \fp_pow_0002:fp_pow_inst|Add42~33 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[9] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][25] ; wire \fp_pow_0002:fp_pow_inst|Add42~34 ; wire \fp_pow_0002:fp_pow_inst|Add42~37 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][26] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[10] ; wire \fp_pow_0002:fp_pow_inst|Add42~38 ; wire \fp_pow_0002:fp_pow_inst|Add42~41 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[11] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][27] ; wire \fp_pow_0002:fp_pow_inst|Add42~42 ; wire \fp_pow_0002:fp_pow_inst|Add42~45 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[12] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][28] ; wire \fp_pow_0002:fp_pow_inst|Add42~46 ; wire \fp_pow_0002:fp_pow_inst|Add42~49 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][29] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[13] ; wire \fp_pow_0002:fp_pow_inst|Add42~50 ; wire \fp_pow_0002:fp_pow_inst|Add42~53 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[14] ; wire \fp_pow_0002:fp_pow_inst|Add42~54 ; wire \fp_pow_0002:fp_pow_inst|Add42~57 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[15] ; wire \fp_pow_0002:fp_pow_inst|Add42~58 ; wire \fp_pow_0002:fp_pow_inst|Add42~61 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[16] ; wire \fp_pow_0002:fp_pow_inst|Add42~62 ; wire \fp_pow_0002:fp_pow_inst|Add42~65 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[17] ; wire \fp_pow_0002:fp_pow_inst|Add42~66 ; wire \fp_pow_0002:fp_pow_inst|Add42~69 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[18] ; wire \fp_pow_0002:fp_pow_inst|Add42~70 ; wire \fp_pow_0002:fp_pow_inst|Add42~73 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[19] ; wire \fp_pow_0002:fp_pow_inst|Add42~74 ; wire \fp_pow_0002:fp_pow_inst|Add42~77 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[20] ; wire \fp_pow_0002:fp_pow_inst|Add42~78 ; wire \fp_pow_0002:fp_pow_inst|Add42~81 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[21] ; wire \fp_pow_0002:fp_pow_inst|Add42~82 ; wire \fp_pow_0002:fp_pow_inst|Add42~85 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[22] ; wire \fp_pow_0002:fp_pow_inst|Add42~86 ; wire \fp_pow_0002:fp_pow_inst|Add42~89 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[23] ; wire \fp_pow_0002:fp_pow_inst|Add42~90 ; wire \fp_pow_0002:fp_pow_inst|Add42~93 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|Add42~94 ; wire \fp_pow_0002:fp_pow_inst|Add42~97 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|Add41~157 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Add41~161 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Add41~165 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Add41~169 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|Add41~173 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|Add41~177 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|Add41~181 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][8]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][14]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist36|delay_signals[0][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist36|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][2]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add43~73 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Add43~74 ; wire \fp_pow_0002:fp_pow_inst|Add43~77 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][2]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][2]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|Add43~78 ; wire \fp_pow_0002:fp_pow_inst|Add43~81 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Add43~82 ; wire \fp_pow_0002:fp_pow_inst|Add43~85 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][4]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][4]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Add43~86 ; wire \fp_pow_0002:fp_pow_inst|Add43~89 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|Add43~90 ; wire \fp_pow_0002:fp_pow_inst|Add43~93 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|Add43~94 ; wire \fp_pow_0002:fp_pow_inst|Add43~97 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|Add43~98 ; wire \fp_pow_0002:fp_pow_inst|Add43~101 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][8]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][8]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|Add43~102 ; wire \fp_pow_0002:fp_pow_inst|Add43~105 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][9]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][9]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|Add43~106 ; wire \fp_pow_0002:fp_pow_inst|Add43~109 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][10]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|Add43~110 ; wire \fp_pow_0002:fp_pow_inst|Add43~113 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][11]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|Add43~114 ; wire \fp_pow_0002:fp_pow_inst|Add43~117 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][12]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|Add43~118 ; wire \fp_pow_0002:fp_pow_inst|Add43~121 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][13]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][13]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|Add43~122 ; wire \fp_pow_0002:fp_pow_inst|Add43~125 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][14]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|Add43~126 ; wire \fp_pow_0002:fp_pow_inst|Add43~129 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][15]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][40] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][15]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|Add43~130 ; wire \fp_pow_0002:fp_pow_inst|Add43~133 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][41] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][16]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|Add43~134 ; wire \fp_pow_0002:fp_pow_inst|Add43~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][42] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][17]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|Add43~2 ; wire \fp_pow_0002:fp_pow_inst|Add43~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][18]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][43] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][18]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|Add43~6 ; wire \fp_pow_0002:fp_pow_inst|Add43~9 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][19]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][44] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|Add43~10 ; wire \fp_pow_0002:fp_pow_inst|Add43~13 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][45] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][20]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][20]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|Add43~14 ; wire \fp_pow_0002:fp_pow_inst|Add43~17 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][46] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][21]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|Add43~18 ; wire \fp_pow_0002:fp_pow_inst|Add43~21 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][22]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][47] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|Add43~22 ; wire \fp_pow_0002:fp_pow_inst|Add43~25 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][48] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][23]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|Add43~26 ; wire \fp_pow_0002:fp_pow_inst|Add43~29 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][24]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][49] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][24]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|Add43~30 ; wire \fp_pow_0002:fp_pow_inst|Add43~33 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|Add43~34 ; wire \fp_pow_0002:fp_pow_inst|Add43~37 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|Add43~38 ; wire \fp_pow_0002:fp_pow_inst|Add43~41 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][27]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|Add43~42 ; wire \fp_pow_0002:fp_pow_inst|Add43~45 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][28]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|Add43~46 ; wire \fp_pow_0002:fp_pow_inst|Add43~49 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|Add43~50 ; wire \fp_pow_0002:fp_pow_inst|Add43~53 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][30]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|Add43~54 ; wire \fp_pow_0002:fp_pow_inst|Add43~57 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|Add43~58 ; wire \fp_pow_0002:fp_pow_inst|Add43~61 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][32]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|Add43~62 ; wire \fp_pow_0002:fp_pow_inst|Add43~65 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|Add43~66 ; wire \fp_pow_0002:fp_pow_inst|Add43~69 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][0]~1 ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][1]~2 ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][2]~3 ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][3]~4 ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][4]~5 ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][5]~6 ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][6]~7 ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][7]~8 ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][8]~9 ; wire \fp_pow_0002:fp_pow_inst|Add41~149 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|Add41~153 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[8] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][24]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_a0[0][17]~0 ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][40]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][39]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][38]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][37]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][35]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][34]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][33]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][31]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][28]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][26]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][25]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][23]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][23]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][22]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][21]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][20]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][20]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][19]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][17]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][17]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][16]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][13]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][12]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][11]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][9]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][9]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][8]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][8]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_b0[1] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_a0[2] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[1][2] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_b0[0] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[0][2] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_a0[1] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[1][1] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_a0[0] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[1][0] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[0][1] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~14 ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~10 ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~6 ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~1 ; wire \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_b0[2] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[2][2] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~5 ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[2][1] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[2][0] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~9 ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~14 ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~10 ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~6 ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~1 ; wire \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~5 ; wire \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~9 ; wire \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~13 ; wire \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][2]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~13 ; wire \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[0][0] ; wire \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add45~162 ; wire \fp_pow_0002:fp_pow_inst|Add45~158 ; wire \fp_pow_0002:fp_pow_inst|Add45~154 ; wire \fp_pow_0002:fp_pow_inst|Add45~150 ; wire \fp_pow_0002:fp_pow_inst|Add45~146 ; wire \fp_pow_0002:fp_pow_inst|Add45~142 ; wire \fp_pow_0002:fp_pow_inst|Add45~138 ; wire \fp_pow_0002:fp_pow_inst|Add45~134 ; wire \fp_pow_0002:fp_pow_inst|Add45~130 ; wire \fp_pow_0002:fp_pow_inst|Add45~126 ; wire \fp_pow_0002:fp_pow_inst|Add45~122 ; wire \fp_pow_0002:fp_pow_inst|Add45~118 ; wire \fp_pow_0002:fp_pow_inst|Add45~114 ; wire \fp_pow_0002:fp_pow_inst|Add45~110 ; wire \fp_pow_0002:fp_pow_inst|Add45~106 ; wire \fp_pow_0002:fp_pow_inst|Add45~102 ; wire \fp_pow_0002:fp_pow_inst|Add45~98 ; wire \fp_pow_0002:fp_pow_inst|Add45~94 ; wire \fp_pow_0002:fp_pow_inst|Add45~90 ; wire \fp_pow_0002:fp_pow_inst|Add45~86 ; wire \fp_pow_0002:fp_pow_inst|Add45~82 ; wire \fp_pow_0002:fp_pow_inst|Add45~78 ; wire \fp_pow_0002:fp_pow_inst|Add45~2 ; wire \fp_pow_0002:fp_pow_inst|Add45~6 ; wire \fp_pow_0002:fp_pow_inst|Add45~10 ; wire \fp_pow_0002:fp_pow_inst|Add45~14 ; wire \fp_pow_0002:fp_pow_inst|Add45~18 ; wire \fp_pow_0002:fp_pow_inst|Add45~22 ; wire \fp_pow_0002:fp_pow_inst|Add45~26 ; wire \fp_pow_0002:fp_pow_inst|Add45~30 ; wire \fp_pow_0002:fp_pow_inst|Add45~34 ; wire \fp_pow_0002:fp_pow_inst|Add45~38 ; wire \fp_pow_0002:fp_pow_inst|Add45~42 ; wire \fp_pow_0002:fp_pow_inst|Add45~46 ; wire \fp_pow_0002:fp_pow_inst|Add45~50 ; wire \fp_pow_0002:fp_pow_inst|Add45~54 ; wire \fp_pow_0002:fp_pow_inst|Add45~58 ; wire \fp_pow_0002:fp_pow_inst|Add45~62 ; wire \fp_pow_0002:fp_pow_inst|Add45~66 ; wire \fp_pow_0002:fp_pow_inst|Add45~70 ; wire \fp_pow_0002:fp_pow_inst|Add45~73 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][1]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][2]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][2]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][2]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][4]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][4]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][5]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][7]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][39]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][38]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][36]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][35]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][34]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][33]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|Add45~69 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|Add45~65 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][30]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|Add45~61 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|Add45~57 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|Add45~53 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][28]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|Add45~49 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|Add45~45 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][26]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][25]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|Add45~41 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|Add45~37 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|Add45~33 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][22]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|Add45~29 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|Add45~25 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][21]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|Add45~21 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][19]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|Add45~17 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|Add45~13 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|Add45~9 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|Add45~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][16]~feeder ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|Add45~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|Add45~77 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|Add45~81 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|Add45~85 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|Add45~89 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|Add45~93 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|Add45~97 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|Add45~101 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|Add45~105 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|Add45~109 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|Add45~113 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|Add45~117 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Add45~121 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Add45~125 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|Add45~129 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Add45~133 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add46~158 ; wire \fp_pow_0002:fp_pow_inst|Add46~154 ; wire \fp_pow_0002:fp_pow_inst|Add46~150 ; wire \fp_pow_0002:fp_pow_inst|Add46~146 ; wire \fp_pow_0002:fp_pow_inst|Add46~142 ; wire \fp_pow_0002:fp_pow_inst|Add46~138 ; wire \fp_pow_0002:fp_pow_inst|Add46~134 ; wire \fp_pow_0002:fp_pow_inst|Add46~130 ; wire \fp_pow_0002:fp_pow_inst|Add46~126 ; wire \fp_pow_0002:fp_pow_inst|Add46~122 ; wire \fp_pow_0002:fp_pow_inst|Add46~118 ; wire \fp_pow_0002:fp_pow_inst|Add46~114 ; wire \fp_pow_0002:fp_pow_inst|Add46~110 ; wire \fp_pow_0002:fp_pow_inst|Add46~102 ; wire \fp_pow_0002:fp_pow_inst|Add46~94 ; wire \fp_pow_0002:fp_pow_inst|Add46~2 ; wire \fp_pow_0002:fp_pow_inst|Add46~6 ; wire \fp_pow_0002:fp_pow_inst|Add46~10 ; wire \fp_pow_0002:fp_pow_inst|Add46~14 ; wire \fp_pow_0002:fp_pow_inst|Add46~18 ; wire \fp_pow_0002:fp_pow_inst|Add46~22 ; wire \fp_pow_0002:fp_pow_inst|Add46~26 ; wire \fp_pow_0002:fp_pow_inst|Add46~30 ; wire \fp_pow_0002:fp_pow_inst|Add46~34 ; wire \fp_pow_0002:fp_pow_inst|Add46~38 ; wire \fp_pow_0002:fp_pow_inst|Add46~42 ; wire \fp_pow_0002:fp_pow_inst|Add46~46 ; wire \fp_pow_0002:fp_pow_inst|Add46~50 ; wire \fp_pow_0002:fp_pow_inst|Add46~54 ; wire \fp_pow_0002:fp_pow_inst|Add46~58 ; wire \fp_pow_0002:fp_pow_inst|Add46~62 ; wire \fp_pow_0002:fp_pow_inst|Add46~66 ; wire \fp_pow_0002:fp_pow_inst|Add46~70 ; wire \fp_pow_0002:fp_pow_inst|Add46~74 ; wire \fp_pow_0002:fp_pow_inst|Add46~78 ; wire \fp_pow_0002:fp_pow_inst|Add46~82 ; wire \fp_pow_0002:fp_pow_inst|Add46~86 ; wire \fp_pow_0002:fp_pow_inst|Add46~90 ; wire \fp_pow_0002:fp_pow_inst|Add46~106 ; wire \fp_pow_0002:fp_pow_inst|Add46~97 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist85|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add50~2 ; wire \fp_pow_0002:fp_pow_inst|Add50~6 ; wire \fp_pow_0002:fp_pow_inst|Add50~10 ; wire \fp_pow_0002:fp_pow_inst|Add50~14 ; wire \fp_pow_0002:fp_pow_inst|Add50~18 ; wire \fp_pow_0002:fp_pow_inst|Add50~22 ; wire \fp_pow_0002:fp_pow_inst|Add50~26 ; wire \fp_pow_0002:fp_pow_inst|Add50~30 ; wire \fp_pow_0002:fp_pow_inst|Add50~50 ; wire \fp_pow_0002:fp_pow_inst|Add50~46 ; wire \fp_pow_0002:fp_pow_inst|Add50~42 ; wire \fp_pow_0002:fp_pow_inst|Add50~38 ; wire \fp_pow_0002:fp_pow_inst|Add50~33 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[12] ; wire \fp_pow_0002:fp_pow_inst|Add50~37 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[11] ; wire \fp_pow_0002:fp_pow_inst|Add50~41 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[10] ; wire \fp_pow_0002:fp_pow_inst|Add50~45 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[9] ; wire \fp_pow_0002:fp_pow_inst|Add50~49 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[8] ; wire \fp_pow_0002:fp_pow_inst|Add50~29 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[7] ; wire \fp_pow_0002:fp_pow_inst|Add50~25 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[6] ; wire \fp_pow_0002:fp_pow_inst|Add50~21 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[5] ; wire \fp_pow_0002:fp_pow_inst|Add50~17 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[4] ; wire \fp_pow_0002:fp_pow_inst|Add50~13 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[3] ; wire \fp_pow_0002:fp_pow_inst|Add50~9 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Add50~5 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[1] ; wire \fp_pow_0002:fp_pow_inst|Add50~1 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[0] ; wire \fp_pow_0002:fp_pow_inst|Add61~50 ; wire \fp_pow_0002:fp_pow_inst|Add61~46 ; wire \fp_pow_0002:fp_pow_inst|Add61~42 ; wire \fp_pow_0002:fp_pow_inst|Add61~38 ; wire \fp_pow_0002:fp_pow_inst|Add61~34 ; wire \fp_pow_0002:fp_pow_inst|Add61~30 ; wire \fp_pow_0002:fp_pow_inst|Add61~26 ; wire \fp_pow_0002:fp_pow_inst|Add61~22 ; wire \fp_pow_0002:fp_pow_inst|Add61~18 ; wire \fp_pow_0002:fp_pow_inst|Add61~14 ; wire \fp_pow_0002:fp_pow_inst|Add61~10 ; wire \fp_pow_0002:fp_pow_inst|Add61~6 ; wire \fp_pow_0002:fp_pow_inst|Add61~1 ; wire \fp_pow_0002:fp_pow_inst|infCase4_uid187_fpPowrTest_q_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:infCase4_uid187_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|infCase0_uid195_fpPowrTest_q_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:infCase0_uid195_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|redist81_sticky_ena_q[0]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist81_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[3] ; wire \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Add64~1 ; wire \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[3]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|Equal32~0 ; wire \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_eq ; wire \fp_pow_0002:fp_pow_inst|Add64~0 ; wire \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[2] ; wire \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[4]~0 ; wire \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[4] ; wire \fp_pow_0002:fp_pow_inst|Equal31~0 ; wire \fp_pow_0002:fp_pow_inst|redist83_cmpReg_q[0] ; wire \fp_pow_0002:fp_pow_inst|redist83_sticky_ena_q[0]~0 ; wire \fp_pow_0002:fp_pow_inst|redist83_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|Add65~122 ; wire \fp_pow_0002:fp_pow_inst|Add65~118 ; wire \fp_pow_0002:fp_pow_inst|Add65~114 ; wire \fp_pow_0002:fp_pow_inst|Add65~110 ; wire \fp_pow_0002:fp_pow_inst|Add65~106 ; wire \fp_pow_0002:fp_pow_inst|Add65~102 ; wire \fp_pow_0002:fp_pow_inst|Add65~98 ; wire \fp_pow_0002:fp_pow_inst|Add65~94 ; wire \fp_pow_0002:fp_pow_inst|Add65~90 ; wire \fp_pow_0002:fp_pow_inst|Add65~86 ; wire \fp_pow_0002:fp_pow_inst|Add65~82 ; wire \fp_pow_0002:fp_pow_inst|Add65~78 ; wire \fp_pow_0002:fp_pow_inst|Add65~74 ; wire \fp_pow_0002:fp_pow_inst|Add65~70 ; wire \fp_pow_0002:fp_pow_inst|Add65~66 ; wire \fp_pow_0002:fp_pow_inst|Add65~62 ; wire \fp_pow_0002:fp_pow_inst|Add65~58 ; wire \fp_pow_0002:fp_pow_inst|Add65~54 ; wire \fp_pow_0002:fp_pow_inst|Add65~50 ; wire \fp_pow_0002:fp_pow_inst|Add65~46 ; wire \fp_pow_0002:fp_pow_inst|Add65~42 ; wire \fp_pow_0002:fp_pow_inst|Add65~38 ; wire \fp_pow_0002:fp_pow_inst|Add65~34 ; wire \fp_pow_0002:fp_pow_inst|Add65~30 ; wire \fp_pow_0002:fp_pow_inst|Add65~26 ; wire \fp_pow_0002:fp_pow_inst|Add65~22 ; wire \fp_pow_0002:fp_pow_inst|Add65~18 ; wire \fp_pow_0002:fp_pow_inst|Add65~14 ; wire \fp_pow_0002:fp_pow_inst|Add65~10 ; wire \fp_pow_0002:fp_pow_inst|Add65~6 ; wire \fp_pow_0002:fp_pow_inst|Add65~1 ; wire \fp_pow_0002:fp_pow_inst|expFracXGTExpFracOne_uid155_fpPowrTest_o[33] ; wire \fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[2] ; wire \fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[3] ; wire \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[4]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[4]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[1]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[2]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[3]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[4]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|xGTOne_uid157_fpPowrTest_q_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:xGTOne_uid157_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|infCase1_uid194_fpPowrTest_q_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:infCase1_uid194_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|excRInf_uid196_fpPowrTest_q[0] ; wire \fp_pow_0002:fp_pow_inst|Add46~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[0]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist75_sticky_ena_q[0]~feeder ; wire \fp_pow_0002:fp_pow_inst|redist75_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|excROne_uid205_fpPowrTest_q_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:excROne_uid205_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0]~0 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3]~feeder ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|zeroCase2_uid174_fpPowrTest_q_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase2_uid174_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add66~50 ; wire \fp_pow_0002:fp_pow_inst|Add66~46 ; wire \fp_pow_0002:fp_pow_inst|Add66~42 ; wire \fp_pow_0002:fp_pow_inst|Add66~38 ; wire \fp_pow_0002:fp_pow_inst|Add66~34 ; wire \fp_pow_0002:fp_pow_inst|Add66~30 ; wire \fp_pow_0002:fp_pow_inst|Add66~26 ; wire \fp_pow_0002:fp_pow_inst|Add66~22 ; wire \fp_pow_0002:fp_pow_inst|Add66~18 ; wire \fp_pow_0002:fp_pow_inst|Add66~14 ; wire \fp_pow_0002:fp_pow_inst|Add66~10 ; wire \fp_pow_0002:fp_pow_inst|Add66~6 ; wire \fp_pow_0002:fp_pow_inst|Add66~1 ; wire \fp_pow_0002:fp_pow_inst|zeroCase5_uid167_fpPowrTest_q_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase5_uid167_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|zeroCase3_uid172_fpPowrTest_q_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase3_uid172_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[0][0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|zeroCase6_uid165_fpPowrTest_q_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase6_uid165_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|zeroCase4_uid170_fpPowrTest_q_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase4_uid170_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|excRZero_uid180_fpPowrTest_q[0]~0 ; wire \fp_pow_0002:fp_pow_inst|Mux343~0 ; wire \fp_pow_0002:fp_pow_inst|Add46~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[1]~feeder ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|Mux342~0 ; wire \fp_pow_0002:fp_pow_inst|Add46~9 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|Mux341~0 ; wire \fp_pow_0002:fp_pow_inst|Add46~13 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[3]~feeder ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|Mux340~0 ; wire \fp_pow_0002:fp_pow_inst|Add46~17 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|Mux339~0 ; wire \fp_pow_0002:fp_pow_inst|Add46~21 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|Mux338~0 ; wire \fp_pow_0002:fp_pow_inst|Add46~25 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|Mux337~0 ; wire \fp_pow_0002:fp_pow_inst|Add46~29 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|Mux336~0 ; wire \fp_pow_0002:fp_pow_inst|Add46~33 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[8]~feeder ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|Mux335~0 ; wire \fp_pow_0002:fp_pow_inst|Add46~37 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[9]~feeder ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|Mux334~0 ; wire \fp_pow_0002:fp_pow_inst|Add46~41 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|Mux333~0 ; wire \fp_pow_0002:fp_pow_inst|Add46~45 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|Mux332~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|Add46~49 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|Mux331~0 ; wire \fp_pow_0002:fp_pow_inst|Add46~53 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[13]~feeder ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|Mux330~0 ; wire \fp_pow_0002:fp_pow_inst|Add46~57 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|Mux329~0 ; wire \fp_pow_0002:fp_pow_inst|Add46~61 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|Mux328~0 ; wire \fp_pow_0002:fp_pow_inst|Add46~65 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|Mux327~0 ; wire \fp_pow_0002:fp_pow_inst|Add46~69 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|Mux326~0 ; wire \fp_pow_0002:fp_pow_inst|Add46~73 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[18]~feeder ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|Mux325~0 ; wire \fp_pow_0002:fp_pow_inst|Add46~77 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|Mux324~0 ; wire \fp_pow_0002:fp_pow_inst|Add46~81 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|Mux323~0 ; wire \fp_pow_0002:fp_pow_inst|Add46~85 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|Mux322~0 ; wire \fp_pow_0002:fp_pow_inst|Add46~89 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[22]~feeder ; wire \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|Mux321~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist76|delay_signals[0][0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~0 ; wire \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[0] ; wire \fp_pow_0002:fp_pow_inst|Mux320~0 ; wire \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~1 ; wire \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[1] ; wire \fp_pow_0002:fp_pow_inst|Mux319~0 ; wire \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist76|delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~2 ; wire \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[2] ; wire \fp_pow_0002:fp_pow_inst|Mux318~0 ; wire \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~3 ; wire \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[3] ; wire \fp_pow_0002:fp_pow_inst|Mux317~0 ; wire \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~4 ; wire \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[4] ; wire \fp_pow_0002:fp_pow_inst|Mux316~0 ; wire \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~5 ; wire \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[5] ; wire \fp_pow_0002:fp_pow_inst|Mux315~0 ; wire \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~6 ; wire \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[6] ; wire \fp_pow_0002:fp_pow_inst|Mux314~0 ; wire \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~7 ; wire \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[7] ; wire \fp_pow_0002:fp_pow_inst|Mux313~0 ; wire [0:0] \fp_pow_0002:fp_pow_inst|zeroCase2_uid174_fpPowrTest_q_i ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist134_sticky_ena_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg ; wire [22:0] \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|infCase4_uid187_fpPowrTest_q_i ; wire [0:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg ; wire [19:0] \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b ; wire [10:0] \fp_pow_0002:fp_pow_inst|xInZO_uid159_fpPowrTest_o ; wire [0:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|dataout_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg ; wire [1:0] \fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|dataout_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg ; wire [53:0] \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o ; wire [4:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|dataout_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg ; wire [32:0] \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o ; wire [0:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg ; wire [19:0] \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b ; wire [0:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|zeroCase5_uid167_fpPowrTest_q_i ; wire [25:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg ; wire [22:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|dataout_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|dataout_reg ; wire [1:0] \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|q_b ; wire [0:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|dataout_reg ; wire [10:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg ; wire [7:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|excRInf_uid196_fpPowrTest_q ; wire [33:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg ; wire [7:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg ; wire [4:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg ; wire [14:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|xInZOZPos_uid161_fpPowrTest_q_i ; wire [9:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg ; wire [25:0] \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q ; wire [23:0] \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist130_sticky_ena_q ; wire [32:0] \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b ; wire [32:0] \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q ; wire [31:0] \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist127_sticky_ena_q ; wire [48:0] \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q ; wire [14:0] \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b ; wire [39:0] \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b ; wire [22:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg ; wire [42:0] \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q ; wire [19:0] \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist118_sticky_ena_q ; wire [13:0] \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q ; wire [66:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg ; wire [45:0] \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o ; wire [19:0] \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b ; wire [7:0] \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist131_sticky_ena_q ; wire [9:0] \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b ; wire [19:0] \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b ; wire [0:0] \fp_pow_0002:fp_pow_inst|zeroCase6_uid165_fpPowrTest_q_i ; wire [13:0] \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b ; wire [4:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|zeroCase1_uid177_fpPowrTest_q_i ; wire [1:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|zeroCase0_uid179_fpPowrTest_q_i ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist77_sticky_ena_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|infCase5_uid184_fpPowrTest_q_i ; wire [0:0] \fp_pow_0002:fp_pow_inst|infCase3_uid191_fpPowrTest_q_i ; wire [0:0] \fp_pow_0002:fp_pow_inst|infCase2_uid192_fpPowrTest_q_i ; wire [0:0] \fp_pow_0002:fp_pow_inst|infCase1_uid194_fpPowrTest_q_i ; wire [0:0] \fp_pow_0002:fp_pow_inst|infCase0_uid195_fpPowrTest_q_i ; wire [0:0] \fp_pow_0002:fp_pow_inst|zeroCase4_uid170_fpPowrTest_q_i ; wire [0:0] \fp_pow_0002:fp_pow_inst|zeroCase3_uid172_fpPowrTest_q_i ; wire [13:0] \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o ; wire [4:0] \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist77_cmpReg_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist78_sticky_ena_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist97_sticky_ena_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist122_sticky_ena_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist123_sticky_ena_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist79_sticky_ena_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist81_sticky_ena_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist82_sticky_ena_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist118_replace_mem_ia ; wire [4:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg ; wire [4:0] \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist78_cmpReg_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist117_sticky_ena_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|exc_R_uid35_fpPowrTest_q ; wire [4:0] \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i ; wire [3:0] \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i ; wire [4:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg ; wire [13:0] \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o ; wire [4:0] \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q ; wire [4:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist75_cmpReg_q ; wire [4:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg ; wire [4:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q ; wire [4:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg ; wire [4:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg ; wire [12:0] \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist75_sticky_ena_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|excROne_uid205_fpPowrTest_q_i ; wire [4:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg ; wire [4:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg ; wire [4:0] \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i ; wire [4:0] \fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q ; wire [4:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist117_cmpReg_q ; wire [4:0] \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i ; wire [0:0] \fp_pow_0002:fp_pow_inst|exc_I_uid30_fpPowrTest_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|xGTOne_uid157_fpPowrTest_q_i ; wire [0:0] \fp_pow_0002:fp_pow_inst|exc_R_uid51_fpPowrTest_q_i ; wire [4:0] \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist83_sticky_ena_q ; wire [33:0] \fp_pow_0002:fp_pow_inst|expFracXGTExpFracOne_uid155_fpPowrTest_o ; wire [4:0] \fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q ; wire [4:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist83_cmpReg_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q ; wire [4:0] \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i ; wire [3:0] \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q ; wire [3:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist96_cmpReg_q ; wire [43:0] \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q ; wire [3:0] \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i ; wire [11:0] \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o ; wire [46:0] \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q ; wire [4:0] \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q ; wire [4:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist131_cmpReg_q ; wire [43:0] \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i ; wire [4:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist88_cmpReg_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q ; wire [4:0] \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q ; wire [3:0] \fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q ; wire [3:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist134_cmpReg_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q ; wire [10:0] \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o ; wire [1:0] \fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist9_cmpReg_q ; wire [3:0] \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i ; wire [1:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist102_cmpReg_q ; wire [1:0] \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i ; wire [9:0] \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o ; wire [53:0] \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o ; wire [0:0] \fp_pow_0002:fp_pow_inst|signProd_uid106_fpPowrTest_q_i ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q ; wire [3:0] \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q ; wire [3:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist137_cmpReg_q ; wire [20:0] \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o ; wire [66:0] \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q ; wire [5:0] \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1 ; wire [24:0] \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o ; wire [16:0] \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o ; wire [1:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg ; wire [2:0] \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_a0 ; wire [2:0] \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_b0 ; wire [65:0] \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i ; wire [10:0] \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o ; wire [53:0] \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o ; wire [47:0] \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|signRLog0_uid82_fpPowrTest_q_i ; wire [0:0] \fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q ; wire [0:0] \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg ; wire [22:0] \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[14] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[15] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[31] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[15] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[32] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[28] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[30] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[22] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[26] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[18] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[31] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[23] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[27] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[19] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[29] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[21] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[25] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[16] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[8] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[10] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[11] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[12] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[13] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[14] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[15] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[16] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[18] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[19] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[20] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[22] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[24] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[27] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[28] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[30] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[32] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][49] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][48] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][46] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][45] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][43] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][42] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][40] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][38] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][34] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][33] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][31] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][30] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][29] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][28] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][27] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][26] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][24] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[32] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[24] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[28] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[20] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[30] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[22] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[26] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[18] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[31] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[23] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[27] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[19] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[29] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[21] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[25] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[17] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add37~1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|__ALT_INV__dataout_reg[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add66~1 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add61~1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|__ALT_INV__dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|__ALT_INV__dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|__ALT_INV__dataout_reg[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][25] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][22] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][19] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][17] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][15] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][14] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|__ALT_INV__dataout_reg[7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|__ALT_INV__dataout_reg[6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|__ALT_INV__dataout_reg[5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|__ALT_INV__dataout_reg[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][36] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][35] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][34] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][32] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][31] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][29] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][21] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][19] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][34] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][33] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][32] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][31] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][29] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][28] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][27] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|__ALT_INV__dataout_reg[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|__ALT_INV__dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|__ALT_INV__dataout_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|__ALT_INV__dataout_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|__ALT_INV__dataout_reg[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][16] ; wire \__ALT_INV__rtl~74 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux208~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~10 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~9 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[15][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][17] ; wire \__ALT_INV__rtl~71 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux207~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][47] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][46] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][51] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][50] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[53] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][45] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][44] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][49] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][48] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[25] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[29] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[14][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][37] ; wire \__ALT_INV__rtl~285 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[40] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][18] ; wire \__ALT_INV__rtl~66 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux206~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist4|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist4|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[26] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[13][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[13][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|__ALT_INV__delay_signals[13][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][38] ; wire \__ALT_INV__rtl~284 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[41] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][19] ; wire \__ALT_INV__rtl~61 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux205~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[48] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[47] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[43] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[45] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[42] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[27] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram6~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist9_replace_rdcnt_eq ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|__ALT_INV__delay_signals[11][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[12][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][35] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][33] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][32] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][31] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][30] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][29] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][25] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][22] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][21] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][19] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][16] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][14] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][23] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][22] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][21] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][19] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][18] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][17] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][16] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][15] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][14] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][12] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][35] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][34] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][33] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][32] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][31] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][30] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][28] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][27] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][26] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][25] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][23] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][18] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][15] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][13] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~33 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~29 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~25 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~97 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~93 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~77 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~73 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~69 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~65 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~61 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~57 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~53 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~49 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~45 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~41 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~37 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~33 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~29 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~21 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~17 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~13 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~9 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~5 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[36] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[37] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[38] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[39] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[41] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[42] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[43] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[44] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[34] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[35] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[40] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[29] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[30] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[31] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[32] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[33] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[23] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[25] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[26] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[27] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[22] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[28] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[16] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[17] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[18] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[19] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[21] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[12] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[13] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[14] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[15] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|__ALT_INV__op_1~9 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[14] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[13] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[11] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[3] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|__ALT_INV__op_1~5 ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|__ALT_INV__op_1~1 ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|__ALT_INV__dataout_reg[20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[17] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][35] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][33] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][32] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][31] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][28] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][27] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][25] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][22] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][21] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][18] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[10] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[19] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[11] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[8] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[12] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[25] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[21] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[10] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[22] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[14] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[16] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[19] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[21] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[22] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[25] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[26] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[28] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[30] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[33] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[34] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[35] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[36] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[38] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[39] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][34] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][33] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][28] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][17] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][16] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][15] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][13] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][12] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im10_cma_s[0][17] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im10_cma_s[0][15] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im10_cma_s[0][14] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im10_cma_s[0][10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im10_cma_s[0][6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im10_cma_s[0][5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im10_cma_s[0][1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[12] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[12] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[13] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[8] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[10] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[11] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[12] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[13] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[14] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[15] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[16] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[17] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[18] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[19] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[20] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[21] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[22] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[23] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][29] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][28] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][27] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][26] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][25] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][23] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][22] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][21] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][19] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][18] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][17] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][16] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[1][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[1][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[1][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[1][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[1][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[1][11] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[13] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[14] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[1] ; wire \__ALT_INV__rtl~4 ; wire \__ALT_INV__rtl~276 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux168~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][36] ; wire \__ALT_INV__rtl~275 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][32] ; wire \__ALT_INV__rtl~9 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|__ALT_INV__delay_signals[0][1] ; wire \__ALT_INV__rtl~274 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux168~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][37] ; wire \__ALT_INV__rtl~273 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux154~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_eq ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal23~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[5][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|__ALT_INV__delay_signals[5][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal26~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[1][4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[43] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][45] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_cmpReg_q[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[4][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_cmpReg_q[0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|__ALT_INV__delay_signals[5][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|__ALT_INV__delay_signals[3][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_eq ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|__ALT_INV__delay_signals[3][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__addrExp_uid142_fpPowrTest_b[3]~3 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__addrExp_uid142_fpPowrTest_b[0]~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist93|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_eq ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_eq ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|__ALT_INV__delay_signals[3][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_eq ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add54~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_cmpReg_q[0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist85|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[12] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__excRNaN_uid204_fpPowrTest_q_i[0]~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist121|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124_outputreg|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__excRNaN_uid204_fpPowrTest_q_i[0]~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__exc_R_uid35_fpPowrTest_q[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist118_replace_mem_ia[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist119|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[12] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist76|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__zeroCase6_uid165_fpPowrTest_q_i[0]~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist117_outputreg|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist130_outputreg|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist82_outputreg|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase2_uid174_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase3_uid172_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase4_uid170_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase5_uid167_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase6_uid165_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:infCase0_uid195_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:infCase1_uid194_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:infCase2_uid192_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:infCase3_uid191_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:infCase4_uid187_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:infCase5_uid184_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|__ALT_INV__q_b[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|__ALT_INV__q_b[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[8] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[10] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[11] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[12] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[13] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[14] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[15] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[16] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[17] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[18] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[19] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][27] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][26] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][25] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][23] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][22] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][21] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][19] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][18] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][17] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][16] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][15] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][14] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[11] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[12] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[13] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[15] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[16] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[17] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[18] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[3] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[4] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[5] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[8] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][37] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][32] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][31] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][29] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][28] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][27] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][26] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][22] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][21] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][19] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][17] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][16] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[7] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[8] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[9] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[10] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[13] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[14] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[17] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[19] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add3~117 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][35] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][34] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][33] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][32] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][30] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][23] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][22] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][34] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][33] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][31] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][30] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][29] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][28] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][26] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][22] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][16] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][14] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][12] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][2] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|__ALT_INV__q_b[6] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|__ALT_INV__q_b[8] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|__ALT_INV__q_b[13] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|__ALT_INV__q_b[14] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|__ALT_INV__q_b[16] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|__ALT_INV__q_b[18] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|__ALT_INV__q_b[19] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[0] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[1] ; wire \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[4] ; wire \__ALT_INV__areset~CLKENA0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~36 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[1][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[1][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[1][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[1][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[1][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[1][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[2][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[2][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[1][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[1][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist44|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[2][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[2][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[2][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[2][1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[1][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[1][2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[1][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal0~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[23] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[22] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[21] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[19] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|__ALT_INV__delay_signals[34][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[17] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[16] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[15] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[14] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[13] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[12] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|__ALT_INV__delay_signals[30][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist116|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[1][1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][56] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][55] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][49] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][50] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][51] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[41] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[53] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][52] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[44] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][44] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[45] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][45] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][46] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][47] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[40] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][48] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[42] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[43] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[46] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|__ALT_INV__delay_signals[14][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram4~9 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram4~8 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram4~7 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[50] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[45] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[46] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[49] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[42] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][44] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|__ALT_INV__delay_signals[27][0] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[1][0] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[0][1] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[1][1] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[0][2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_b0[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[12] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[12] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][50] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][51] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][44] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][45] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][46] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][47] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][48] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[1][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[1][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[1][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[1][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[1][3] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[2][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_a0[0] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[1][2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_b0[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[13] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[13] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|__ALT_INV__delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_s1[0] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[2][1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_a0[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[14] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[14] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist107|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][49] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][50] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][51] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][44] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][45] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][46] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][47] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][48] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[2][2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_b0[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_a0[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[27] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[26] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[28] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[25] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[15] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[15] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[1][4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[53] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_s1[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[16] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[16] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|__ALT_INV__delay_signals[1][3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[27] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[28] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[30] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[14] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[15] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[16] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[18] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[51] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[44] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[39] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[40] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[42] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[31] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_s1[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux57~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux58~0 ; wire \__ALT_INV__rtl~315 ; wire \__ALT_INV__rtl~314 ; wire \__ALT_INV__rtl~313 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux60~0 ; wire \__ALT_INV__rtl~312 ; wire \__ALT_INV__rtl~311 ; wire \__ALT_INV__rtl~310 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~3 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~2 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux59~0 ; wire \__ALT_INV__rtl~309 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux21~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux22~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux23~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux24~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux56~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux40~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux48~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux52~0 ; wire \__ALT_INV__rtl~308 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux54~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux38~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux46~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux50~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux42~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux26~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux55~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux39~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux47~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux51~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux53~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux37~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux45~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux49~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux41~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux25~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[17] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[17] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[21] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[21] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram5~9 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram5~8 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram5~7 ; wire \__ALT_INV__rtl~307 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~12 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~11 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~10 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~9 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~8 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~6 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~5 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~4 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[12] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[13] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[14] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~3 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][49] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][50] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][51] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~2 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][44] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][45] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][46] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][47] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal22~6 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal22~5 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal22~4 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal22~3 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal22~2 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal22~1 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal22~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[43] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[42] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[41] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[40] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[39] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[38] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[37] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[36] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[35] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[34] ; wire \__ALT_INV__rtl~217 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[25] ; wire \__ALT_INV__rtl~216 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[26] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[30] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[28] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[32] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[27] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[31] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[33] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[56] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[55] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[54] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[53] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[52] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[44] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[48] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[46] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[50] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[45] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[49] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[47] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[51] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|__ALT_INV__delay_signals[7][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[18] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[18] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[22] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[22] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[57] ; wire \__ALT_INV__rtl~305 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][59] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux33~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][27] ; wire \__ALT_INV__rtl~304 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][51] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][19] ; wire \__ALT_INV__rtl~302 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][63] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux29~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][47] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][31] ; wire \__ALT_INV__rtl~301 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][55] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][23] ; wire \__ALT_INV__rtl~299 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][61] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux31~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][45] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][29] ; wire \__ALT_INV__rtl~298 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][53] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux35~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux19~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][57] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux27~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][49] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][17] ; wire \__ALT_INV__rtl~297 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][65] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][33] ; wire \__ALT_INV__rtl~295 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][58] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux34~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][26] ; wire \__ALT_INV__rtl~294 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][50] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][18] ; wire \__ALT_INV__rtl~292 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][62] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux30~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][46] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][30] ; wire \__ALT_INV__rtl~291 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][54] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][22] ; wire \__ALT_INV__rtl~289 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][60] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux32~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][44] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~1 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~0 ; wire \__ALT_INV__rtl~288 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][28] ; wire \__ALT_INV__rtl~287 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][52] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux36~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux20~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][56] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux28~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][48] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][16] ; wire \__ALT_INV__rtl~286 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][64] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|__ALT_INV__delay_signals[1][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][27] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal10~6 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal10~5 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal10~4 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal10~3 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal10~2 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal10~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal10~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[2][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[2][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|__ALT_INV__delay_signals[20][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_s1[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[19] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[19] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[23] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][22] ; wire \__ALT_INV__rtl~146 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[59] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[63] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[61] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[65] ; wire \__ALT_INV__rtl~147 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[58] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[62] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[64] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|__ALT_INV__delay_signals[1][6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_eq ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal11~2 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[14]~14 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[12]~13 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[5]~12 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal11~1 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal11~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[9]~11 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[10]~10 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[6]~9 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[7]~8 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[2]~7 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[3]~6 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[4]~5 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[8]~4 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[13]~3 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[15]~2 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[11]~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[1]~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|__ALT_INV__delay_signals[19][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|__ALT_INV__delay_signals[20][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~18 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__xInZO_uid159_fpPowrTest_o[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal12~3 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal12~2 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal12~1 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal12~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid300_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|__ALT_INV__delay_signals[19][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal6~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal5~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|__ALT_INV__delay_signals[18][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~15 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[21] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[25] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_cmpReg_q[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal14~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal13~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][7] ; wire \__ALT_INV__rtl~135 ; wire \__ALT_INV__rtl~133 ; wire \__ALT_INV__rtl~131 ; wire \__ALT_INV__rtl~129 ; wire \__ALT_INV__rtl~127 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][0] ; wire \__ALT_INV__rtl~125 ; wire \__ALT_INV__rtl~124 ; wire \__ALT_INV__rtl~121 ; wire \__ALT_INV__rtl~118 ; wire \__ALT_INV__rtl~117 ; wire \__ALT_INV__rtl~114 ; wire \__ALT_INV__rtl~111 ; wire \__ALT_INV__rtl~110 ; wire \__ALT_INV__rtl~107 ; wire \__ALT_INV__rtl~104 ; wire \__ALT_INV__rtl~103 ; wire \__ALT_INV__rtl~100 ; wire \__ALT_INV__rtl~97 ; wire \__ALT_INV__rtl~89 ; wire \__ALT_INV__rtl~87 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux212~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][12] ; wire \__ALT_INV__rtl~86 ; wire \__ALT_INV__rtl~85 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][10] ; wire \__ALT_INV__rtl~84 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux213~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][11] ; wire \__ALT_INV__rtl~83 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux211~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][13] ; wire \__ALT_INV__rtl~82 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][9] ; wire \__ALT_INV__rtl~80 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux210~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|__ALT_INV__delay_signals[3][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~13 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~12 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[22] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[26] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[17][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[17][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|__ALT_INV__delay_signals[17][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][15] ; wire \__ALT_INV__rtl~77 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux209~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[23] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Add20~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[16][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|__ALT_INV__delay_signals[15][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[1][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[1][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[1][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux228~1 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[42] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][20] ; wire \__ALT_INV__rtl~58 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux204~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][47] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][46] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][51] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][50] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][45] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][44] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][49] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][48] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[3][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[37] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[39] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[28] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[38] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[40] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[36] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[41] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_replace_rdcnt_eq ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist9_replace_rdcnt_i[1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist9_replace_rdcnt_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|__ALT_INV__delay_signals[10][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[11][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[1][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[1][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[1][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[1][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[1][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[1][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[1][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux226~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux225~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux227~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[43] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][21] ; wire \__ALT_INV__rtl~55 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux203~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist102_cmpReg_q[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[29] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_replace_rdcnt_i[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_replace_rdcnt_i[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[10][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[10][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_eq ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[2][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[2][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[40] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[44] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][22] ; wire \__ALT_INV__rtl~50 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux202~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist102_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[30] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_cmpReg_q[0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[9][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[9][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|__ALT_INV__delay_signals[8][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][15] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][14] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][13] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][20] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][16] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[1][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[1][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[1][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[1][2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux172~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[41] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux228~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[45] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][23] ; wire \__ALT_INV__rtl~45 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux201~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[31] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[3] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[2] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[4] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_sticky_ena_q[0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[8][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][21] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][17] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[42] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[46] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[23] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][24] ; wire \__ALT_INV__rtl~43 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux200~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][27] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[28] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][28] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[34] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[38] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[40] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[32] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[36] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[35] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[39] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[41] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[33] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[37] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[42] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[7][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][22] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][11] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][9] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][18] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|__ALT_INV__delay_signals[0][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[36] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[35] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[34] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[33] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[32] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[31] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][44] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[47] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[24] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][25] ; wire \__ALT_INV__rtl~41 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux199~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][25] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[29] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][29] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux162~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux163~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux164~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux166~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux167~1 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux178~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux165~0 ; wire \__ALT_INV__rtl~281 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux167~0 ; wire \__ALT_INV__rtl~280 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux168~2 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_eq ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|__ALT_INV__delay_signals[5][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][8] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|__ALT_INV__delay_signals[6][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[6][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][12] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][10] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][19] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[2][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[2][2] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[2][1] ; wire \__ALT_INV__rtl~279 ; wire \__ALT_INV__rtl~278 ; wire \__ALT_INV__rtl~277 ; wire \__ALT_INV__rtl~23 ; wire \__ALT_INV__rtl~21 ; wire \__ALT_INV__rtl~19 ; wire \__ALT_INV__rtl~17 ; wire \__ALT_INV__rtl~15 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux182~0 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[25] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ; wire \__ALT_INV__rtl~13 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux183~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][41] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux191~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][33] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux187~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][37] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux195~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][29] ; wire \__ALT_INV__rtl~12 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux185~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][39] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux193~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][31] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux189~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][35] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux197~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][27] ; wire \__ALT_INV__rtl~11 ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux184~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][40] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux192~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][32] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux188~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][36] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux196~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][28] ; wire \__ALT_INV__rtl~10 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux186~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][38] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux194~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][30] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux190~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][34] ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux198~0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][26] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][42] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2] ; wire \__ALT_INV__a[14]~input0 ; wire \__ALT_INV__a[0]~input0 ; wire \__ALT_INV__a[12]~input0 ; wire \__ALT_INV__a[13]~input0 ; wire \__ALT_INV__a[8]~input0 ; wire \__ALT_INV__a[9]~input0 ; wire \__ALT_INV__a[10]~input0 ; wire \__ALT_INV__a[6]~input0 ; wire \__ALT_INV__a[7]~input0 ; wire \__ALT_INV__a[1]~input0 ; wire \__ALT_INV__a[2]~input0 ; wire \__ALT_INV__a[3]~input0 ; wire \__ALT_INV__a[4]~input0 ; wire \__ALT_INV__a[5]~input0 ; wire \__ALT_INV__a[18]~input0 ; wire \__ALT_INV__a[21]~input0 ; wire \__ALT_INV__a[22]~input0 ; wire \__ALT_INV__a[23]~input0 ; wire \__ALT_INV__a[24]~input0 ; wire \__ALT_INV__a[25]~input0 ; wire \__ALT_INV__a[26]~input0 ; wire \__ALT_INV__a[27]~input0 ; wire \__ALT_INV__a[28]~input0 ; wire \__ALT_INV__a[29]~input0 ; wire \__ALT_INV__a[30]~input0 ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][4]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][49]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][42]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][4]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][17]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[5]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[14]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][45]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][48]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][38]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][40]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][41]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][7]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][17]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][18]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][16]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][24]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][25]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][9]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][16]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[3]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][10]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][9]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][3]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|__ALT_INV__delay_signals[0][3]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][14]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_replace_rdcnt_eq~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist9_replace_rdcnt_i[0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_replace_rdcnt_i[3]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[4]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][35]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][33]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[4]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[3]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_eq~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[3]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[3]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[1]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[0][0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|__ALT_INV__delay_signals[0][0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[2]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist76|__ALT_INV__delay_signals[0][0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|__ALT_INV__delay_signals[0][0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][13]~DUPLICATE ; wire \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[9]~DUPLICATE ; wire gnd; wire vcc; assign gnd = 1'b0; assign vcc = 1'b1; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[0] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[0] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[6] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[6] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[14] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[14] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[15] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[15] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[31] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[31] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[7] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][42] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][42] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[15] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[15] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[16] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][36] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][36] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[8] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[32] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[32] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[24] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[28] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[28] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[20] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[30] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[30] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[22] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[22] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[26] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[26] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[18] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[18] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[31] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[31] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[23] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[23] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[27] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[27] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[19] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[19] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[29] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[29] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[21] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[21] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[25] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[25] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[16] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[16] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[17] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[1] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[1] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[2] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[2] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[3] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[3] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[4] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[4] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[5] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[5] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[7] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[7] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[8] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[8] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[9] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[9] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[10] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[10] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[11] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[11] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[12] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[12] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[13] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[13] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[14] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[14] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[15] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[15] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[16] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[16] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[18] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[18] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[19] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[19] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[20] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[20] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[22] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[22] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[24] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[24] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[27] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[27] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[28] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[28] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[30] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[30] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[32] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[32] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][49] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][49] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][48] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][48] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][46] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][46] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][45] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][45] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][43] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][43] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][42] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][42] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][40] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][40] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][38] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][38] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][34] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][34] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][33] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][33] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][31] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][31] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][30] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][30] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][29] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][29] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][28] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][28] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][27] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][27] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][26] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][26] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][24] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][24] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[32] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[32] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[24] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[24] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[28] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[28] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[20] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[20] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[30] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[30] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[22] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[22] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[26] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[26] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[18] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[18] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[31] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[31] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[23] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[23] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[27] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[27] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[19] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[19] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[29] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[29] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[21] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[21] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[25] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[25] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[17] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[17] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[33] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[9] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add37~1 = ~ \fp_pow_0002:fp_pow_inst|Add37~1 ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|__ALT_INV__dataout_reg[8] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|dataout_reg[0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add66~1 = ~ \fp_pow_0002:fp_pow_inst|Add66~1 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add61~1 = ~ \fp_pow_0002:fp_pow_inst|Add61~1 ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|dataout_reg[0] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|__ALT_INV__dataout_reg[0] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|dataout_reg[0] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|__ALT_INV__dataout_reg[0] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|dataout_reg[0] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|__ALT_INV__dataout_reg[1] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][25] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][25] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][22] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][22] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][20] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][19] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][19] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][17] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][17] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][15] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][15] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][14] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][14] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][11] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][10] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][7] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][5] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][3] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][2] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][1] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][1] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|__ALT_INV__dataout_reg[7] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[7] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|__ALT_INV__dataout_reg[6] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[6] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|__ALT_INV__dataout_reg[5] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[5] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|__ALT_INV__dataout_reg[4] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][36] = ~ \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][36] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][35] = ~ \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][35] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][34] = ~ \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][34] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][32] = ~ \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][32] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][31] = ~ \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][31] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][29] = ~ \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][29] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][24] = ~ \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][21] = ~ \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][21] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][20] = ~ \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][19] = ~ \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][19] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][34] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][34] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][33] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][33] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][32] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][32] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][31] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][31] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][29] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][29] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][28] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][28] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][27] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][27] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|__ALT_INV__dataout_reg[3] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|__ALT_INV__dataout_reg[0] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[0] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|__ALT_INV__dataout_reg[1] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[1] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|__ALT_INV__dataout_reg[2] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[2] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|__ALT_INV__dataout_reg[9] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][16] ; assign \__ALT_INV__rtl~74 = ~ \rtl~74 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux208~0 = ~ \fp_pow_0002:fp_pow_inst|Mux208~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][36] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][36] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[38] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[38] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][39] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][39] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~10 = ~ \fp_pow_0002:fp_pow_inst|Ram7~10 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~9 = ~ \fp_pow_0002:fp_pow_inst|Ram7~9 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[24] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[26] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[28] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[7] = ~ \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][41] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][41] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[15][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[15][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[35] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[35] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][36] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][36] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[39] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[39] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][39] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][39] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[16] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][17] ; assign \__ALT_INV__rtl~71 = ~ \rtl~71 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux207~0 = ~ \fp_pow_0002:fp_pow_inst|Mux207~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][47] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][47] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][46] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][46] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][51] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][51] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][50] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][50] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][43] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][43] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][42] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][42] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[53] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[53] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][45] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][45] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][44] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][44] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][49] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][49] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][48] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][48] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][37] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][37] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[39] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[39] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][41] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][41] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][40] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][40] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[21] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[25] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[25] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[27] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[29] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[29] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[28] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[8] = ~ \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[14][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[14][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[36] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[36] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][37] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][37] ; assign \__ALT_INV__rtl~285 = ~ \rtl~285 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[40] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[40] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][40] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][40] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[17] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][18] ; assign \__ALT_INV__rtl~66 = ~ \rtl~66 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux206~0 = ~ \fp_pow_0002:fp_pow_inst|Mux206~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist4|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist4|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][38] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][38] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist4|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist4|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[26] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[26] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[28] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[30] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[29] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[9] = ~ \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[13][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[13][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[13][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[13][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|__ALT_INV__delay_signals[13][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[13][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[37] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[37] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][38] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][38] ; assign \__ALT_INV__rtl~284 = ~ \rtl~284 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[41] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[41] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][41] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][41] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[18] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][19] ; assign \__ALT_INV__rtl~61 = ~ \rtl~61 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux205~0 = ~ \fp_pow_0002:fp_pow_inst|Mux205~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[48] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[48] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[47] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[47] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[43] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[43] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[45] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[45] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][39] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][39] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[42] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[42] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[23] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[27] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[27] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[29] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[30] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram6~5 = ~ \fp_pow_0002:fp_pow_inst|Ram6~5 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[10] = ~ \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[4] = ~ \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist9_replace_rdcnt_eq = ~ \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_eq ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|__ALT_INV__delay_signals[11][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[11][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[12][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[12][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][35] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][35] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][33] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][33] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][32] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][32] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][31] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][31] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][30] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][30] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][29] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][29] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][25] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][25] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][24] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][22] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][22] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][21] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][21] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][19] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][19] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][16] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][16] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][14] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][14] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][11] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][10] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][8] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][6] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][5] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][4] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][3] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][2] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][1] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][0] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][23] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][23] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][22] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][22] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][21] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][21] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][20] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][19] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][19] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][18] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][18] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][17] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][17] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][16] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][16] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][15] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][15] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][14] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][14] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][12] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][12] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][11] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][10] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][9] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][7] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][6] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][5] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][4] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][3] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][0] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][35] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][35] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][34] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][34] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][33] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][33] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][32] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][32] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][31] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][31] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][30] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][30] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][28] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][28] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][27] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][27] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][26] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][26] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][25] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][25] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][24] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][23] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][23] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][20] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][18] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][18] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][15] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][15] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][13] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][13] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][10] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][7] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][5] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~33 = ~ \fp_pow_0002:fp_pow_inst|Add13~33 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~29 = ~ \fp_pow_0002:fp_pow_inst|Add13~29 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~25 = ~ \fp_pow_0002:fp_pow_inst|Add13~25 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 = ~ \fp_pow_0002:fp_pow_inst|Add13~21 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 = ~ \fp_pow_0002:fp_pow_inst|Add13~17 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 = ~ \fp_pow_0002:fp_pow_inst|Add13~13 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 = ~ \fp_pow_0002:fp_pow_inst|Add13~9 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 = ~ \fp_pow_0002:fp_pow_inst|Add13~5 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 = ~ \fp_pow_0002:fp_pow_inst|Add13~1 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][43] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][43] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] = ~ \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~97 = ~ \fp_pow_0002:fp_pow_inst|Add15~97 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~93 = ~ \fp_pow_0002:fp_pow_inst|Add15~93 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~77 = ~ \fp_pow_0002:fp_pow_inst|Add15~77 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~73 = ~ \fp_pow_0002:fp_pow_inst|Add15~73 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~69 = ~ \fp_pow_0002:fp_pow_inst|Add15~69 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~65 = ~ \fp_pow_0002:fp_pow_inst|Add15~65 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~61 = ~ \fp_pow_0002:fp_pow_inst|Add15~61 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~57 = ~ \fp_pow_0002:fp_pow_inst|Add15~57 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~53 = ~ \fp_pow_0002:fp_pow_inst|Add15~53 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~49 = ~ \fp_pow_0002:fp_pow_inst|Add15~49 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~45 = ~ \fp_pow_0002:fp_pow_inst|Add15~45 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~41 = ~ \fp_pow_0002:fp_pow_inst|Add15~41 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~37 = ~ \fp_pow_0002:fp_pow_inst|Add15~37 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~33 = ~ \fp_pow_0002:fp_pow_inst|Add15~33 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~29 = ~ \fp_pow_0002:fp_pow_inst|Add15~29 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~21 = ~ \fp_pow_0002:fp_pow_inst|Add15~21 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~17 = ~ \fp_pow_0002:fp_pow_inst|Add15~17 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~13 = ~ \fp_pow_0002:fp_pow_inst|Add15~13 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~9 = ~ \fp_pow_0002:fp_pow_inst|Add15~9 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~5 = ~ \fp_pow_0002:fp_pow_inst|Add15~5 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[1] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[2] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[3] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[5] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[6] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[7] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[8] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[9] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[4] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[36] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[36] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[37] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[37] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[38] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[38] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[39] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[39] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[41] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[41] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[42] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[42] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[43] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[43] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[44] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[44] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[34] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[34] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[35] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[35] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[40] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[40] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[29] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[29] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[30] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[30] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[31] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[31] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[32] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[32] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[33] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[33] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[23] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[23] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[24] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[25] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[25] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[26] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[26] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[27] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[27] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[22] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[22] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[28] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[28] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[16] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[16] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[17] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[17] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[18] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[18] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[19] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[19] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[20] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[21] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[21] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[10] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[11] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[12] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[12] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[13] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[13] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[14] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[14] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[15] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[15] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ; assign \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|__ALT_INV__op_1~9 = ~ \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~9 ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[14] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[14] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[0] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[0] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[13] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[13] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[9] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[9] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[11] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[11] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[6] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[6] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[7] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[7] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[1] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[1] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[3] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[3] ; assign \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|__ALT_INV__op_1~5 = ~ \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~5 ; assign \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|__ALT_INV__op_1~1 = ~ \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~1 ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|__ALT_INV__dataout_reg[20] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[3] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[1] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[2] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[4] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[0] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[5] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] = ~ \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[17] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[17] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[3] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[3] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[1] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[1] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[2] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[2] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[4] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[4] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[0] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[0] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[5] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[6] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][35] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][35] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][33] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][33] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][32] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][32] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][31] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][31] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][28] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][28] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][27] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][27] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][25] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][25] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][24] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][22] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][22] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][21] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][21] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][18] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][18] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[6] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[7] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[10] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[10] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[9] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[9] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[6] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[6] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[5] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[5] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[4] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[4] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[2] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[2] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[1] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[1] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[0] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[22] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[19] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[19] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[11] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[11] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[7] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[8] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[8] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[20] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[12] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[12] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[8] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[25] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[25] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[21] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[21] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[9] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[10] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[10] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[22] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[22] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[14] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[14] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[16] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[16] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[19] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[19] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[21] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[21] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[22] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[22] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[25] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[25] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[26] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[26] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[28] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[28] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[30] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[30] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[33] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[33] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[34] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[34] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[35] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[35] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[36] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[36] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[38] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[38] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[39] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[39] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[10] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[11] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][34] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][34] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][33] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][33] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][28] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][28] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][17] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][17] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][16] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][16] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][15] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][15] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][13] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][13] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][12] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][12] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][11] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][10] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][9] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][8] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][7] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][6] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][5] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im10_cma_s[0][17] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][17] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im10_cma_s[0][15] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][15] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im10_cma_s[0][14] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][14] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im10_cma_s[0][10] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im10_cma_s[0][6] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im10_cma_s[0][5] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im10_cma_s[0][1] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][1] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[11] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[12] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[12] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[4] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[4] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[12] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[12] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[13] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[13] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[1] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[1] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[3] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[3] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[2] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[2] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[5] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[5] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[1] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[1] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[2] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[2] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[3] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[3] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[4] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[4] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[5] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[5] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[6] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[6] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[7] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[7] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[8] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[8] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[9] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[9] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[10] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[10] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[11] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[11] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[12] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[12] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[13] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[13] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[14] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[14] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[15] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[15] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[16] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[16] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[17] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[17] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[18] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[18] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[19] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[19] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[20] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[20] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[21] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[21] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[22] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[22] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[23] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[23] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[0] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][29] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][29] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][28] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][28] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][27] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][27] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][26] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][26] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][25] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][25] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][24] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][23] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][23] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][22] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][22] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][21] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][21] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][20] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][19] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][19] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][18] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][18] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][17] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][17] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][16] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][16] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][15] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[1][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[1][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[1][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[1][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[1][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[1][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][11] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[13] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[13] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[14] = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[14] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[22] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[3] = ~ \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[2] = ~ \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[1] = ~ \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[1] ; assign \__ALT_INV__rtl~4 = ~ \rtl~4 ; assign \__ALT_INV__rtl~276 = ~ \rtl~276 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux168~1 = ~ \fp_pow_0002:fp_pow_inst|Mux168~1 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][36] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][36] ; assign \__ALT_INV__rtl~275 = ~ \rtl~275 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][32] ; assign \__ALT_INV__rtl~9 = ~ \rtl~9 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[0][1] ; assign \__ALT_INV__rtl~274 = ~ \rtl~274 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux168~0 = ~ \fp_pow_0002:fp_pow_inst|Mux168~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][37] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][37] ; assign \__ALT_INV__rtl~273 = ~ \rtl~273 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux154~0 = ~ \fp_pow_0002:fp_pow_inst|Mux154~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][38] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][38] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_eq = ~ \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_eq ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[8] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal23~0 = ~ \fp_pow_0002:fp_pow_inst|Equal23~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[5][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[5][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|__ALT_INV__delay_signals[5][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[5][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal26~0 = ~ \fp_pow_0002:fp_pow_inst|Equal26~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[1][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[33] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[32] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[31] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[30] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[29] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[28] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[27] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[43] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[43] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][45] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][45] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[26] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_cmpReg_q[0] = ~ \fp_pow_0002:fp_pow_inst|redist96_cmpReg_q[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[4] = ~ \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[3] = ~ \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[2] = ~ \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[8] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[9] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[4][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[4][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_sticky_ena_q[0] = ~ \fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][38] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][38] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][40] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][40] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][39] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][39] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][38] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][38] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][37] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][37] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][36] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][36] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_cmpReg_q[0] = ~ \fp_pow_0002:fp_pow_inst|redist83_cmpReg_q[0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[9] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[10] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|__ALT_INV__delay_signals[5][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[5][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|__ALT_INV__delay_signals[3][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[3][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_eq = ~ \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_eq ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|__ALT_INV__delay_signals[3][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[3][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__addrExp_uid142_fpPowrTest_b[3]~3 = ~ \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__addrExp_uid142_fpPowrTest_b[0]~0 = ~ \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist93|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][39] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][39] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_sticky_ena_q[0] = ~ \fp_pow_0002:fp_pow_inst|redist83_sticky_ena_q[0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[10] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_eq = ~ \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_eq ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[4] = ~ \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[3] = ~ \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[2] = ~ \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[1] = ~ \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_eq = ~ \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_eq ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][37] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][37] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][36] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][36] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[11] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[11] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[4] = ~ \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[3] = ~ \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[2] = ~ \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[1] = ~ \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[0] = ~ \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|__ALT_INV__delay_signals[3][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[3][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_eq = ~ \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_eq ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add54~0 = ~ \fp_pow_0002:fp_pow_inst|Add54~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_cmpReg_q[0] = ~ \fp_pow_0002:fp_pow_inst|redist117_cmpReg_q[0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[4] = ~ \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[3] = ~ \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[2] = ~ \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[1] = ~ \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[0] = ~ \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[7] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[6] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[5] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[4] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[3] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[2] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[1] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[0] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist85|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist85|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[12] = ~ \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[12] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[4] = ~ \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[3] = ~ \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[2] = ~ \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[1] = ~ \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__excRNaN_uid204_fpPowrTest_q_i[0]~1 = ~ \fp_pow_0002:fp_pow_inst|excRNaN_uid204_fpPowrTest_q_i[0]~1 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist121|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist124_outputreg|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist124_outputreg|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__excRNaN_uid204_fpPowrTest_q_i[0]~0 = ~ \fp_pow_0002:fp_pow_inst|excRNaN_uid204_fpPowrTest_q_i[0]~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__exc_R_uid35_fpPowrTest_q[0] = ~ \fp_pow_0002:fp_pow_inst|exc_R_uid35_fpPowrTest_q[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_sticky_ena_q[0] = ~ \fp_pow_0002:fp_pow_inst|redist117_sticky_ena_q[0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist118_replace_mem_ia[0] = ~ \fp_pow_0002:fp_pow_inst|redist118_replace_mem_ia[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist119|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[12] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[12] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] = ~ \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[7] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[6] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[5] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[4] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[3] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[2] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[1] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist76|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist76|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[0] = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__zeroCase6_uid165_fpPowrTest_q_i[0]~0 = ~ \fp_pow_0002:fp_pow_inst|zeroCase6_uid165_fpPowrTest_q_i[0]~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist117_outputreg|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist117_outputreg|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist130_outputreg|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist130_outputreg|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist82_outputreg|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist82_outputreg|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[7] = ~ \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[6] = ~ \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[5] = ~ \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[4] = ~ \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[3] = ~ \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[2] = ~ \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[1] = ~ \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[0] = ~ \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 = ~ \fp_pow_0002:fp_pow_inst|excRZero_uid180_fpPowrTest_q[0]~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase2_uid174_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase2_uid174_fpPowrTest_delay|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase3_uid172_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase3_uid172_fpPowrTest_delay|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase4_uid170_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase4_uid170_fpPowrTest_delay|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase5_uid167_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase5_uid167_fpPowrTest_delay|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase6_uid165_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase6_uid165_fpPowrTest_delay|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] = ~ \fp_pow_0002:fp_pow_inst|excRInf_uid196_fpPowrTest_q[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:infCase0_uid195_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:infCase0_uid195_fpPowrTest_delay|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:infCase1_uid194_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:infCase1_uid194_fpPowrTest_delay|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:infCase2_uid192_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:infCase2_uid192_fpPowrTest_delay|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:infCase3_uid191_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:infCase3_uid191_fpPowrTest_delay|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:infCase4_uid187_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:infCase4_uid187_fpPowrTest_delay|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:infCase5_uid184_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:infCase5_uid184_fpPowrTest_delay|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|__ALT_INV__q_b[1] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|q_b[1] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|__ALT_INV__q_b[0] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|q_b[0] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[1] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[1] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[2] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[2] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[3] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[3] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[4] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[4] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[5] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[5] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[6] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[6] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[7] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[7] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[8] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[8] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[9] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[9] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[10] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[10] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[11] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[11] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[12] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[12] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[13] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[13] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[14] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[14] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[15] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[15] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[16] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[16] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[17] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[17] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[18] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[18] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[19] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[19] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[0] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][27] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][27] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][26] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][26] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][25] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][25] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][24] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][23] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][23] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][22] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][22] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][21] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][21] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][20] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][19] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][19] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][18] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][18] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][17] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][17] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][16] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][16] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][15] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][15] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][14] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][14] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[5] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[5] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[6] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[6] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[7] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[7] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[9] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[9] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[11] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[11] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[12] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[12] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[3] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[3] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[1] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[1] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[13] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[13] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[15] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[15] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[16] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[16] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[17] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[17] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[18] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[18] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[0] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[0] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[1] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[1] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[2] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[2] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[3] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[3] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[4] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[4] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[5] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[5] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[6] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[6] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[8] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[8] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[9] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][37] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][37] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][32] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][32] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][31] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][31] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][29] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][29] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][28] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][28] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][27] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][27] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][26] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][26] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][24] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][22] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][22] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][21] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][21] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][19] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][19] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][17] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][17] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][16] = ~ \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][16] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[7] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[7] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[8] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[8] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[9] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[9] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[10] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[10] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[13] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[13] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[14] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[14] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[17] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[17] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[19] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[19] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add3~117 = ~ \fp_pow_0002:fp_pow_inst|Add3~117 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][35] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][35] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][34] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][34] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][33] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][33] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][32] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][32] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][30] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][30] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][24] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][23] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][23] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][22] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][22] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][34] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][34] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][33] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][33] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][31] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][31] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][30] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][30] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][29] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][29] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][28] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][28] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][26] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][26] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][24] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][22] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][22] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][20] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][16] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][16] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][14] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][14] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][12] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][12] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][10] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][9] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][8] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][6] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][4] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][2] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][2] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|__ALT_INV__q_b[6] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[6] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|__ALT_INV__q_b[8] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[8] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|__ALT_INV__q_b[13] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[13] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|__ALT_INV__q_b[14] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[14] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|__ALT_INV__q_b[16] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[16] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|__ALT_INV__q_b[18] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[18] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|__ALT_INV__q_b[19] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[19] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[0] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[0] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[1] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[1] ; assign \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[4] = ~ \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[4] ; assign \__ALT_INV__areset~CLKENA0 = ~ \areset~CLKENA0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~36 = ~ \fp_pow_0002:fp_pow_inst|Ram7~36 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[1][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[1][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[1][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[1][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[1][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[1][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[2][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[2][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[2][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[1][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[1][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[1][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist44|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist44|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] = ~ \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] = ~ \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[0] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] = ~ \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] = ~ \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[1] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[2][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[2][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[2][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[2][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[0] = ~ \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[0] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] = ~ \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] = ~ \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[2] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[1][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[1][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[1] = ~ \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[1] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] = ~ \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] = ~ \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[3] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[1][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[2] = ~ \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[2] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] = ~ \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] = ~ \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[4] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal0~0 = ~ \fp_pow_0002:fp_pow_inst|Equal0~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[3] = ~ \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[3] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] = ~ \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] = ~ \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[5] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][39] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][39] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][38] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][38] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][37] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][37] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][36] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][36] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[4] = ~ \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[4] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] = ~ \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] = ~ \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[6] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[5] = ~ \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[5] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] = ~ \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] = ~ \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[7] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[24] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[23] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[23] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[22] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[22] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[21] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[21] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[20] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[19] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[19] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[18] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|__ALT_INV__delay_signals[34][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[34][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[6] = ~ \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[6] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] = ~ \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] = ~ \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[8] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[17] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[17] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[16] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[16] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[15] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[15] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[14] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[14] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[13] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[13] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[12] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[12] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[11] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[10] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[9] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[8] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[7] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[6] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[5] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[4] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[3] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[2] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[1] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[7] = ~ \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[7] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] = ~ \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] = ~ \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[9] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[8] = ~ \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[8] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] = ~ \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] = ~ \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[10] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|__ALT_INV__delay_signals[30][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[30][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist116|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist116|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[9] = ~ \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[9] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] = ~ \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] = ~ \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[1][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[11] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[9] = ~ \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[10] = ~ \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][56] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][56] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][38] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][38] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][39] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][39] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][40] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][40] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][41] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][41] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][36] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][36] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][55] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][55] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][37] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][37] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][42] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][42] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][49] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][49] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[31] = ~ \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][50] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][50] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][51] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][51] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[41] = ~ \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[41] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[53] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[53] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][52] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][52] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][43] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][43] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[44] = ~ \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[44] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][44] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][44] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[45] = ~ \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[45] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][45] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][45] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][46] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][46] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][47] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][47] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[40] = ~ \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[40] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][42] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][42] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][48] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][48] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[30] = ~ \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][36] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][36] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][37] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][37] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][38] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][38] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][39] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][39] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][40] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][40] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][41] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][41] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[34] = ~ \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[34] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[42] = ~ \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[42] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[43] = ~ \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[43] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[17] = ~ \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[46] = ~ \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[46] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[10] = ~ \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[10] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] = ~ \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] = ~ \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[12] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|__ALT_INV__delay_signals[14][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[14][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[11] = ~ \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[11] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] = ~ \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[13] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram4~9 = ~ \fp_pow_0002:fp_pow_inst|Ram4~9 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram4~8 = ~ \fp_pow_0002:fp_pow_inst|Ram4~8 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram4~7 = ~ \fp_pow_0002:fp_pow_inst|Ram4~7 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[24] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[26] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[27] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[29] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[11] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][36] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][36] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][37] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][37] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][38] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][38] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][39] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][39] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][41] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][41] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][42] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][42] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][43] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][43] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][40] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][40] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[50] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[50] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[45] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[45] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[46] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[46] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[49] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[49] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[38] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[38] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[42] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[42] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[33] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[35] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[35] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][44] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][44] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|__ALT_INV__delay_signals[27][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[27][0] ; assign \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[1][0] = ~ \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[1][0] ; assign \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[0][1] = ~ \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[0][1] ; assign \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[1][1] = ~ \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[1][1] ; assign \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[0][2] = ~ \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[0][2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_b0[0] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_b0[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[12] = ~ \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[12] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[12] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[12] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] = ~ \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[14] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[5] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[6] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[7] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[3] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[4] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][50] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][50] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][51] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][51] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[1] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[2] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][43] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][43] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][44] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][44] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][45] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][45] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][46] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][46] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][47] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][47] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][48] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][48] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][36] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][36] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][37] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][37] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][38] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][38] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][39] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][39] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][40] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][40] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][41] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][41] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[8] = ~ \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[1][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[1][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[1][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[1][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[1][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][3] ; assign \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[2][0] = ~ \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[2][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_a0[0] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_a0[0] ; assign \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[1][2] = ~ \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[1][2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_b0[1] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_b0[1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[13] = ~ \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[13] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[13] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[13] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] = ~ \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[15] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|__ALT_INV__delay_signals[1][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[0] = ~ \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_s1[0] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[0] ; assign \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[2][1] = ~ \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[2][1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_a0[1] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_a0[1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[14] = ~ \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[14] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[14] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[14] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] = ~ \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[16] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist107|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist107|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][49] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][49] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][50] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][50] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][51] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][51] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][43] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][43] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][44] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][44] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][45] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][45] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][46] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][46] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][47] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][47] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][42] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][42] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][48] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][48] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][36] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][36] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][37] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][37] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][38] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][38] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][39] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][39] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][40] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][40] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][41] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][41] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[2][2] = ~ \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[2][2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_b0[2] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_b0[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_a0[2] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_a0[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[27] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[27] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[26] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[26] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[28] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[28] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[25] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[25] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[24] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[29] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[15] = ~ \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[15] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[15] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[15] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] = ~ \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[1][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[17] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[53] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[53] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_s1[2] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[16] = ~ \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[16] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[16] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[16] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] = ~ \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[18] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[20] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[20] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|__ALT_INV__delay_signals[1][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[2] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[3] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[20] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[27] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[27] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[28] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[28] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[30] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[30] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[14] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[14] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[15] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[15] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[16] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[16] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[18] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[18] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[8] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[4] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[51] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[51] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[44] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[44] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[39] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[39] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[40] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[40] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[42] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[42] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[31] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[31] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[33] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_s1[3] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[31] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux57~0 = ~ \fp_pow_0002:fp_pow_inst|Mux57~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux58~0 = ~ \fp_pow_0002:fp_pow_inst|Mux58~0 ; assign \__ALT_INV__rtl~315 = ~ \rtl~315 ; assign \__ALT_INV__rtl~314 = ~ \rtl~314 ; assign \__ALT_INV__rtl~313 = ~ \rtl~313 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux60~0 = ~ \fp_pow_0002:fp_pow_inst|Mux60~0 ; assign \__ALT_INV__rtl~312 = ~ \rtl~312 ; assign \__ALT_INV__rtl~311 = ~ \rtl~311 ; assign \__ALT_INV__rtl~310 = ~ \rtl~310 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~3 = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~3 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~2 = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~2 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux59~0 = ~ \fp_pow_0002:fp_pow_inst|Mux59~0 ; assign \__ALT_INV__rtl~309 = ~ \rtl~309 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux21~0 = ~ \fp_pow_0002:fp_pow_inst|Mux21~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux22~0 = ~ \fp_pow_0002:fp_pow_inst|Mux22~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux23~0 = ~ \fp_pow_0002:fp_pow_inst|Mux23~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux24~0 = ~ \fp_pow_0002:fp_pow_inst|Mux24~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux56~0 = ~ \fp_pow_0002:fp_pow_inst|Mux56~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux40~0 = ~ \fp_pow_0002:fp_pow_inst|Mux40~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux48~0 = ~ \fp_pow_0002:fp_pow_inst|Mux48~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux52~0 = ~ \fp_pow_0002:fp_pow_inst|Mux52~0 ; assign \__ALT_INV__rtl~308 = ~ \rtl~308 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux54~0 = ~ \fp_pow_0002:fp_pow_inst|Mux54~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux38~0 = ~ \fp_pow_0002:fp_pow_inst|Mux38~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux46~0 = ~ \fp_pow_0002:fp_pow_inst|Mux46~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux50~0 = ~ \fp_pow_0002:fp_pow_inst|Mux50~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux42~0 = ~ \fp_pow_0002:fp_pow_inst|Mux42~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux26~0 = ~ \fp_pow_0002:fp_pow_inst|Mux26~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux55~0 = ~ \fp_pow_0002:fp_pow_inst|Mux55~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux39~0 = ~ \fp_pow_0002:fp_pow_inst|Mux39~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux47~0 = ~ \fp_pow_0002:fp_pow_inst|Mux47~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux51~0 = ~ \fp_pow_0002:fp_pow_inst|Mux51~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux53~0 = ~ \fp_pow_0002:fp_pow_inst|Mux53~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux37~0 = ~ \fp_pow_0002:fp_pow_inst|Mux37~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux45~0 = ~ \fp_pow_0002:fp_pow_inst|Mux45~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux49~0 = ~ \fp_pow_0002:fp_pow_inst|Mux49~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux41~0 = ~ \fp_pow_0002:fp_pow_inst|Mux41~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux25~0 = ~ \fp_pow_0002:fp_pow_inst|Mux25~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[17] = ~ \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[17] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[17] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[17] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[19] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[21] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[21] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[21] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[21] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[20] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram5~9 = ~ \fp_pow_0002:fp_pow_inst|Ram5~9 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram5~8 = ~ \fp_pow_0002:fp_pow_inst|Ram5~8 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram5~7 = ~ \fp_pow_0002:fp_pow_inst|Ram5~7 ; assign \__ALT_INV__rtl~307 = ~ \rtl~307 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 = ~ \fp_pow_0002:fp_pow_inst|Equal9~13 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~12 = ~ \fp_pow_0002:fp_pow_inst|Equal9~12 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~11 = ~ \fp_pow_0002:fp_pow_inst|Equal9~11 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~10 = ~ \fp_pow_0002:fp_pow_inst|Equal9~10 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~9 = ~ \fp_pow_0002:fp_pow_inst|Equal9~9 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~8 = ~ \fp_pow_0002:fp_pow_inst|Equal9~8 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 = ~ \fp_pow_0002:fp_pow_inst|Equal9~7 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~6 = ~ \fp_pow_0002:fp_pow_inst|Equal9~6 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~5 = ~ \fp_pow_0002:fp_pow_inst|Equal9~5 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[5] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[6] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[7] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[8] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~4 = ~ \fp_pow_0002:fp_pow_inst|Equal9~4 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[10] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[11] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[12] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[12] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[13] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[13] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[14] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[14] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[3] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[4] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[9] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~3 = ~ \fp_pow_0002:fp_pow_inst|Equal9~3 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][49] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][49] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][50] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][50] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][51] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][51] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[1] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[2] = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~2 = ~ \fp_pow_0002:fp_pow_inst|Equal9~2 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][43] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][43] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][44] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][44] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][45] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][45] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][46] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][46] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][47] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][47] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][42] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][42] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 = ~ \fp_pow_0002:fp_pow_inst|Equal9~1 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][36] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][36] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][37] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][37] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][39] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][39] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][40] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][40] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][41] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][41] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 = ~ \fp_pow_0002:fp_pow_inst|Equal9~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal22~6 = ~ \fp_pow_0002:fp_pow_inst|Equal22~6 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal22~5 = ~ \fp_pow_0002:fp_pow_inst|Equal22~5 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal22~4 = ~ \fp_pow_0002:fp_pow_inst|Equal22~4 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal22~3 = ~ \fp_pow_0002:fp_pow_inst|Equal22~3 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[0] = ~ \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal22~2 = ~ \fp_pow_0002:fp_pow_inst|Equal22~2 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal22~1 = ~ \fp_pow_0002:fp_pow_inst|Equal22~1 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal22~0 = ~ \fp_pow_0002:fp_pow_inst|Equal22~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[32] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[43] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[43] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[42] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[42] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[41] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[41] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[40] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[40] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[39] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[39] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[38] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[38] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[37] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[37] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[36] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[36] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[35] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[35] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[34] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[34] ; assign \__ALT_INV__rtl~217 = ~ \rtl~217 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[25] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[25] ; assign \__ALT_INV__rtl~216 = ~ \rtl~216 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[26] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[26] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[30] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[30] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[28] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[28] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[32] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[32] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[27] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[27] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[31] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[31] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[33] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[33] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[56] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[56] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[55] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[55] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[54] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[54] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[53] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[53] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[52] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[52] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[44] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[44] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[48] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[48] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[46] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[46] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[50] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[50] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[45] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[45] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[49] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[49] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[47] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[47] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[51] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[51] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|__ALT_INV__delay_signals[7][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[7][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[18] = ~ \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[18] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[18] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[18] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[20] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[22] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[22] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[22] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[22] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[21] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[57] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[57] ; assign \__ALT_INV__rtl~305 = ~ \rtl~305 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][59] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][59] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux33~0 = ~ \fp_pow_0002:fp_pow_inst|Mux33~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][43] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][43] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][27] ; assign \__ALT_INV__rtl~304 = ~ \rtl~304 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][51] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][51] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][19] ; assign \__ALT_INV__rtl~302 = ~ \rtl~302 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][63] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][63] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux29~0 = ~ \fp_pow_0002:fp_pow_inst|Mux29~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][47] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][47] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][31] ; assign \__ALT_INV__rtl~301 = ~ \rtl~301 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][39] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][39] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][55] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][55] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][23] ; assign \__ALT_INV__rtl~299 = ~ \rtl~299 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][61] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][61] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux31~0 = ~ \fp_pow_0002:fp_pow_inst|Mux31~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][45] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][45] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][29] ; assign \__ALT_INV__rtl~298 = ~ \rtl~298 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][37] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][37] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][53] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][53] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux35~0 = ~ \fp_pow_0002:fp_pow_inst|Mux35~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][41] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][41] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux19~0 = ~ \fp_pow_0002:fp_pow_inst|Mux19~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][57] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][57] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux27~0 = ~ \fp_pow_0002:fp_pow_inst|Mux27~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][49] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][49] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][17] ; assign \__ALT_INV__rtl~297 = ~ \rtl~297 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][65] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][65] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][33] ; assign \__ALT_INV__rtl~295 = ~ \rtl~295 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][58] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][58] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux34~0 = ~ \fp_pow_0002:fp_pow_inst|Mux34~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][42] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][42] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][26] ; assign \__ALT_INV__rtl~294 = ~ \rtl~294 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][50] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][50] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][18] ; assign \__ALT_INV__rtl~292 = ~ \rtl~292 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][62] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][62] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux30~0 = ~ \fp_pow_0002:fp_pow_inst|Mux30~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][46] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][46] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][30] ; assign \__ALT_INV__rtl~291 = ~ \rtl~291 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][38] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][38] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][54] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][54] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][22] ; assign \__ALT_INV__rtl~289 = ~ \rtl~289 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][60] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][60] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux32~0 = ~ \fp_pow_0002:fp_pow_inst|Mux32~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][44] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][44] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~1 = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~1 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~0 = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~0 ; assign \__ALT_INV__rtl~288 = ~ \rtl~288 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][28] ; assign \__ALT_INV__rtl~287 = ~ \rtl~287 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][36] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][36] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][52] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][52] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux36~0 = ~ \fp_pow_0002:fp_pow_inst|Mux36~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][40] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][40] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux20~0 = ~ \fp_pow_0002:fp_pow_inst|Mux20~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][56] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][56] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux28~0 = ~ \fp_pow_0002:fp_pow_inst|Mux28~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][48] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][48] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][16] ; assign \__ALT_INV__rtl~286 = ~ \rtl~286 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][64] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][64] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|__ALT_INV__delay_signals[1][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][27] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal10~6 = ~ \fp_pow_0002:fp_pow_inst|Equal10~6 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal10~5 = ~ \fp_pow_0002:fp_pow_inst|Equal10~5 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal10~4 = ~ \fp_pow_0002:fp_pow_inst|Equal10~4 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal10~3 = ~ \fp_pow_0002:fp_pow_inst|Equal10~3 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal10~2 = ~ \fp_pow_0002:fp_pow_inst|Equal10~2 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal10~1 = ~ \fp_pow_0002:fp_pow_inst|Equal10~1 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal10~0 = ~ \fp_pow_0002:fp_pow_inst|Equal10~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[2][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[2][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|__ALT_INV__delay_signals[20][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[20][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_s1[5] = ~ \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[33] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[19] = ~ \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[19] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[19] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[19] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[21] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[23] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[23] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[23] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][22] ; assign \__ALT_INV__rtl~146 = ~ \rtl~146 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[59] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[59] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[63] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[63] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[61] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[61] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[65] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[65] ; assign \__ALT_INV__rtl~147 = ~ \rtl~147 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[58] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[58] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[62] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[62] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[64] = ~ \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[64] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|__ALT_INV__delay_signals[1][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_eq = ~ \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_eq ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal11~2 = ~ \fp_pow_0002:fp_pow_inst|Equal11~2 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[14]~14 = ~ \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[14]~14 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[12]~13 = ~ \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[12]~13 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[5]~12 = ~ \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[5]~12 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal11~1 = ~ \fp_pow_0002:fp_pow_inst|Equal11~1 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal11~0 = ~ \fp_pow_0002:fp_pow_inst|Equal11~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[9]~11 = ~ \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[9]~11 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[10]~10 = ~ \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[10]~10 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[6]~9 = ~ \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[6]~9 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[7]~8 = ~ \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[7]~8 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[2]~7 = ~ \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[2]~7 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[3]~6 = ~ \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[3]~6 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[4]~5 = ~ \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[4]~5 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[8]~4 = ~ \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[8]~4 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[13]~3 = ~ \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[13]~3 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[15]~2 = ~ \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[15]~2 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[11]~1 = ~ \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[11]~1 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[1]~0 = ~ \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[1]~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|__ALT_INV__delay_signals[19][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[19][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|__ALT_INV__delay_signals[20][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[20][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~18 = ~ \fp_pow_0002:fp_pow_inst|Ram7~18 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[34] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[34] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[20] = ~ \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[20] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[22] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[24] = ~ \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[24] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[23] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][36] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][36] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[3] = ~ \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[2] = ~ \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[1] = ~ \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[0] = ~ \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__xInZO_uid159_fpPowrTest_o[10] = ~ \fp_pow_0002:fp_pow_inst|xInZO_uid159_fpPowrTest_o[10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][37] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][37] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal12~3 = ~ \fp_pow_0002:fp_pow_inst|Equal12~3 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal12~2 = ~ \fp_pow_0002:fp_pow_inst|Equal12~2 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal12~1 = ~ \fp_pow_0002:fp_pow_inst|Equal12~1 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal12~0 = ~ \fp_pow_0002:fp_pow_inst|Equal12~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid300_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid300_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|__ALT_INV__delay_signals[19][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[19][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal6~0 = ~ \fp_pow_0002:fp_pow_inst|Equal6~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal5~0 = ~ \fp_pow_0002:fp_pow_inst|Equal5~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|__ALT_INV__delay_signals[18][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[18][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[11] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[10] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[9] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[8] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[7] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[16] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[12] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][36] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][36] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[17] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~15 = ~ \fp_pow_0002:fp_pow_inst|Ram7~15 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[21] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[21] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[23] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[25] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[25] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[24] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_cmpReg_q[0] = ~ \fp_pow_0002:fp_pow_inst|redist137_cmpReg_q[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][38] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][38] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal14~0 = ~ \fp_pow_0002:fp_pow_inst|Equal14~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Equal13~0 = ~ \fp_pow_0002:fp_pow_inst|Equal13~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][7] ; assign \__ALT_INV__rtl~135 = ~ \rtl~135 ; assign \__ALT_INV__rtl~133 = ~ \rtl~133 ; assign \__ALT_INV__rtl~131 = ~ \rtl~131 ; assign \__ALT_INV__rtl~129 = ~ \rtl~129 ; assign \__ALT_INV__rtl~127 = ~ \rtl~127 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][0] ; assign \__ALT_INV__rtl~125 = ~ \rtl~125 ; assign \__ALT_INV__rtl~124 = ~ \rtl~124 ; assign \__ALT_INV__rtl~121 = ~ \rtl~121 ; assign \__ALT_INV__rtl~118 = ~ \rtl~118 ; assign \__ALT_INV__rtl~117 = ~ \rtl~117 ; assign \__ALT_INV__rtl~114 = ~ \rtl~114 ; assign \__ALT_INV__rtl~111 = ~ \rtl~111 ; assign \__ALT_INV__rtl~110 = ~ \rtl~110 ; assign \__ALT_INV__rtl~107 = ~ \rtl~107 ; assign \__ALT_INV__rtl~104 = ~ \rtl~104 ; assign \__ALT_INV__rtl~103 = ~ \rtl~103 ; assign \__ALT_INV__rtl~100 = ~ \rtl~100 ; assign \__ALT_INV__rtl~97 = ~ \rtl~97 ; assign \__ALT_INV__rtl~89 = ~ \rtl~89 ; assign \__ALT_INV__rtl~87 = ~ \rtl~87 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux212~0 = ~ \fp_pow_0002:fp_pow_inst|Mux212~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][12] ; assign \__ALT_INV__rtl~86 = ~ \rtl~86 ; assign \__ALT_INV__rtl~85 = ~ \rtl~85 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][10] ; assign \__ALT_INV__rtl~84 = ~ \rtl~84 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux213~0 = ~ \fp_pow_0002:fp_pow_inst|Mux213~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][11] ; assign \__ALT_INV__rtl~83 = ~ \rtl~83 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux211~0 = ~ \fp_pow_0002:fp_pow_inst|Mux211~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][13] ; assign \__ALT_INV__rtl~82 = ~ \rtl~82 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][9] ; assign \__ALT_INV__rtl~80 = ~ \rtl~80 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux210~0 = ~ \fp_pow_0002:fp_pow_inst|Mux210~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[36] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[36] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][37] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][37] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|__ALT_INV__delay_signals[3][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[3][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[18] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~13 = ~ \fp_pow_0002:fp_pow_inst|Ram7~13 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~12 = ~ \fp_pow_0002:fp_pow_inst|Ram7~12 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[22] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[22] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[24] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[26] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[26] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[25] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_sticky_ena_q[0] = ~ \fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][39] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][39] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist56|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist58|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist61|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[17][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[17][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[17][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[17][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|__ALT_INV__delay_signals[17][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[17][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[8] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[7] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[6] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[5] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[4] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[3] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[2] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[1] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[0] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[13] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[12] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[11] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[10] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[9] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[37] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[37] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][37] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][37] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[14] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][15] ; assign \__ALT_INV__rtl~77 = ~ \rtl~77 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux209~0 = ~ \fp_pow_0002:fp_pow_inst|Mux209~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][38] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][38] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[23] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[23] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[25] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[27] = ~ \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[6] = ~ \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][40] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][40] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Add20~0 = ~ \fp_pow_0002:fp_pow_inst|Add20~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[16][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[16][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|__ALT_INV__delay_signals[15][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[15][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[34] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[34] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][38] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][38] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[15] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[1][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[1][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[1][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[38] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[38] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][39] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][39] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux228~1 = ~ \fp_pow_0002:fp_pow_inst|Mux228~1 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[42] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[42] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[19] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][20] ; assign \__ALT_INV__rtl~58 = ~ \rtl~58 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux204~0 = ~ \fp_pow_0002:fp_pow_inst|Mux204~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[4] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[3] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][47] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][47] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][46] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][46] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][51] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][51] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][50] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][50] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][43] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][43] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][42] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][42] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[2] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[1] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][45] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][45] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][44] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][44] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][49] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][49] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][48] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][48] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] = ~ \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][41] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][41] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][40] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][40] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[3][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[3][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[24] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[33] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[37] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[37] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[39] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[39] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[28] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[28] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[30] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[31] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[35] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[35] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[1] = ~ \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[3] = ~ \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[34] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[34] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[38] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[38] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[40] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[40] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[32] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[2] = ~ \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[36] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[36] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[41] = ~ \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[41] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[11] = ~ \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_replace_rdcnt_eq = ~ \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_eq ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[5] = ~ \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist9_replace_rdcnt_i[1] = ~ \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist9_replace_rdcnt_i[0] = ~ \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|__ALT_INV__delay_signals[10][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[10][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[11][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[11][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[1][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[1][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[1][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[1][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[1][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[1][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[1][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[39] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[39] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][40] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][40] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux226~0 = ~ \fp_pow_0002:fp_pow_inst|Mux226~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux225~0 = ~ \fp_pow_0002:fp_pow_inst|Mux225~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux227~0 = ~ \fp_pow_0002:fp_pow_inst|Mux227~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[43] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[43] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[20] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][21] ; assign \__ALT_INV__rtl~55 = ~ \rtl~55 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux203~0 = ~ \fp_pow_0002:fp_pow_inst|Mux203~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist102_cmpReg_q[0] = ~ \fp_pow_0002:fp_pow_inst|redist102_cmpReg_q[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[2][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[2][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[25] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[29] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[29] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[31] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[0] = ~ \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_replace_rdcnt_i[3] = ~ \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_replace_rdcnt_i[2] = ~ \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[6] = ~ \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[10][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[10][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[10][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[10][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_eq = ~ \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_eq ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[2][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[2][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[40] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[40] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][41] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][41] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[44] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[44] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[21] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][22] ; assign \__ALT_INV__rtl~50 = ~ \rtl~50 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux202~0 = ~ \fp_pow_0002:fp_pow_inst|Mux202~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist102_sticky_ena_q[0] = ~ \fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[26] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][38] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][38] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][40] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][40] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[30] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[30] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[32] = ~ \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][36] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][36] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][39] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][39] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][41] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][41] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][37] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][37] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][42] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][42] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_cmpReg_q[0] = ~ \fp_pow_0002:fp_pow_inst|redist134_cmpReg_q[0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[7] = ~ \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[9][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[9][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[9][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[9][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[4] = ~ \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[3] = ~ \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[2] = ~ \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[1] = ~ \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[0] = ~ \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|__ALT_INV__delay_signals[8][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[8][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][15] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][15] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][14] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][14] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][13] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][13] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][20] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][20] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][16] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][16] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[1][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[1][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[1][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[1][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux172~0 = ~ \fp_pow_0002:fp_pow_inst|Mux172~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[41] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[41] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][42] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][42] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux228~0 = ~ \fp_pow_0002:fp_pow_inst|Mux228~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[45] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[45] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[22] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][23] ; assign \__ALT_INV__rtl~45 = ~ \rtl~45 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux201~0 = ~ \fp_pow_0002:fp_pow_inst|Mux201~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][23] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[27] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[31] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[31] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[1] = ~ \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[3] = ~ \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[3] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[2] = ~ \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[2] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[4] = ~ \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[4] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[5] = ~ \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[0] = ~ \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_sticky_ena_q[0] = ~ \fp_pow_0002:fp_pow_inst|redist134_sticky_ena_q[0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[8] = ~ \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[8][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[8][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][21] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][21] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][17] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][17] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[42] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[42] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][43] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][43] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[46] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[46] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[23] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[23] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][24] ; assign \__ALT_INV__rtl~43 = ~ \rtl~43 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux200~0 = ~ \fp_pow_0002:fp_pow_inst|Mux200~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][24] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][41] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][41] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][37] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][37] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][39] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][39] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][27] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][40] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][40] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][36] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][36] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][38] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][38] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][43] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][43] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][42] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][42] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[28] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[28] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][28] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[34] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[34] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[38] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[38] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[40] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[40] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[32] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[32] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[36] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[36] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[35] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[35] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[39] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[39] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[41] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[41] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[33] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[33] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[37] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[37] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[42] = ~ \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[42] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[9] = ~ \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[7][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[7][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][22] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][22] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][11] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][11] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][9] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][9] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][18] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][18] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[36] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[36] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][36] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][36] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[35] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[35] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[34] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[34] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[33] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[33] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[32] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[32] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[31] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[31] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[30] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][44] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][44] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[47] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[47] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[24] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[24] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][25] ; assign \__ALT_INV__rtl~41 = ~ \rtl~41 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux199~0 = ~ \fp_pow_0002:fp_pow_inst|Mux199~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][25] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][25] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[29] = ~ \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[29] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][29] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux162~0 = ~ \fp_pow_0002:fp_pow_inst|Mux162~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux163~0 = ~ \fp_pow_0002:fp_pow_inst|Mux163~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux164~0 = ~ \fp_pow_0002:fp_pow_inst|Mux164~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux166~0 = ~ \fp_pow_0002:fp_pow_inst|Mux166~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux167~1 = ~ \fp_pow_0002:fp_pow_inst|Mux167~1 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux178~0 = ~ \fp_pow_0002:fp_pow_inst|Mux178~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux165~0 = ~ \fp_pow_0002:fp_pow_inst|Mux165~0 ; assign \__ALT_INV__rtl~281 = ~ \rtl~281 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux167~0 = ~ \fp_pow_0002:fp_pow_inst|Mux167~0 ; assign \__ALT_INV__rtl~280 = ~ \rtl~280 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux168~2 = ~ \fp_pow_0002:fp_pow_inst|Mux168~2 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_eq = ~ \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_eq ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|__ALT_INV__delay_signals[5][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[5][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][8] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][8] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[10] = ~ \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|__ALT_INV__delay_signals[6][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[6][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[6][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[6][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][12] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][12] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][10] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][10] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][19] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][19] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[2][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[2][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][2] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[2][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][1] ; assign \__ALT_INV__rtl~279 = ~ \rtl~279 ; assign \__ALT_INV__rtl~278 = ~ \rtl~278 ; assign \__ALT_INV__rtl~277 = ~ \rtl~277 ; assign \__ALT_INV__rtl~23 = ~ \rtl~23 ; assign \__ALT_INV__rtl~21 = ~ \rtl~21 ; assign \__ALT_INV__rtl~19 = ~ \rtl~19 ; assign \__ALT_INV__rtl~17 = ~ \rtl~17 ; assign \__ALT_INV__rtl~15 = ~ \rtl~15 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux182~0 = ~ \fp_pow_0002:fp_pow_inst|Mux182~0 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[25] = ~ \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[25] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[0][1] ; assign \__ALT_INV__rtl~13 = ~ \rtl~13 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux183~0 = ~ \fp_pow_0002:fp_pow_inst|Mux183~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][41] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][41] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux191~0 = ~ \fp_pow_0002:fp_pow_inst|Mux191~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][33] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][33] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux187~0 = ~ \fp_pow_0002:fp_pow_inst|Mux187~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][37] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][37] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux195~0 = ~ \fp_pow_0002:fp_pow_inst|Mux195~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][29] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][29] ; assign \__ALT_INV__rtl~12 = ~ \rtl~12 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux185~0 = ~ \fp_pow_0002:fp_pow_inst|Mux185~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][39] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][39] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux193~0 = ~ \fp_pow_0002:fp_pow_inst|Mux193~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][31] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][31] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux189~0 = ~ \fp_pow_0002:fp_pow_inst|Mux189~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][35] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][35] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux197~0 = ~ \fp_pow_0002:fp_pow_inst|Mux197~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][27] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][27] ; assign \__ALT_INV__rtl~11 = ~ \rtl~11 ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux184~0 = ~ \fp_pow_0002:fp_pow_inst|Mux184~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][40] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][40] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux192~0 = ~ \fp_pow_0002:fp_pow_inst|Mux192~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][32] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][32] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux188~0 = ~ \fp_pow_0002:fp_pow_inst|Mux188~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][36] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][36] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux196~0 = ~ \fp_pow_0002:fp_pow_inst|Mux196~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][28] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][28] ; assign \__ALT_INV__rtl~10 = ~ \rtl~10 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux186~0 = ~ \fp_pow_0002:fp_pow_inst|Mux186~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][38] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][38] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux194~0 = ~ \fp_pow_0002:fp_pow_inst|Mux194~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][30] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][30] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux190~0 = ~ \fp_pow_0002:fp_pow_inst|Mux190~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][34] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][34] ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__Mux198~0 = ~ \fp_pow_0002:fp_pow_inst|Mux198~0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][43] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][26] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][26] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[0][0] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][42] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][42] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[0][1] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][7] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][6] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][5] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][4] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][3] ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2] = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][2] ; assign \__ALT_INV__a[14]~input0 = ~ \a[14]~input0 ; assign \__ALT_INV__a[0]~input0 = ~ \a[0]~input0 ; assign \__ALT_INV__a[12]~input0 = ~ \a[12]~input0 ; assign \__ALT_INV__a[13]~input0 = ~ \a[13]~input0 ; assign \__ALT_INV__a[8]~input0 = ~ \a[8]~input0 ; assign \__ALT_INV__a[9]~input0 = ~ \a[9]~input0 ; assign \__ALT_INV__a[10]~input0 = ~ \a[10]~input0 ; assign \__ALT_INV__a[6]~input0 = ~ \a[6]~input0 ; assign \__ALT_INV__a[7]~input0 = ~ \a[7]~input0 ; assign \__ALT_INV__a[1]~input0 = ~ \a[1]~input0 ; assign \__ALT_INV__a[2]~input0 = ~ \a[2]~input0 ; assign \__ALT_INV__a[3]~input0 = ~ \a[3]~input0 ; assign \__ALT_INV__a[4]~input0 = ~ \a[4]~input0 ; assign \__ALT_INV__a[5]~input0 = ~ \a[5]~input0 ; assign \__ALT_INV__a[18]~input0 = ~ \a[18]~input0 ; assign \__ALT_INV__a[21]~input0 = ~ \a[21]~input0 ; assign \__ALT_INV__a[22]~input0 = ~ \a[22]~input0 ; assign \__ALT_INV__a[23]~input0 = ~ \a[23]~input0 ; assign \__ALT_INV__a[24]~input0 = ~ \a[24]~input0 ; assign \__ALT_INV__a[25]~input0 = ~ \a[25]~input0 ; assign \__ALT_INV__a[26]~input0 = ~ \a[26]~input0 ; assign \__ALT_INV__a[27]~input0 = ~ \a[27]~input0 ; assign \__ALT_INV__a[28]~input0 = ~ \a[28]~input0 ; assign \__ALT_INV__a[29]~input0 = ~ \a[29]~input0 ; assign \__ALT_INV__a[30]~input0 = ~ \a[30]~input0 ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][2]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][2]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][0]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][0]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][4]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][4]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][49]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][49]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][42]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][42]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][4]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][4]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][0]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][0]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][17]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][17]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[5]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[5]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[14]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[14]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][45]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][45]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][48]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][48]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][38]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][38]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][40]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][40]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][41]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][41]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][7]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][7]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][1]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][1]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][2]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][2]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][17]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][17]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][18]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][18]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][16]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][16]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][24]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][24]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][25]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][25]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][9]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][9]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][16]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][16]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[3]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[3]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[2]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[0]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[0]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][1]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][1]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][10]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][10]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][9]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][9]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][3]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][3]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][1]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][1]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|__ALT_INV__delay_signals[0][3]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][3]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist56|delay_signals[0][0]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][1]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][2]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][14]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][14]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][1]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][1]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_replace_rdcnt_eq~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_eq~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist9_replace_rdcnt_i[0]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[0]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_replace_rdcnt_i[3]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[3]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[4]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[2]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[2]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[1]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[1]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[0][0]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][2]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[2]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[2]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[1]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[1]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][35]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][35]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][33]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][33]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][1]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][1]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[4]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[4]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[3]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[3]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[2]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[2]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_eq~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_eq~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[2]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[2]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[1]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[1]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[3]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[3]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[2]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[2]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[1]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[1]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[0]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[0]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[3]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[0]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[0]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[1]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[1]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[0][0]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[0][0]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|__ALT_INV__delay_signals[0][0]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[0][0]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[2]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[2]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist76|__ALT_INV__delay_signals[0][0]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist76|delay_signals[0][0]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|__ALT_INV__delay_signals[0][0]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[0][0]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|delay_signals[0][0]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][13]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][13]~DUPLICATE ; assign \fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[9]~DUPLICATE = ~ \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[9]~DUPLICATE ; assign q[0] = \fp_pow_0002:fp_pow_inst|Mux343~0 ; assign q[1] = \fp_pow_0002:fp_pow_inst|Mux342~0 ; assign q[2] = \fp_pow_0002:fp_pow_inst|Mux341~0 ; assign q[3] = \fp_pow_0002:fp_pow_inst|Mux340~0 ; assign q[4] = \fp_pow_0002:fp_pow_inst|Mux339~0 ; assign q[5] = \fp_pow_0002:fp_pow_inst|Mux338~0 ; assign q[6] = \fp_pow_0002:fp_pow_inst|Mux337~0 ; assign q[7] = \fp_pow_0002:fp_pow_inst|Mux336~0 ; assign q[8] = \fp_pow_0002:fp_pow_inst|Mux335~0 ; assign q[9] = \fp_pow_0002:fp_pow_inst|Mux334~0 ; assign q[10] = \fp_pow_0002:fp_pow_inst|Mux333~0 ; assign q[11] = \fp_pow_0002:fp_pow_inst|Mux332~0 ; assign q[12] = \fp_pow_0002:fp_pow_inst|Mux331~0 ; assign q[13] = \fp_pow_0002:fp_pow_inst|Mux330~0 ; assign q[14] = \fp_pow_0002:fp_pow_inst|Mux329~0 ; assign q[15] = \fp_pow_0002:fp_pow_inst|Mux328~0 ; assign q[16] = \fp_pow_0002:fp_pow_inst|Mux327~0 ; assign q[17] = \fp_pow_0002:fp_pow_inst|Mux326~0 ; assign q[18] = \fp_pow_0002:fp_pow_inst|Mux325~0 ; assign q[19] = \fp_pow_0002:fp_pow_inst|Mux324~0 ; assign q[20] = \fp_pow_0002:fp_pow_inst|Mux323~0 ; assign q[21] = \fp_pow_0002:fp_pow_inst|Mux322~0 ; assign q[22] = \fp_pow_0002:fp_pow_inst|Mux321~0 ; assign q[23] = \fp_pow_0002:fp_pow_inst|Mux320~0 ; assign q[24] = \fp_pow_0002:fp_pow_inst|Mux319~0 ; assign q[25] = \fp_pow_0002:fp_pow_inst|Mux318~0 ; assign q[26] = \fp_pow_0002:fp_pow_inst|Mux317~0 ; assign q[27] = \fp_pow_0002:fp_pow_inst|Mux316~0 ; assign q[28] = \fp_pow_0002:fp_pow_inst|Mux315~0 ; assign q[29] = \fp_pow_0002:fp_pow_inst|Mux314~0 ; assign q[30] = \fp_pow_0002:fp_pow_inst|Mux313~0 ; assign q[31] = gnd; assign \clk~input0 = clk; cyclonev_clkena \clk~CLKENA0_I ( .inclk(\clk~input0 ), .outclk(\clk~CLKENA0 )); defparam \clk~CLKENA0_I .clock_type = "Global Clock"; defparam \clk~CLKENA0_I .ena_register_mode = "always enabled"; defparam \clk~CLKENA0_I .ena_register_power_up = "high"; defparam \clk~CLKENA0_I .disable_mode = "low"; defparam \clk~CLKENA0_I .test_syn = "high"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist130_sticky_ena_q[0]~feeder_I ( .combout(\fp_pow_0002:fp_pow_inst|redist130_sticky_ena_q[0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist130_sticky_ena_q[0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist130_sticky_ena_q[0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist130_sticky_ena_q[0]~feeder_I .lut_mask = "FFFFFFFFFFFFFFFF"; assign \areset~input0 = areset; cyclonev_clkena \areset~CLKENA0_I ( .inclk(\areset~input0 ), .outclk(\areset~CLKENA0 )); defparam \areset~CLKENA0_I .clock_type = "Global Clock"; defparam \areset~CLKENA0_I .ena_register_mode = "always enabled"; defparam \areset~CLKENA0_I .ena_register_power_up = "high"; defparam \areset~CLKENA0_I .disable_mode = "low"; defparam \areset~CLKENA0_I .test_syn = "high"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i~1_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[1] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_eq ), .combout(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i~1 )); defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i~1_I .lut_mask = "F00FF00FFF00FF00"; dffeas \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[1] )); defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[2]~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_eq ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[2] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[1] ), .combout(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[2]~2 )); defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[2]~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[2]~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[2]~2_I .lut_mask = "00FF00FFAF50AF50"; dffeas \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[2]~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[2] )); defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~3_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[2] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_eq ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[3] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[1] ), .combout(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~3 )); defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~3_I .lut_mask = "0FF00FF02CD32CD3"; dffeas \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~3 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3] )); defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[4]~4_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_eq ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[3] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[1] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[4] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[4]~4 )); defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[4]~4_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[4]~4_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[4]~4_I .lut_mask = "0303FCFC033BFCC4"; dffeas \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[4]~4 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[4] )); defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~3 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~DUPLICATE_I .created_from = "Q(redist78_replace_rdcnt_i[3])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal28~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[4] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[2] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[3]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[1] ), .combout(\fp_pow_0002:fp_pow_inst|Equal28~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal28~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal28~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal28~0_I .lut_mask = "0200020000000000"; dffeas \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_eq~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal28~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_eq )); defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_eq~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_eq~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[0]~0_I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_eq ), .combout(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[0]~0_I .lut_mask = "FF00FF0000FF00FF"; dffeas \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[0]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[0] )); defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal27~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[2] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[3] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[4] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[1] ), .combout(\fp_pow_0002:fp_pow_inst|Equal27~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal27~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal27~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal27~0_I .lut_mask = "0000000000100010"; dffeas \fp_pow_0002:fp_pow_inst|redist78_cmpReg_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal27~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist78_cmpReg_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist78_cmpReg_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist78_cmpReg_q[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist130_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist130_sticky_ena_q[0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|redist78_cmpReg_q[0] ), .q(\fp_pow_0002:fp_pow_inst|redist130_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist130_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist130_sticky_ena_q[0]~I .is_wysiwyg = "true"; assign \b[31]~input0 = b[31]; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[35][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\b[31]~input0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[35][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[35][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[35][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[34][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[35][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[34][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[34][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[34][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[33][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[34][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[33][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[33][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[33][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[32][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[33][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[32][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[32][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[32][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[31][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[32][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[31][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[31][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[31][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[30][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[31][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[30][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[30][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[30][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[29][0]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|__ALT_INV__delay_signals[30][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[29][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[29][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[29][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[29][0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[29][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[29][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[29][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[29][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[29][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[28][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[29][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[28][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[28][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[28][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[27][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[28][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[27][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[27][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[27][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[26][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|__ALT_INV__delay_signals[27][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[26][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[26][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[26][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[26][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[26][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[26][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[26][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[26][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[26][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[25][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[26][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[25][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[25][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[25][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[24][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[25][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[24][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[24][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[24][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[23][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[24][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[23][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[23][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[23][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[22][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[23][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[22][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[22][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[22][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[21][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[22][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[21][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[21][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[21][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[20][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[21][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[20][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[20][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[20][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[19][0]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|__ALT_INV__delay_signals[20][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[19][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[19][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[19][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[19][0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[19][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[19][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[19][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[19][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[19][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[18][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[19][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[18][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[18][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[18][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[17][0]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|__ALT_INV__delay_signals[18][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[17][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[17][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[17][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[17][0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[17][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[17][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[17][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[17][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[17][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[16][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[17][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[16][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[16][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[16][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[15][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[16][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[15][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[15][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[15][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[14][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|__ALT_INV__delay_signals[15][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[14][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[14][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[14][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[14][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[14][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[14][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[14][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[14][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[14][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[13][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[14][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[13][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[13][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[13][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[12][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[13][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[12][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[12][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[12][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[11][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[12][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[11][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[11][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[11][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[10][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[11][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[10][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[10][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[10][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[9][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[10][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[9][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[9][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[9][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[8][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[9][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[8][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[8][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[8][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[7][0]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|__ALT_INV__delay_signals[8][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[7][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[7][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[7][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[7][0]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[7][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[7][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[7][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[7][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[7][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[6][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[7][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[6][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[6][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[6][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[5][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[6][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[5][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[5][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[5][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[4][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[5][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[4][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[4][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[4][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[3][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[4][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[3][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[3][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[3][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[3][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[0]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[0]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[0]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[0]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[0]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[0]~DUPLICATE_I .created_from = "Q(redist78_replace_rdcnt_i[0])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[0]~0_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[0]~0_I .lut_mask = "FFFFFFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[0]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[1] ), .combout(\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~DUPLICATE_I .created_from = "Q(redist78_replace_rdreg_q[1])"; dffeas \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[2] )); defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~DUPLICATE ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[3] )); defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[4]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[4] ), .combout(\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[4]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[4]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[4] )); defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "AAAAAAAAAAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[1] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[2] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~DUPLICATE ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[4] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist130_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_0,portadatain_unconnected_wire_1,portadatain_unconnected_wire_2,portadatain_unconnected_wire_3,portadatain_unconnected_wire_4,portadatain_unconnected_wire_5,portadatain_unconnected_wire_6,portadatain_unconnected_wire_7, portadatain_unconnected_wire_8,portadatain_unconnected_wire_9,portadatain_unconnected_wire_10,portadatain_unconnected_wire_11,portadatain_unconnected_wire_12,portadatain_unconnected_wire_13,portadatain_unconnected_wire_14,portadatain_unconnected_wire_15, portadatain_unconnected_wire_16,portadatain_unconnected_wire_17,portadatain_unconnected_wire_18,\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|delay_signals[0][0] }), .portaaddr({portaaddr_unconnected_wire_19,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~DUPLICATE , \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_20,\fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_depth = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .last_address = 22; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist130_outputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist130_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist130_outputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist130_outputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist130_outputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist118_sticky_ena_q[0]~feeder_I ( .combout(\fp_pow_0002:fp_pow_inst|redist118_sticky_ena_q[0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist118_sticky_ena_q[0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist118_sticky_ena_q[0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist118_sticky_ena_q[0]~feeder_I .lut_mask = "FFFFFFFFFFFFFFFF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0]~0_I ( .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .combout(\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0]~0_I .lut_mask = "FFFF0000FFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist102_replace_rdcnt_i[1]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[1] )); defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist102_replace_rdcnt_i[1]~0_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[1] ), .combout(\fp_pow_0002:fp_pow_inst|redist102_replace_rdcnt_i[1]~0 )); defparam \fp_pow_0002:fp_pow_inst|redist102_replace_rdcnt_i[1]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist102_replace_rdcnt_i[1]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist102_replace_rdcnt_i[1]~0_I .lut_mask = "CC33CC33CC33CC33"; dffeas \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[1]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist102_replace_rdcnt_i[1]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[1]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[1]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[1]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[1]~DUPLICATE_I .created_from = "Q(redist77_replace_rdcnt_i[1])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add54~0_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[1]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Add54~0 )); defparam \fp_pow_0002:fp_pow_inst|Add54~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add54~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add54~0_I .lut_mask = "00000000CCCCCCCC"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[2]~0_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add54~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[2]~0 )); defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[2]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[2]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[2]~0_I .lut_mask = "3333CCCC3333CCCC"; dffeas \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[2]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[2] )); defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal25~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[2] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[3] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[4] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[1]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Equal25~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal25~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal25~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal25~0_I .lut_mask = "0000000000040004"; dffeas \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_eq~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal25~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_eq )); defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_eq~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_eq~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add54~1_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[2] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add54~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[3] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_eq ), .combout(\fp_pow_0002:fp_pow_inst|Add54~1 )); defparam \fp_pow_0002:fp_pow_inst|Add54~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add54~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add54~1_I .lut_mask = "03FC03FCFC03FC03"; dffeas \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add54~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[3] )); defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[4]~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[2] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[3] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add54~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[4] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_eq ), .combout(\fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[4]~1 )); defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[4]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[4]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[4]~1_I .lut_mask = "01FE01FE37C837C8"; dffeas \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[4]~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[4] )); defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal24~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[4] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[2] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[3] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[1]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Equal24~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal24~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal24~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal24~0_I .lut_mask = "0000000010001000"; dffeas \fp_pow_0002:fp_pow_inst|redist77_cmpReg_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal24~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist77_cmpReg_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist77_cmpReg_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist77_cmpReg_q[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist118_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist118_sticky_ena_q[0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|redist77_cmpReg_q[0] ), .q(\fp_pow_0002:fp_pow_inst|redist118_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist118_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist118_sticky_ena_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist131_sticky_ena_q[0]~feeder_I ( .combout(\fp_pow_0002:fp_pow_inst|redist131_sticky_ena_q[0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist131_sticky_ena_q[0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist131_sticky_ena_q[0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist131_sticky_ena_q[0]~feeder_I .lut_mask = "FFFFFFFFFFFFFFFF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[0]~3_I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[0] ), .combout(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[0]~3 )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[0]~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[0]~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[0]~3_I .lut_mask = "FF00FF00FF00FF00"; dffeas \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[0]~3 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_eq ), .q(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[0] )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add17~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_eq ), .q(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[1] )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add17~0_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[1] ), .combout(\fp_pow_0002:fp_pow_inst|Add17~0 )); defparam \fp_pow_0002:fp_pow_inst|Add17~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add17~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add17~0_I .lut_mask = "CC33CC33CC33CC33"; dffeas \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[1]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add17~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_eq ), .q(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[1]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[1]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[1]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[1]~DUPLICATE_I .created_from = "Q(redist131_replace_rdcnt_i[1])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_eq ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[2] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[1]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i~0 )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i~0_I .lut_mask = "55AA55AADD22DD22"; dffeas \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[2] )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4]~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[3] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_eq ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[2] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[4] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[1]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4]~2 )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4]~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4]~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4]~2_I .lut_mask = "0101FEFE0501FAFE"; dffeas \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4]~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4] )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[2]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[2]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[2]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[2]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[2]~DUPLICATE_I .created_from = "Q(redist131_replace_rdcnt_i[2])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal8~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[3] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[4] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[2]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[1]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Equal8~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal8~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal8~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal8~0_I .lut_mask = "0000000010001000"; dffeas \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_eq~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal8~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_eq )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_eq~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_eq~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[3]~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_eq ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[3] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[3]~1 )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[3]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[3]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[3]~1_I .lut_mask = "00FF00FF5DA25DA2"; dffeas \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[3]~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[3] )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal7~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[3] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[4] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[1]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Equal7~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal7~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal7~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal7~0_I .lut_mask = "0000000001000100"; dffeas \fp_pow_0002:fp_pow_inst|redist131_cmpReg_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal7~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist131_cmpReg_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist131_cmpReg_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist131_cmpReg_q[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist131_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist131_sticky_ena_q[0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|redist131_cmpReg_q[0] ), .q(\fp_pow_0002:fp_pow_inst|redist131_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist131_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist131_sticky_ena_q[0]~I .is_wysiwyg = "true"; assign \b[23]~input0 = b[23]; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0]~0_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[0] ), .combout(\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0]~0_I .lut_mask = "F0F0F0F0F0F0F0F0"; dffeas \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[1]~DUPLICATE ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[3] ), .combout(\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4]~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4]~DUPLICATE_I .created_from = "Q(redist131_replace_rdcnt_i[4])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[4]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~DUPLICATE_I .created_from = "Q(redist131_replace_rdreg_q[4])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[0]~0_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[0] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "F0F0F0F0F0F0F0F0"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[1] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[1] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[2]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[2]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[2]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[2] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[3] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[3] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[4] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist131_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_21,portadatain_unconnected_wire_22,portadatain_unconnected_wire_23,portadatain_unconnected_wire_24,portadatain_unconnected_wire_25,portadatain_unconnected_wire_26,portadatain_unconnected_wire_27,portadatain_unconnected_wire_28, portadatain_unconnected_wire_29,portadatain_unconnected_wire_30,portadatain_unconnected_wire_31,portadatain_unconnected_wire_32,portadatain_unconnected_wire_33,portadatain_unconnected_wire_34,portadatain_unconnected_wire_35,portadatain_unconnected_wire_36, portadatain_unconnected_wire_37,portadatain_unconnected_wire_38,portadatain_unconnected_wire_39,\b[23]~input0 }), .portaaddr({portaaddr_unconnected_wire_40,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_41,\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0 .logical_ram_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][0]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][0]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; assign \b[26]~input0 = b[26]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist131_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_42,portadatain_unconnected_wire_43,portadatain_unconnected_wire_44,portadatain_unconnected_wire_45,portadatain_unconnected_wire_46,portadatain_unconnected_wire_47,portadatain_unconnected_wire_48,portadatain_unconnected_wire_49, portadatain_unconnected_wire_50,portadatain_unconnected_wire_51,portadatain_unconnected_wire_52,portadatain_unconnected_wire_53,portadatain_unconnected_wire_54,portadatain_unconnected_wire_55,portadatain_unconnected_wire_56,portadatain_unconnected_wire_57, portadatain_unconnected_wire_58,portadatain_unconnected_wire_59,portadatain_unconnected_wire_60,\b[26]~input0 }), .portaaddr({portaaddr_unconnected_wire_61,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_62,\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[3] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3 .logical_ram_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3 .first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama3 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][3]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|__ALT_INV__dataout_reg[3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][3]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][3]~I .is_wysiwyg = "true"; assign \b[28]~input0 = b[28]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist131_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_63,portadatain_unconnected_wire_64,portadatain_unconnected_wire_65,portadatain_unconnected_wire_66,portadatain_unconnected_wire_67,portadatain_unconnected_wire_68,portadatain_unconnected_wire_69,portadatain_unconnected_wire_70, portadatain_unconnected_wire_71,portadatain_unconnected_wire_72,portadatain_unconnected_wire_73,portadatain_unconnected_wire_74,portadatain_unconnected_wire_75,portadatain_unconnected_wire_76,portadatain_unconnected_wire_77,portadatain_unconnected_wire_78, portadatain_unconnected_wire_79,portadatain_unconnected_wire_80,portadatain_unconnected_wire_81,\b[28]~input0 }), .portaaddr({portaaddr_unconnected_wire_82,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_83,\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[5] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5 .logical_ram_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5 .first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama5 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][5]~I .is_wysiwyg = "true"; assign \b[30]~input0 = b[30]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist131_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_84,portadatain_unconnected_wire_85,portadatain_unconnected_wire_86,portadatain_unconnected_wire_87,portadatain_unconnected_wire_88,portadatain_unconnected_wire_89,portadatain_unconnected_wire_90,portadatain_unconnected_wire_91, portadatain_unconnected_wire_92,portadatain_unconnected_wire_93,portadatain_unconnected_wire_94,portadatain_unconnected_wire_95,portadatain_unconnected_wire_96,portadatain_unconnected_wire_97,portadatain_unconnected_wire_98,portadatain_unconnected_wire_99, portadatain_unconnected_wire_100,portadatain_unconnected_wire_101,portadatain_unconnected_wire_102,\b[30]~input0 }), .portaaddr({portaaddr_unconnected_wire_103,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_104,\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[7] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7 .logical_ram_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7 .first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama7 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][7]~I .is_wysiwyg = "true"; assign \b[27]~input0 = b[27]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist131_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_105,portadatain_unconnected_wire_106,portadatain_unconnected_wire_107,portadatain_unconnected_wire_108,portadatain_unconnected_wire_109,portadatain_unconnected_wire_110,portadatain_unconnected_wire_111,portadatain_unconnected_wire_112, portadatain_unconnected_wire_113,portadatain_unconnected_wire_114,portadatain_unconnected_wire_115,portadatain_unconnected_wire_116,portadatain_unconnected_wire_117,portadatain_unconnected_wire_118,portadatain_unconnected_wire_119,portadatain_unconnected_wire_120, portadatain_unconnected_wire_121,portadatain_unconnected_wire_122,portadatain_unconnected_wire_123,\b[27]~input0 }), .portaaddr({portaaddr_unconnected_wire_124,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_125,\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[4] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4 .logical_ram_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4 .first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama4 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][4]~I .is_wysiwyg = "true"; assign \b[29]~input0 = b[29]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist131_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_126,portadatain_unconnected_wire_127,portadatain_unconnected_wire_128,portadatain_unconnected_wire_129,portadatain_unconnected_wire_130,portadatain_unconnected_wire_131,portadatain_unconnected_wire_132,portadatain_unconnected_wire_133, portadatain_unconnected_wire_134,portadatain_unconnected_wire_135,portadatain_unconnected_wire_136,portadatain_unconnected_wire_137,portadatain_unconnected_wire_138,portadatain_unconnected_wire_139,portadatain_unconnected_wire_140,portadatain_unconnected_wire_141, portadatain_unconnected_wire_142,portadatain_unconnected_wire_143,portadatain_unconnected_wire_144,\b[29]~input0 }), .portaaddr({portaaddr_unconnected_wire_145,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_146,\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[6] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6 .logical_ram_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6 .first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama6 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal26~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][7] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Equal26~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal26~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal26~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal26~0_I .lut_mask = "0000000000050005"; assign \b[24]~input0 = b[24]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist131_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_147,portadatain_unconnected_wire_148,portadatain_unconnected_wire_149,portadatain_unconnected_wire_150,portadatain_unconnected_wire_151,portadatain_unconnected_wire_152,portadatain_unconnected_wire_153,portadatain_unconnected_wire_154, portadatain_unconnected_wire_155,portadatain_unconnected_wire_156,portadatain_unconnected_wire_157,portadatain_unconnected_wire_158,portadatain_unconnected_wire_159,portadatain_unconnected_wire_160,portadatain_unconnected_wire_161,portadatain_unconnected_wire_162, portadatain_unconnected_wire_163,portadatain_unconnected_wire_164,portadatain_unconnected_wire_165,\b[24]~input0 }), .portaaddr({portaaddr_unconnected_wire_166,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_167,\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[1] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1 .logical_ram_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1 .first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama1 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][1]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|__ALT_INV__dataout_reg[1] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][1]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][1]~I .is_wysiwyg = "true"; assign \b[25]~input0 = b[25]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist131_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_168,portadatain_unconnected_wire_169,portadatain_unconnected_wire_170,portadatain_unconnected_wire_171,portadatain_unconnected_wire_172,portadatain_unconnected_wire_173,portadatain_unconnected_wire_174,portadatain_unconnected_wire_175, portadatain_unconnected_wire_176,portadatain_unconnected_wire_177,portadatain_unconnected_wire_178,portadatain_unconnected_wire_179,portadatain_unconnected_wire_180,portadatain_unconnected_wire_181,portadatain_unconnected_wire_182,portadatain_unconnected_wire_183, portadatain_unconnected_wire_184,portadatain_unconnected_wire_185,portadatain_unconnected_wire_186,\b[25]~input0 }), .portaaddr({portaaddr_unconnected_wire_187,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_188,\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|dataout_reg[2] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2 .logical_ram_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2 .first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|lutrama2 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][2]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|altera_syncram:redist131_replace_mem_dmem|altera_syncram_meg3:auto_generated|altsyncram_hnb4:altsyncram1|__ALT_INV__dataout_reg[2] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][2]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal26~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal26~0 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Equal26~1 )); defparam \fp_pow_0002:fp_pow_inst|Equal26~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal26~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal26~1_I .lut_mask = "0000000000010001"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:expXIsMax_uid42_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal26~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:expXIsMax_uid42_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expXIsMax_uid42_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expXIsMax_uid42_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[3][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:expXIsMax_uid42_fpPowrTest_delay|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[3][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[3][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[3][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[2][0]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist120|__ALT_INV__delay_signals[3][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[2][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[2][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[2][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[2][0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[2][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist120|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0]~feeder_I ( .combout(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0]~feeder_I .lut_mask = "FFFFFFFFFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|redist131_cmpReg_q[0] ), .q(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0]~I .is_wysiwyg = "true"; assign \b[22]~input0 = b[22]; dffeas \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4] )); defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0]~0_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[0] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "F0F0F0F0F0F0F0F0"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[1] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist131_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[3] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist131_replace_rdcnt_i[4] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_189,portadatain_unconnected_wire_190,portadatain_unconnected_wire_191,portadatain_unconnected_wire_192,portadatain_unconnected_wire_193,portadatain_unconnected_wire_194,portadatain_unconnected_wire_195,portadatain_unconnected_wire_196, portadatain_unconnected_wire_197,portadatain_unconnected_wire_198,portadatain_unconnected_wire_199,portadatain_unconnected_wire_200,portadatain_unconnected_wire_201,portadatain_unconnected_wire_202,portadatain_unconnected_wire_203,portadatain_unconnected_wire_204, portadatain_unconnected_wire_205,portadatain_unconnected_wire_206,portadatain_unconnected_wire_207,\b[22]~input0 }), .portaaddr({portaaddr_unconnected_wire_208,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_209,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[22] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22 .first_bit_number = 22; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama22 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[22] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][22]~I .is_wysiwyg = "true"; assign \b[21]~input0 = b[21]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_210,portadatain_unconnected_wire_211,portadatain_unconnected_wire_212,portadatain_unconnected_wire_213,portadatain_unconnected_wire_214,portadatain_unconnected_wire_215,portadatain_unconnected_wire_216,portadatain_unconnected_wire_217, portadatain_unconnected_wire_218,portadatain_unconnected_wire_219,portadatain_unconnected_wire_220,portadatain_unconnected_wire_221,portadatain_unconnected_wire_222,portadatain_unconnected_wire_223,portadatain_unconnected_wire_224,portadatain_unconnected_wire_225, portadatain_unconnected_wire_226,portadatain_unconnected_wire_227,portadatain_unconnected_wire_228,\b[21]~input0 }), .portaaddr({portaaddr_unconnected_wire_229,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_230,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[21] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21 .first_bit_number = 21; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama21 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][21]~I .is_wysiwyg = "true"; assign \b[20]~input0 = b[20]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_231,portadatain_unconnected_wire_232,portadatain_unconnected_wire_233,portadatain_unconnected_wire_234,portadatain_unconnected_wire_235,portadatain_unconnected_wire_236,portadatain_unconnected_wire_237,portadatain_unconnected_wire_238, portadatain_unconnected_wire_239,portadatain_unconnected_wire_240,portadatain_unconnected_wire_241,portadatain_unconnected_wire_242,portadatain_unconnected_wire_243,portadatain_unconnected_wire_244,portadatain_unconnected_wire_245,portadatain_unconnected_wire_246, portadatain_unconnected_wire_247,portadatain_unconnected_wire_248,portadatain_unconnected_wire_249,\b[20]~input0 }), .portaaddr({portaaddr_unconnected_wire_250,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_251,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[20] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20 .first_bit_number = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama20 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[20] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][20]~I .is_wysiwyg = "true"; assign \b[19]~input0 = b[19]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_252,portadatain_unconnected_wire_253,portadatain_unconnected_wire_254,portadatain_unconnected_wire_255,portadatain_unconnected_wire_256,portadatain_unconnected_wire_257,portadatain_unconnected_wire_258,portadatain_unconnected_wire_259, portadatain_unconnected_wire_260,portadatain_unconnected_wire_261,portadatain_unconnected_wire_262,portadatain_unconnected_wire_263,portadatain_unconnected_wire_264,portadatain_unconnected_wire_265,portadatain_unconnected_wire_266,portadatain_unconnected_wire_267, portadatain_unconnected_wire_268,portadatain_unconnected_wire_269,portadatain_unconnected_wire_270,\b[19]~input0 }), .portaaddr({portaaddr_unconnected_wire_271,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_272,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[19] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19 .first_bit_number = 19; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama19 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][19]~I .is_wysiwyg = "true"; assign \b[18]~input0 = b[18]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_273,portadatain_unconnected_wire_274,portadatain_unconnected_wire_275,portadatain_unconnected_wire_276,portadatain_unconnected_wire_277,portadatain_unconnected_wire_278,portadatain_unconnected_wire_279,portadatain_unconnected_wire_280, portadatain_unconnected_wire_281,portadatain_unconnected_wire_282,portadatain_unconnected_wire_283,portadatain_unconnected_wire_284,portadatain_unconnected_wire_285,portadatain_unconnected_wire_286,portadatain_unconnected_wire_287,portadatain_unconnected_wire_288, portadatain_unconnected_wire_289,portadatain_unconnected_wire_290,portadatain_unconnected_wire_291,\b[18]~input0 }), .portaaddr({portaaddr_unconnected_wire_292,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_293,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[18] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18 .first_bit_number = 18; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama18 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][18]~I .is_wysiwyg = "true"; assign \b[17]~input0 = b[17]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_294,portadatain_unconnected_wire_295,portadatain_unconnected_wire_296,portadatain_unconnected_wire_297,portadatain_unconnected_wire_298,portadatain_unconnected_wire_299,portadatain_unconnected_wire_300,portadatain_unconnected_wire_301, portadatain_unconnected_wire_302,portadatain_unconnected_wire_303,portadatain_unconnected_wire_304,portadatain_unconnected_wire_305,portadatain_unconnected_wire_306,portadatain_unconnected_wire_307,portadatain_unconnected_wire_308,portadatain_unconnected_wire_309, portadatain_unconnected_wire_310,portadatain_unconnected_wire_311,portadatain_unconnected_wire_312,\b[17]~input0 }), .portaaddr({portaaddr_unconnected_wire_313,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_314,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[17] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17 .first_bit_number = 17; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama17 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][17]~I .is_wysiwyg = "true"; assign \b[16]~input0 = b[16]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_315,portadatain_unconnected_wire_316,portadatain_unconnected_wire_317,portadatain_unconnected_wire_318,portadatain_unconnected_wire_319,portadatain_unconnected_wire_320,portadatain_unconnected_wire_321,portadatain_unconnected_wire_322, portadatain_unconnected_wire_323,portadatain_unconnected_wire_324,portadatain_unconnected_wire_325,portadatain_unconnected_wire_326,portadatain_unconnected_wire_327,portadatain_unconnected_wire_328,portadatain_unconnected_wire_329,portadatain_unconnected_wire_330, portadatain_unconnected_wire_331,portadatain_unconnected_wire_332,portadatain_unconnected_wire_333,\b[16]~input0 }), .portaaddr({portaaddr_unconnected_wire_334,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_335,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[16] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16 .first_bit_number = 16; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama16 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][16]~I .is_wysiwyg = "true"; assign \b[15]~input0 = b[15]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_336,portadatain_unconnected_wire_337,portadatain_unconnected_wire_338,portadatain_unconnected_wire_339,portadatain_unconnected_wire_340,portadatain_unconnected_wire_341,portadatain_unconnected_wire_342,portadatain_unconnected_wire_343, portadatain_unconnected_wire_344,portadatain_unconnected_wire_345,portadatain_unconnected_wire_346,portadatain_unconnected_wire_347,portadatain_unconnected_wire_348,portadatain_unconnected_wire_349,portadatain_unconnected_wire_350,portadatain_unconnected_wire_351, portadatain_unconnected_wire_352,portadatain_unconnected_wire_353,portadatain_unconnected_wire_354,\b[15]~input0 }), .portaaddr({portaaddr_unconnected_wire_355,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_356,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[15] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15 .first_bit_number = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama15 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][15]~I .is_wysiwyg = "true"; assign \b[14]~input0 = b[14]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_357,portadatain_unconnected_wire_358,portadatain_unconnected_wire_359,portadatain_unconnected_wire_360,portadatain_unconnected_wire_361,portadatain_unconnected_wire_362,portadatain_unconnected_wire_363,portadatain_unconnected_wire_364, portadatain_unconnected_wire_365,portadatain_unconnected_wire_366,portadatain_unconnected_wire_367,portadatain_unconnected_wire_368,portadatain_unconnected_wire_369,portadatain_unconnected_wire_370,portadatain_unconnected_wire_371,portadatain_unconnected_wire_372, portadatain_unconnected_wire_373,portadatain_unconnected_wire_374,portadatain_unconnected_wire_375,\b[14]~input0 }), .portaaddr({portaaddr_unconnected_wire_376,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_377,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[14] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14 .first_bit_number = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama14 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][14]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[14] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][14]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][14]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][14]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][14]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][14]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][14]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][14]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][14]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][14]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][14]~DUPLICATE_I .created_from = "Q(delay_signals[0][14])"; assign \b[13]~input0 = b[13]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_378,portadatain_unconnected_wire_379,portadatain_unconnected_wire_380,portadatain_unconnected_wire_381,portadatain_unconnected_wire_382,portadatain_unconnected_wire_383,portadatain_unconnected_wire_384,portadatain_unconnected_wire_385, portadatain_unconnected_wire_386,portadatain_unconnected_wire_387,portadatain_unconnected_wire_388,portadatain_unconnected_wire_389,portadatain_unconnected_wire_390,portadatain_unconnected_wire_391,portadatain_unconnected_wire_392,portadatain_unconnected_wire_393, portadatain_unconnected_wire_394,portadatain_unconnected_wire_395,portadatain_unconnected_wire_396,\b[13]~input0 }), .portaaddr({portaaddr_unconnected_wire_397,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_398,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[13] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13 .first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama13 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][13]~I .is_wysiwyg = "true"; assign \b[12]~input0 = b[12]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_399,portadatain_unconnected_wire_400,portadatain_unconnected_wire_401,portadatain_unconnected_wire_402,portadatain_unconnected_wire_403,portadatain_unconnected_wire_404,portadatain_unconnected_wire_405,portadatain_unconnected_wire_406, portadatain_unconnected_wire_407,portadatain_unconnected_wire_408,portadatain_unconnected_wire_409,portadatain_unconnected_wire_410,portadatain_unconnected_wire_411,portadatain_unconnected_wire_412,portadatain_unconnected_wire_413,portadatain_unconnected_wire_414, portadatain_unconnected_wire_415,portadatain_unconnected_wire_416,portadatain_unconnected_wire_417,\b[12]~input0 }), .portaaddr({portaaddr_unconnected_wire_418,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_419,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[12] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12 .first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama12 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][12]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[12] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][12]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][12]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][12]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][12]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][12]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][12]~I .is_wysiwyg = "true"; assign \b[11]~input0 = b[11]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_420,portadatain_unconnected_wire_421,portadatain_unconnected_wire_422,portadatain_unconnected_wire_423,portadatain_unconnected_wire_424,portadatain_unconnected_wire_425,portadatain_unconnected_wire_426,portadatain_unconnected_wire_427, portadatain_unconnected_wire_428,portadatain_unconnected_wire_429,portadatain_unconnected_wire_430,portadatain_unconnected_wire_431,portadatain_unconnected_wire_432,portadatain_unconnected_wire_433,portadatain_unconnected_wire_434,portadatain_unconnected_wire_435, portadatain_unconnected_wire_436,portadatain_unconnected_wire_437,portadatain_unconnected_wire_438,\b[11]~input0 }), .portaaddr({portaaddr_unconnected_wire_439,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_440,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[11] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11 .first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama11 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][11]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[11] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][11]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][11]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][11]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][11]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][11]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][11]~I .is_wysiwyg = "true"; assign \b[10]~input0 = b[10]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_441,portadatain_unconnected_wire_442,portadatain_unconnected_wire_443,portadatain_unconnected_wire_444,portadatain_unconnected_wire_445,portadatain_unconnected_wire_446,portadatain_unconnected_wire_447,portadatain_unconnected_wire_448, portadatain_unconnected_wire_449,portadatain_unconnected_wire_450,portadatain_unconnected_wire_451,portadatain_unconnected_wire_452,portadatain_unconnected_wire_453,portadatain_unconnected_wire_454,portadatain_unconnected_wire_455,portadatain_unconnected_wire_456, portadatain_unconnected_wire_457,portadatain_unconnected_wire_458,portadatain_unconnected_wire_459,\b[10]~input0 }), .portaaddr({portaaddr_unconnected_wire_460,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_461,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[10] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10 .first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama10 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][10]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[10] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][10]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][10]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][10]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][10]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][10]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][10]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][10]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][10]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][10]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][10]~DUPLICATE_I .created_from = "Q(delay_signals[0][10])"; assign \b[9]~input0 = b[9]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_462,portadatain_unconnected_wire_463,portadatain_unconnected_wire_464,portadatain_unconnected_wire_465,portadatain_unconnected_wire_466,portadatain_unconnected_wire_467,portadatain_unconnected_wire_468,portadatain_unconnected_wire_469, portadatain_unconnected_wire_470,portadatain_unconnected_wire_471,portadatain_unconnected_wire_472,portadatain_unconnected_wire_473,portadatain_unconnected_wire_474,portadatain_unconnected_wire_475,portadatain_unconnected_wire_476,portadatain_unconnected_wire_477, portadatain_unconnected_wire_478,portadatain_unconnected_wire_479,portadatain_unconnected_wire_480,\b[9]~input0 }), .portaaddr({portaaddr_unconnected_wire_481,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_482,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[9] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9 .first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama9 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][9]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[9] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][9]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][9]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][9]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][9]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][9]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][9]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][9]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][9]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][9]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][9]~DUPLICATE_I .created_from = "Q(delay_signals[0][9])"; assign \b[8]~input0 = b[8]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_483,portadatain_unconnected_wire_484,portadatain_unconnected_wire_485,portadatain_unconnected_wire_486,portadatain_unconnected_wire_487,portadatain_unconnected_wire_488,portadatain_unconnected_wire_489,portadatain_unconnected_wire_490, portadatain_unconnected_wire_491,portadatain_unconnected_wire_492,portadatain_unconnected_wire_493,portadatain_unconnected_wire_494,portadatain_unconnected_wire_495,portadatain_unconnected_wire_496,portadatain_unconnected_wire_497,portadatain_unconnected_wire_498, portadatain_unconnected_wire_499,portadatain_unconnected_wire_500,portadatain_unconnected_wire_501,\b[8]~input0 }), .portaaddr({portaaddr_unconnected_wire_502,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_503,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[8] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8 .first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama8 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][8]~I .is_wysiwyg = "true"; assign \b[7]~input0 = b[7]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_504,portadatain_unconnected_wire_505,portadatain_unconnected_wire_506,portadatain_unconnected_wire_507,portadatain_unconnected_wire_508,portadatain_unconnected_wire_509,portadatain_unconnected_wire_510,portadatain_unconnected_wire_511, portadatain_unconnected_wire_512,portadatain_unconnected_wire_513,portadatain_unconnected_wire_514,portadatain_unconnected_wire_515,portadatain_unconnected_wire_516,portadatain_unconnected_wire_517,portadatain_unconnected_wire_518,portadatain_unconnected_wire_519, portadatain_unconnected_wire_520,portadatain_unconnected_wire_521,portadatain_unconnected_wire_522,\b[7]~input0 }), .portaaddr({portaaddr_unconnected_wire_523,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_524,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[7] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7 .first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama7 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][7]~I .is_wysiwyg = "true"; assign \b[6]~input0 = b[6]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_525,portadatain_unconnected_wire_526,portadatain_unconnected_wire_527,portadatain_unconnected_wire_528,portadatain_unconnected_wire_529,portadatain_unconnected_wire_530,portadatain_unconnected_wire_531,portadatain_unconnected_wire_532, portadatain_unconnected_wire_533,portadatain_unconnected_wire_534,portadatain_unconnected_wire_535,portadatain_unconnected_wire_536,portadatain_unconnected_wire_537,portadatain_unconnected_wire_538,portadatain_unconnected_wire_539,portadatain_unconnected_wire_540, portadatain_unconnected_wire_541,portadatain_unconnected_wire_542,portadatain_unconnected_wire_543,\b[6]~input0 }), .portaaddr({portaaddr_unconnected_wire_544,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_545,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[6] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6 .first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama6 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][6]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][6]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][6]~I .is_wysiwyg = "true"; assign \b[5]~input0 = b[5]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_546,portadatain_unconnected_wire_547,portadatain_unconnected_wire_548,portadatain_unconnected_wire_549,portadatain_unconnected_wire_550,portadatain_unconnected_wire_551,portadatain_unconnected_wire_552,portadatain_unconnected_wire_553, portadatain_unconnected_wire_554,portadatain_unconnected_wire_555,portadatain_unconnected_wire_556,portadatain_unconnected_wire_557,portadatain_unconnected_wire_558,portadatain_unconnected_wire_559,portadatain_unconnected_wire_560,portadatain_unconnected_wire_561, portadatain_unconnected_wire_562,portadatain_unconnected_wire_563,portadatain_unconnected_wire_564,\b[5]~input0 }), .portaaddr({portaaddr_unconnected_wire_565,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_566,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[5] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5 .first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama5 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][5]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][5]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][5]~I .is_wysiwyg = "true"; assign \b[4]~input0 = b[4]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_567,portadatain_unconnected_wire_568,portadatain_unconnected_wire_569,portadatain_unconnected_wire_570,portadatain_unconnected_wire_571,portadatain_unconnected_wire_572,portadatain_unconnected_wire_573,portadatain_unconnected_wire_574, portadatain_unconnected_wire_575,portadatain_unconnected_wire_576,portadatain_unconnected_wire_577,portadatain_unconnected_wire_578,portadatain_unconnected_wire_579,portadatain_unconnected_wire_580,portadatain_unconnected_wire_581,portadatain_unconnected_wire_582, portadatain_unconnected_wire_583,portadatain_unconnected_wire_584,portadatain_unconnected_wire_585,\b[4]~input0 }), .portaaddr({portaaddr_unconnected_wire_586,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_587,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[4] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4 .first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama4 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][4]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[4] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][4]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][4]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][4]~I .is_wysiwyg = "true"; assign \b[3]~input0 = b[3]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_588,portadatain_unconnected_wire_589,portadatain_unconnected_wire_590,portadatain_unconnected_wire_591,portadatain_unconnected_wire_592,portadatain_unconnected_wire_593,portadatain_unconnected_wire_594,portadatain_unconnected_wire_595, portadatain_unconnected_wire_596,portadatain_unconnected_wire_597,portadatain_unconnected_wire_598,portadatain_unconnected_wire_599,portadatain_unconnected_wire_600,portadatain_unconnected_wire_601,portadatain_unconnected_wire_602,portadatain_unconnected_wire_603, portadatain_unconnected_wire_604,portadatain_unconnected_wire_605,portadatain_unconnected_wire_606,\b[3]~input0 }), .portaaddr({portaaddr_unconnected_wire_607,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_608,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[3] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3 .first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama3 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][3]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][3]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][3]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][3]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][3]~DUPLICATE_I .created_from = "Q(delay_signals[0][3])"; assign \b[2]~input0 = b[2]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_609,portadatain_unconnected_wire_610,portadatain_unconnected_wire_611,portadatain_unconnected_wire_612,portadatain_unconnected_wire_613,portadatain_unconnected_wire_614,portadatain_unconnected_wire_615,portadatain_unconnected_wire_616, portadatain_unconnected_wire_617,portadatain_unconnected_wire_618,portadatain_unconnected_wire_619,portadatain_unconnected_wire_620,portadatain_unconnected_wire_621,portadatain_unconnected_wire_622,portadatain_unconnected_wire_623,portadatain_unconnected_wire_624, portadatain_unconnected_wire_625,portadatain_unconnected_wire_626,portadatain_unconnected_wire_627,\b[2]~input0 }), .portaaddr({portaaddr_unconnected_wire_628,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_629,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[2] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2 .first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama2 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][2]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[2] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][2]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][2]~I .is_wysiwyg = "true"; assign \b[1]~input0 = b[1]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_630,portadatain_unconnected_wire_631,portadatain_unconnected_wire_632,portadatain_unconnected_wire_633,portadatain_unconnected_wire_634,portadatain_unconnected_wire_635,portadatain_unconnected_wire_636,portadatain_unconnected_wire_637, portadatain_unconnected_wire_638,portadatain_unconnected_wire_639,portadatain_unconnected_wire_640,portadatain_unconnected_wire_641,portadatain_unconnected_wire_642,portadatain_unconnected_wire_643,portadatain_unconnected_wire_644,portadatain_unconnected_wire_645, portadatain_unconnected_wire_646,portadatain_unconnected_wire_647,portadatain_unconnected_wire_648,\b[1]~input0 }), .portaaddr({portaaddr_unconnected_wire_649,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_650,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[1] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1 .first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama1 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[1] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][1]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][1]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][1]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][1]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][1]~DUPLICATE_I .created_from = "Q(delay_signals[0][1])"; assign \b[0]~input0 = b[0]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist132_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_651,portadatain_unconnected_wire_652,portadatain_unconnected_wire_653,portadatain_unconnected_wire_654,portadatain_unconnected_wire_655,portadatain_unconnected_wire_656,portadatain_unconnected_wire_657,portadatain_unconnected_wire_658, portadatain_unconnected_wire_659,portadatain_unconnected_wire_660,portadatain_unconnected_wire_661,portadatain_unconnected_wire_662,portadatain_unconnected_wire_663,portadatain_unconnected_wire_664,portadatain_unconnected_wire_665,portadatain_unconnected_wire_666, portadatain_unconnected_wire_667,portadatain_unconnected_wire_668,portadatain_unconnected_wire_669,\b[0]~input0 }), .portaaddr({portaaddr_unconnected_wire_670,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist131_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_671,\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0 .logical_ram_depth = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0 .last_address = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~94_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][0] ), .cin(gnd), .cout(\fp_pow_0002:fp_pow_inst|Add55~94 )); defparam \fp_pow_0002:fp_pow_inst|Add55~94_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~94_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~94_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~90_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .cin(\fp_pow_0002:fp_pow_inst|Add55~94 ), .cout(\fp_pow_0002:fp_pow_inst|Add55~90 )); defparam \fp_pow_0002:fp_pow_inst|Add55~90_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~90_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~90_I .lut_mask = "0000000000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~86_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][2] ), .cin(\fp_pow_0002:fp_pow_inst|Add55~90 ), .cout(\fp_pow_0002:fp_pow_inst|Add55~86 )); defparam \fp_pow_0002:fp_pow_inst|Add55~86_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~86_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~86_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~82_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][3]~DUPLICATE ), .cin(\fp_pow_0002:fp_pow_inst|Add55~86 ), .cout(\fp_pow_0002:fp_pow_inst|Add55~82 )); defparam \fp_pow_0002:fp_pow_inst|Add55~82_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~82_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~82_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~78_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][4] ), .cin(\fp_pow_0002:fp_pow_inst|Add55~82 ), .cout(\fp_pow_0002:fp_pow_inst|Add55~78 )); defparam \fp_pow_0002:fp_pow_inst|Add55~78_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~78_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~78_I .lut_mask = "0000000000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~74_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add55~78 ), .cout(\fp_pow_0002:fp_pow_inst|Add55~74 )); defparam \fp_pow_0002:fp_pow_inst|Add55~74_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~74_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~74_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~70_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][6] ), .cin(\fp_pow_0002:fp_pow_inst|Add55~74 ), .cout(\fp_pow_0002:fp_pow_inst|Add55~70 )); defparam \fp_pow_0002:fp_pow_inst|Add55~70_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~70_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~70_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~66_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add55~70 ), .cout(\fp_pow_0002:fp_pow_inst|Add55~66 )); defparam \fp_pow_0002:fp_pow_inst|Add55~66_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~66_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~66_I .lut_mask = "0000000000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~62_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][8] ), .cin(\fp_pow_0002:fp_pow_inst|Add55~66 ), .cout(\fp_pow_0002:fp_pow_inst|Add55~62 )); defparam \fp_pow_0002:fp_pow_inst|Add55~62_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~62_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~62_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~58_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][9]~DUPLICATE ), .cin(\fp_pow_0002:fp_pow_inst|Add55~62 ), .cout(\fp_pow_0002:fp_pow_inst|Add55~58 )); defparam \fp_pow_0002:fp_pow_inst|Add55~58_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~58_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~58_I .lut_mask = "0000000000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~54_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][10]~DUPLICATE ), .cin(\fp_pow_0002:fp_pow_inst|Add55~58 ), .cout(\fp_pow_0002:fp_pow_inst|Add55~54 )); defparam \fp_pow_0002:fp_pow_inst|Add55~54_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~54_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~54_I .lut_mask = "0000000000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~50_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][11] ), .cin(\fp_pow_0002:fp_pow_inst|Add55~54 ), .cout(\fp_pow_0002:fp_pow_inst|Add55~50 )); defparam \fp_pow_0002:fp_pow_inst|Add55~50_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~50_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~50_I .lut_mask = "0000000000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~46_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][12] ), .cin(\fp_pow_0002:fp_pow_inst|Add55~50 ), .cout(\fp_pow_0002:fp_pow_inst|Add55~46 )); defparam \fp_pow_0002:fp_pow_inst|Add55~46_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~46_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~46_I .lut_mask = "0000000000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~42_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][13] ), .cin(\fp_pow_0002:fp_pow_inst|Add55~46 ), .cout(\fp_pow_0002:fp_pow_inst|Add55~42 )); defparam \fp_pow_0002:fp_pow_inst|Add55~42_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~42_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~42_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~38_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][14]~DUPLICATE ), .cin(\fp_pow_0002:fp_pow_inst|Add55~42 ), .cout(\fp_pow_0002:fp_pow_inst|Add55~38 )); defparam \fp_pow_0002:fp_pow_inst|Add55~38_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~38_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~38_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~34_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][15] ), .cin(\fp_pow_0002:fp_pow_inst|Add55~38 ), .cout(\fp_pow_0002:fp_pow_inst|Add55~34 )); defparam \fp_pow_0002:fp_pow_inst|Add55~34_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~34_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~34_I .lut_mask = "00000000000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~30_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][16] ), .cin(\fp_pow_0002:fp_pow_inst|Add55~34 ), .cout(\fp_pow_0002:fp_pow_inst|Add55~30 )); defparam \fp_pow_0002:fp_pow_inst|Add55~30_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~30_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~30_I .lut_mask = "00000000000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~26_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][17] ), .cin(\fp_pow_0002:fp_pow_inst|Add55~30 ), .cout(\fp_pow_0002:fp_pow_inst|Add55~26 )); defparam \fp_pow_0002:fp_pow_inst|Add55~26_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~26_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~26_I .lut_mask = "00000000000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~22_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][18] ), .cin(\fp_pow_0002:fp_pow_inst|Add55~26 ), .cout(\fp_pow_0002:fp_pow_inst|Add55~22 )); defparam \fp_pow_0002:fp_pow_inst|Add55~22_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~22_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~22_I .lut_mask = "00000000000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~18_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][19] ), .cin(\fp_pow_0002:fp_pow_inst|Add55~22 ), .cout(\fp_pow_0002:fp_pow_inst|Add55~18 )); defparam \fp_pow_0002:fp_pow_inst|Add55~18_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~18_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~18_I .lut_mask = "00000000000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~14_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][20] ), .cin(\fp_pow_0002:fp_pow_inst|Add55~18 ), .cout(\fp_pow_0002:fp_pow_inst|Add55~14 )); defparam \fp_pow_0002:fp_pow_inst|Add55~14_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~14_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~14_I .lut_mask = "00000000000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~10_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][21] ), .cin(\fp_pow_0002:fp_pow_inst|Add55~14 ), .cout(\fp_pow_0002:fp_pow_inst|Add55~10 )); defparam \fp_pow_0002:fp_pow_inst|Add55~10_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~10_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~10_I .lut_mask = "00000000000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~6_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|__ALT_INV__delay_signals[0][22] ), .cin(\fp_pow_0002:fp_pow_inst|Add55~10 ), .cout(\fp_pow_0002:fp_pow_inst|Add55~6 )); defparam \fp_pow_0002:fp_pow_inst|Add55~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~6_I .lut_mask = "00000000000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add55~1_I ( .cin(\fp_pow_0002:fp_pow_inst|Add55~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add55~1 )); defparam \fp_pow_0002:fp_pow_inst|Add55~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add55~1_I .lut_mask = "0000FFFF0000FFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:fracXIsZero_uid45_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add55~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:fracXIsZero_uid45_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:fracXIsZero_uid45_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:fracXIsZero_uid45_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[3][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:fracXIsZero_uid45_fpPowrTest_delay|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[3][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[3][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[3][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[3][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist119|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist118_replace_mem_ia[0]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist120|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist119|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|redist118_replace_mem_ia[0] )); defparam \fp_pow_0002:fp_pow_inst|redist118_replace_mem_ia[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist118_replace_mem_ia[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist118_replace_mem_ia[0]~I .lut_mask = "0000000033333333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[1]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] )); defparam \fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[2] )); defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[3] )); defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[4] )); defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0]~0_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "FFFFFFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[1]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[1]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[1] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[3] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[3]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[3] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[4] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[4] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist118_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_672,portadatain_unconnected_wire_673,portadatain_unconnected_wire_674,portadatain_unconnected_wire_675,portadatain_unconnected_wire_676,portadatain_unconnected_wire_677,portadatain_unconnected_wire_678,portadatain_unconnected_wire_679, portadatain_unconnected_wire_680,portadatain_unconnected_wire_681,portadatain_unconnected_wire_682,portadatain_unconnected_wire_683,portadatain_unconnected_wire_684,portadatain_unconnected_wire_685,portadatain_unconnected_wire_686,portadatain_unconnected_wire_687, portadatain_unconnected_wire_688,portadatain_unconnected_wire_689,portadatain_unconnected_wire_690,\fp_pow_0002:fp_pow_inst|redist118_replace_mem_ia[0] }), .portaaddr({portaaddr_unconnected_wire_691,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_692,\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .logical_ram_depth = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .logical_ram_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .last_address = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist127_sticky_ena_q[0]~feeder_I ( .combout(\fp_pow_0002:fp_pow_inst|redist127_sticky_ena_q[0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist127_sticky_ena_q[0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist127_sticky_ena_q[0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist127_sticky_ena_q[0]~feeder_I .lut_mask = "FFFFFFFFFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist127_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist127_sticky_ena_q[0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|redist78_cmpReg_q[0] ), .q(\fp_pow_0002:fp_pow_inst|redist127_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist127_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist127_sticky_ena_q[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_eq~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal4~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_eq )); defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_eq~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_eq~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[3]~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add54~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_replace_rdcnt_eq ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_replace_rdcnt_i[3] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[3]~0 )); defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[3]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[3]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[3]~0_I .lut_mask = "05FA05FA5FA05FA0"; dffeas \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[3]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[3] )); defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal4~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_replace_rdcnt_i[2] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_replace_rdcnt_i[3] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[1]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Equal4~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal4~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal4~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal4~0_I .lut_mask = "00000000000A000A"; dffeas \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_eq~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal4~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_eq~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_eq~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_eq~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_eq~DUPLICATE_I .created_from = "Q(redist134_replace_rdcnt_eq)"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add12~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add54~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_replace_rdcnt_i[2] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_replace_rdcnt_eq~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Add12~0 )); defparam \fp_pow_0002:fp_pow_inst|Add12~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add12~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add12~0_I .lut_mask = "55AA55AAAA55AA55"; dffeas \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add12~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[2] )); defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal3~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_replace_rdcnt_i[2] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_replace_rdcnt_i[3] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[1]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Equal3~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal3~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal3~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal3~0_I .lut_mask = "0000000000880088"; dffeas \fp_pow_0002:fp_pow_inst|redist134_cmpReg_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal3~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist134_cmpReg_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist134_cmpReg_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist134_cmpReg_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist134_sticky_ena_q[0]~0_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_cmpReg_q[0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_sticky_ena_q[0] ), .combout(\fp_pow_0002:fp_pow_inst|redist134_sticky_ena_q[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|redist134_sticky_ena_q[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist134_sticky_ena_q[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist134_sticky_ena_q[0]~0_I .lut_mask = "0F0FFFFF0F0FFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist134_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist134_sticky_ena_q[0]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist134_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist134_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist134_sticky_ena_q[0]~I .is_wysiwyg = "true"; assign \a[25]~input0 = a[25]; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[2]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[2]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[2] )); defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[3]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[3]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[3]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[3]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[3]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[3]~DUPLICATE_I .created_from = "Q(redist134_replace_rdcnt_i[3])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_replace_rdcnt_i[3]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[3] )); defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[0]~0_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "CCCCCCCCCCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[1]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[1]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[1] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist134_replace_rdcnt_i[2] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[2] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist134_replace_rdcnt_i[3]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[3]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[3] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[3]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist134_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_693,portadatain_unconnected_wire_694,portadatain_unconnected_wire_695,portadatain_unconnected_wire_696,portadatain_unconnected_wire_697,portadatain_unconnected_wire_698,portadatain_unconnected_wire_699,portadatain_unconnected_wire_700, portadatain_unconnected_wire_701,portadatain_unconnected_wire_702,portadatain_unconnected_wire_703,portadatain_unconnected_wire_704,portadatain_unconnected_wire_705,portadatain_unconnected_wire_706,portadatain_unconnected_wire_707,portadatain_unconnected_wire_708, portadatain_unconnected_wire_709,portadatain_unconnected_wire_710,portadatain_unconnected_wire_711,\a[25]~input0 }), .portaaddr({portaaddr_unconnected_wire_712,portaaddr_unconnected_wire_713,\fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_714,portbaddr_unconnected_wire_715,\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[2] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2 .logical_ram_depth = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2 .logical_ram_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2 .first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2 .last_address = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama2 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][2]~I .is_wysiwyg = "true"; assign \a[24]~input0 = a[24]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist134_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_716,portadatain_unconnected_wire_717,portadatain_unconnected_wire_718,portadatain_unconnected_wire_719,portadatain_unconnected_wire_720,portadatain_unconnected_wire_721,portadatain_unconnected_wire_722,portadatain_unconnected_wire_723, portadatain_unconnected_wire_724,portadatain_unconnected_wire_725,portadatain_unconnected_wire_726,portadatain_unconnected_wire_727,portadatain_unconnected_wire_728,portadatain_unconnected_wire_729,portadatain_unconnected_wire_730,portadatain_unconnected_wire_731, portadatain_unconnected_wire_732,portadatain_unconnected_wire_733,portadatain_unconnected_wire_734,\a[24]~input0 }), .portaaddr({portaaddr_unconnected_wire_735,portaaddr_unconnected_wire_736,\fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_737,portbaddr_unconnected_wire_738,\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[1] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1 .logical_ram_depth = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1 .logical_ram_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1 .first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1 .last_address = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama1 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][1]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][1]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][1]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][1]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][1]~DUPLICATE_I .created_from = "Q(delay_signals[0][1])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][1]~I .is_wysiwyg = "true"; assign \a[29]~input0 = a[29]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist134_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_739,portadatain_unconnected_wire_740,portadatain_unconnected_wire_741,portadatain_unconnected_wire_742,portadatain_unconnected_wire_743,portadatain_unconnected_wire_744,portadatain_unconnected_wire_745,portadatain_unconnected_wire_746, portadatain_unconnected_wire_747,portadatain_unconnected_wire_748,portadatain_unconnected_wire_749,portadatain_unconnected_wire_750,portadatain_unconnected_wire_751,portadatain_unconnected_wire_752,portadatain_unconnected_wire_753,portadatain_unconnected_wire_754, portadatain_unconnected_wire_755,portadatain_unconnected_wire_756,portadatain_unconnected_wire_757,\a[29]~input0 }), .portaaddr({portaaddr_unconnected_wire_758,portaaddr_unconnected_wire_759,\fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_760,portbaddr_unconnected_wire_761,\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[6] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6 .logical_ram_depth = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6 .logical_ram_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6 .first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6 .last_address = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama6 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][6]~I .is_wysiwyg = "true"; assign \a[27]~input0 = a[27]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist134_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_762,portadatain_unconnected_wire_763,portadatain_unconnected_wire_764,portadatain_unconnected_wire_765,portadatain_unconnected_wire_766,portadatain_unconnected_wire_767,portadatain_unconnected_wire_768,portadatain_unconnected_wire_769, portadatain_unconnected_wire_770,portadatain_unconnected_wire_771,portadatain_unconnected_wire_772,portadatain_unconnected_wire_773,portadatain_unconnected_wire_774,portadatain_unconnected_wire_775,portadatain_unconnected_wire_776,portadatain_unconnected_wire_777, portadatain_unconnected_wire_778,portadatain_unconnected_wire_779,portadatain_unconnected_wire_780,\a[27]~input0 }), .portaaddr({portaaddr_unconnected_wire_781,portaaddr_unconnected_wire_782,\fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_783,portbaddr_unconnected_wire_784,\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[4] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4 .logical_ram_depth = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4 .logical_ram_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4 .first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4 .last_address = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama4 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][4]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[2][4] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][4]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][4]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][4]~I .is_wysiwyg = "true"; assign \a[30]~input0 = a[30]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist134_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_785,portadatain_unconnected_wire_786,portadatain_unconnected_wire_787,portadatain_unconnected_wire_788,portadatain_unconnected_wire_789,portadatain_unconnected_wire_790,portadatain_unconnected_wire_791,portadatain_unconnected_wire_792, portadatain_unconnected_wire_793,portadatain_unconnected_wire_794,portadatain_unconnected_wire_795,portadatain_unconnected_wire_796,portadatain_unconnected_wire_797,portadatain_unconnected_wire_798,portadatain_unconnected_wire_799,portadatain_unconnected_wire_800, portadatain_unconnected_wire_801,portadatain_unconnected_wire_802,portadatain_unconnected_wire_803,\a[30]~input0 }), .portaaddr({portaaddr_unconnected_wire_804,portaaddr_unconnected_wire_805,\fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_806,portbaddr_unconnected_wire_807,\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[7] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7 .logical_ram_depth = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7 .logical_ram_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7 .first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7 .last_address = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama7 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][7]~I .is_wysiwyg = "true"; assign \a[28]~input0 = a[28]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist134_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_808,portadatain_unconnected_wire_809,portadatain_unconnected_wire_810,portadatain_unconnected_wire_811,portadatain_unconnected_wire_812,portadatain_unconnected_wire_813,portadatain_unconnected_wire_814,portadatain_unconnected_wire_815, portadatain_unconnected_wire_816,portadatain_unconnected_wire_817,portadatain_unconnected_wire_818,portadatain_unconnected_wire_819,portadatain_unconnected_wire_820,portadatain_unconnected_wire_821,portadatain_unconnected_wire_822,portadatain_unconnected_wire_823, portadatain_unconnected_wire_824,portadatain_unconnected_wire_825,portadatain_unconnected_wire_826,\a[28]~input0 }), .portaaddr({portaaddr_unconnected_wire_827,portaaddr_unconnected_wire_828,\fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_829,portbaddr_unconnected_wire_830,\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[5] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5 .logical_ram_depth = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5 .logical_ram_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5 .first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5 .last_address = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama5 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][5]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[2][5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][5]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal6~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][6] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][7] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][5] ), .combout(\fp_pow_0002:fp_pow_inst|Equal6~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal6~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal6~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal6~0_I .lut_mask = "A000A00000000000"; assign \a[26]~input0 = a[26]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist134_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_831,portadatain_unconnected_wire_832,portadatain_unconnected_wire_833,portadatain_unconnected_wire_834,portadatain_unconnected_wire_835,portadatain_unconnected_wire_836,portadatain_unconnected_wire_837,portadatain_unconnected_wire_838, portadatain_unconnected_wire_839,portadatain_unconnected_wire_840,portadatain_unconnected_wire_841,portadatain_unconnected_wire_842,portadatain_unconnected_wire_843,portadatain_unconnected_wire_844,portadatain_unconnected_wire_845,portadatain_unconnected_wire_846, portadatain_unconnected_wire_847,portadatain_unconnected_wire_848,portadatain_unconnected_wire_849,\a[26]~input0 }), .portaaddr({portaaddr_unconnected_wire_850,portaaddr_unconnected_wire_851,\fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_852,portbaddr_unconnected_wire_853,\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[3] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3 .logical_ram_depth = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3 .logical_ram_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3 .first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3 .last_address = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama3 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][3]~I .is_wysiwyg = "true"; assign \a[23]~input0 = a[23]; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist134_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_854,portadatain_unconnected_wire_855,portadatain_unconnected_wire_856,portadatain_unconnected_wire_857,portadatain_unconnected_wire_858,portadatain_unconnected_wire_859,portadatain_unconnected_wire_860,portadatain_unconnected_wire_861, portadatain_unconnected_wire_862,portadatain_unconnected_wire_863,portadatain_unconnected_wire_864,portadatain_unconnected_wire_865,portadatain_unconnected_wire_866,portadatain_unconnected_wire_867,portadatain_unconnected_wire_868,portadatain_unconnected_wire_869, portadatain_unconnected_wire_870,portadatain_unconnected_wire_871,portadatain_unconnected_wire_872,\a[23]~input0 }), .portaaddr({portaaddr_unconnected_wire_873,portaaddr_unconnected_wire_874,\fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist134_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_875,portbaddr_unconnected_wire_876,\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0 .logical_ram_depth = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0 .logical_ram_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0 .last_address = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal6~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][2] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal6~0 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Equal6~1 )); defparam \fp_pow_0002:fp_pow_inst|Equal6~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal6~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal6~1_I .lut_mask = "0808000000000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:expXIsZero_uid24_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal6~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:expXIsZero_uid24_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expXIsZero_uid24_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expXIsZero_uid24_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[17][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:expXIsZero_uid24_fpPowrTest_delay|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[17][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[17][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[17][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[16][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[17][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[16][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[16][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[16][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[16][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[16][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[16][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[16][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[16][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[16][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[15][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[16][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[15][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[15][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[15][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[15][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[15][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[15][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[15][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[15][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[15][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[14][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[15][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[14][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[14][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[14][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[13][0]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[14][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[13][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[13][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[13][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[13][0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[13][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[13][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[13][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[13][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[13][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[12][0]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[13][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[12][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[12][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[12][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[12][0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[12][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[12][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[12][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[12][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[12][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[11][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[12][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[11][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[11][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[11][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[11][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[11][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[11][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[11][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[11][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[11][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[10][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[11][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[10][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[10][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[10][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[9][0]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[10][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[9][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[9][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[9][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[9][0]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[9][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[9][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[9][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[9][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[9][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[8][0]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[9][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[8][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[8][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[8][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[8][0]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[8][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[8][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[8][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[8][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[8][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[7][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[8][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[7][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[7][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[7][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[6][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[7][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[6][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[6][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[6][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[5][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[6][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[5][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[5][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[5][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[4][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[5][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[4][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[4][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[4][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[3][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[4][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[3][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[3][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[3][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[3][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[3][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[3][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[3][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[3][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[3][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[3][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[0][0]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[0][0]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[0][0]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[0][0]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[0][0]~DUPLICATE_I .created_from = "Q(delay_signals[0][0])"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist127_inputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[0][0]~DUPLICATE ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist127_inputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist127_inputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist127_inputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1] )); defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "FFFFFFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[1] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[3]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[4] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist127_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_877,portadatain_unconnected_wire_878,portadatain_unconnected_wire_879,portadatain_unconnected_wire_880,portadatain_unconnected_wire_881,portadatain_unconnected_wire_882,portadatain_unconnected_wire_883,portadatain_unconnected_wire_884, portadatain_unconnected_wire_885,portadatain_unconnected_wire_886,portadatain_unconnected_wire_887,portadatain_unconnected_wire_888,portadatain_unconnected_wire_889,portadatain_unconnected_wire_890,portadatain_unconnected_wire_891,portadatain_unconnected_wire_892, portadatain_unconnected_wire_893,portadatain_unconnected_wire_894,portadatain_unconnected_wire_895,\fp_pow_0002:fp_pow_inst|dspba_delay:redist127_inputreg|delay_signals[0][0] }), .portaaddr({portaaddr_unconnected_wire_896,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_897,\fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_depth = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .last_address = 22; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_eq~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal30~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_eq )); defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_eq~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_eq~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[2]~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[2] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_eq~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[2]~0 )); defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[2]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[2]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[2]~0_I .lut_mask = "0AF50AF5AF50AF50"; dffeas \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[2]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[2] )); defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add60~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[1] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_eq ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[3] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|Add60~1 )); defparam \fp_pow_0002:fp_pow_inst|Add60~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add60~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add60~1_I .lut_mask = "0FF00FF024DB24DB"; dffeas \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add60~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[3] )); defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[4]~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_eq~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[3] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[1] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[4] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[4]~1 )); defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[4]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[4]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[4]~1_I .lut_mask = "0303FCFC233BDCC4"; dffeas \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[4]~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[4] )); defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal30~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[1] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[3] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[4] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|Equal30~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal30~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal30~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal30~0_I .lut_mask = "0000000000400040"; dffeas \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_eq~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal30~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_eq~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_eq~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_eq~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_eq~DUPLICATE_I .created_from = "Q(redist117_replace_rdcnt_eq)"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add60~0_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[1] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_eq~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Add60~0 )); defparam \fp_pow_0002:fp_pow_inst|Add60~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add60~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add60~0_I .lut_mask = "F0F00F0F0F0FF0F0"; dffeas \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add60~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[1] )); defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal29~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[1] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[3] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[4] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|Equal29~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal29~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal29~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal29~0_I .lut_mask = "0000000000800080"; dffeas \fp_pow_0002:fp_pow_inst|redist117_cmpReg_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal29~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist117_cmpReg_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist117_cmpReg_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist117_cmpReg_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist117_sticky_ena_q[0]~0_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_cmpReg_q[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_sticky_ena_q[0] ), .combout(\fp_pow_0002:fp_pow_inst|redist117_sticky_ena_q[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|redist117_sticky_ena_q[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist117_sticky_ena_q[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist117_sticky_ena_q[0]~0_I .lut_mask = "33FF33FF33FF33FF"; dffeas \fp_pow_0002:fp_pow_inst|redist117_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist117_sticky_ena_q[0]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist117_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist117_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist117_sticky_ena_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal23~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][7] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Equal23~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal23~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal23~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal23~0_I .lut_mask = "8000800080008000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal23~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal23~0 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Equal23~1 )); defparam \fp_pow_0002:fp_pow_inst|Equal23~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal23~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal23~1_I .lut_mask = "0800080000000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:expXIsZero_uid40_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal23~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:expXIsZero_uid40_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expXIsZero_uid40_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expXIsZero_uid40_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[3][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:expXIsZero_uid40_fpPowrTest_delay|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[3][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[3][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[3][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[3][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist121|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|exc_R_uid51_fpPowrTest_q_i[0]~I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist120|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist121|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|exc_R_uid51_fpPowrTest_q_i[0] )); defparam \fp_pow_0002:fp_pow_inst|exc_R_uid51_fpPowrTest_q_i[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|exc_R_uid51_fpPowrTest_q_i[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|exc_R_uid51_fpPowrTest_q_i[0]~I .lut_mask = "F0F0F0F000000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:exc_R_uid51_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|exc_R_uid51_fpPowrTest_q_i[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:exc_R_uid51_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:exc_R_uid51_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:exc_R_uid51_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[1]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add60~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[1]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[1]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[1]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[1]~DUPLICATE_I .created_from = "Q(redist117_replace_rdcnt_i[1])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[1]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[1] )); defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[2] )); defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[3] )); defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[4] )); defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[0]~0_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "FFFFFFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[1]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[1]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[1] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[2]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[2]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[2]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[2]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[2]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[2]~DUPLICATE_I .created_from = "Q(redist117_replace_rdcnt_i[2])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[2]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist117_replace_rdcnt_i[2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[2]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[2]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[2] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[3] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[3] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist117_replace_rdcnt_i[4] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[4] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist117_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_898,portadatain_unconnected_wire_899,portadatain_unconnected_wire_900,portadatain_unconnected_wire_901,portadatain_unconnected_wire_902,portadatain_unconnected_wire_903,portadatain_unconnected_wire_904,portadatain_unconnected_wire_905, portadatain_unconnected_wire_906,portadatain_unconnected_wire_907,portadatain_unconnected_wire_908,portadatain_unconnected_wire_909,portadatain_unconnected_wire_910,portadatain_unconnected_wire_911,portadatain_unconnected_wire_912,portadatain_unconnected_wire_913, portadatain_unconnected_wire_914,portadatain_unconnected_wire_915,portadatain_unconnected_wire_916,\fp_pow_0002:fp_pow_inst|dspba_delay:exc_R_uid51_fpPowrTest_delay|delay_signals[0][0] }), .portaaddr({portaaddr_unconnected_wire_917,\fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist117_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_918,\fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0 .logical_ram_depth = 22; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0 .logical_ram_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0 .last_address = 21; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist117_outputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist117_replace_mem_dmem|altera_syncram_qdg3:auto_generated|altsyncram_lmb4:altsyncram1|dataout_reg[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist117_outputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist117_outputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist117_outputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|zeroCase0_uid179_fpPowrTest_q_i[0]~I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist130_outputreg|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist117_outputreg|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|zeroCase0_uid179_fpPowrTest_q_i[0] )); defparam \fp_pow_0002:fp_pow_inst|zeroCase0_uid179_fpPowrTest_q_i[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|zeroCase0_uid179_fpPowrTest_q_i[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|zeroCase0_uid179_fpPowrTest_q_i[0]~I .lut_mask = "0022002200AA00AA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|delay_signals[0][0]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|zeroCase0_uid179_fpPowrTest_q_i[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|delay_signals[0][0]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|delay_signals[0][0]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|delay_signals[0][0]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|delay_signals[0][0]~DUPLICATE_I .created_from = "Q(delay_signals[0][0])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist77_sticky_ena_q[0]~feeder_I ( .combout(\fp_pow_0002:fp_pow_inst|redist77_sticky_ena_q[0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist77_sticky_ena_q[0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist77_sticky_ena_q[0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist77_sticky_ena_q[0]~feeder_I .lut_mask = "FFFFFFFFFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist77_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist77_sticky_ena_q[0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|redist77_cmpReg_q[0] ), .q(\fp_pow_0002:fp_pow_inst|redist77_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist77_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist77_sticky_ena_q[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist126|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal5~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][6] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][7] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Equal5~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal5~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal5~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal5~0_I .lut_mask = "0000000001010101"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal5~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal5~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Equal5~1 )); defparam \fp_pow_0002:fp_pow_inst|Equal5~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal5~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal5~1_I .lut_mask = "0000000000000005"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:expXIsMax_uid26_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal5~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:expXIsMax_uid26_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expXIsMax_uid26_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expXIsMax_uid26_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[17][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:expXIsMax_uid26_fpPowrTest_delay|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[17][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[17][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[17][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[16][0]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|__ALT_INV__delay_signals[17][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[16][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[16][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[16][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[16][0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[16][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[16][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[16][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[16][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[16][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[15][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[16][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[15][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[15][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[15][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[14][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[15][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[14][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[14][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[14][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[13][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[14][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[13][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[13][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[13][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[12][0]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|__ALT_INV__delay_signals[13][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[12][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[12][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[12][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[12][0]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[12][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[12][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[12][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[12][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[12][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[11][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[12][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[11][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[11][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[11][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[10][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[11][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[10][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[10][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[10][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[9][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[10][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[9][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[9][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[9][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[8][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[9][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[8][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[8][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[8][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[7][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[8][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[7][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[7][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[7][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[6][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[7][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[6][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[6][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[6][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[5][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[6][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[5][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[5][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[5][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[4][0]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|__ALT_INV__delay_signals[5][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[4][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[4][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[4][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[4][0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[4][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[4][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[4][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[4][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[4][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[3][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[4][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[3][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[3][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[3][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[3][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|exc_R_uid35_fpPowrTest_q[0]~I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|exc_R_uid35_fpPowrTest_q[0] )); defparam \fp_pow_0002:fp_pow_inst|exc_R_uid35_fpPowrTest_q[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|exc_R_uid35_fpPowrTest_q[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|exc_R_uid35_fpPowrTest_q[0]~I .lut_mask = "FF00FF0000000000"; dffeas \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[3] )); defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2]~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_eq ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[2] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[0] ), .combout(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2]~0 )); defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2]~0_I .lut_mask = "0AF50AF500FF00FF"; dffeas \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2] )); defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_eq ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[1] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[0]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[3] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i~1 )); defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i~1_I .lut_mask = "5555AAAA75758A8A"; dffeas \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[3]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[3]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[3]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[3]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[3]~DUPLICATE_I .created_from = "Q(redist137_replace_rdcnt_i[3])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal2~0_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[3]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|Equal2~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal2~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal2~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal2~0_I .lut_mask = "000000000C000C00"; dffeas \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_eq~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal2~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_eq )); defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_eq~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_eq~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[0]~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_eq ), .q(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[0] )); defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[0]~2_I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[0] ), .combout(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[0]~2 )); defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[0]~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[0]~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[0]~2_I .lut_mask = "FF00FF00FF00FF00"; dffeas \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[0]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[0]~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_eq ), .q(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[0]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[0]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[0]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[0]~DUPLICATE_I .created_from = "Q(redist137_replace_rdcnt_i[0])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add6~0_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[0]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[1] ), .combout(\fp_pow_0002:fp_pow_inst|Add6~0 )); defparam \fp_pow_0002:fp_pow_inst|Add6~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add6~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add6~0_I .lut_mask = "F00FF00FF00FF00F"; dffeas \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add6~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_eq ), .q(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[1] )); defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2]~DUPLICATE_I .created_from = "Q(redist137_replace_rdcnt_i[2])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal1~0_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[1] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[3] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[2]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[0] ), .combout(\fp_pow_0002:fp_pow_inst|Equal1~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal1~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal1~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal1~0_I .lut_mask = "000000000C000C00"; dffeas \fp_pow_0002:fp_pow_inst|redist137_cmpReg_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal1~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist137_cmpReg_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist137_cmpReg_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist137_cmpReg_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0]~0_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_cmpReg_q[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_sticky_ena_q[0] ), .combout(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0]~0_I .lut_mask = "0FFF0FFF0FFF0FFF"; dffeas \fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0]~I .is_wysiwyg = "true"; assign \a[10]~input0 = a[10]; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][10]~feeder_I ( .dataf(\__ALT_INV__a[10]~input0 ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][10]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][10]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][10]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][10]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][10]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0]~0_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0]~0_I .lut_mask = "F0F0F0F0F0F0F0F0"; dffeas \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] )); defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2]~DUPLICATE ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] )); defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[3]~DUPLICATE ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] )); defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0]~0_I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist137_replace_rdcnt_i[0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "FF00FF00FF00FF00"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[1] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[2]~DUPLICATE ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist137_replace_rdcnt_i[3]~DUPLICATE ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_919,portadatain_unconnected_wire_920,portadatain_unconnected_wire_921,portadatain_unconnected_wire_922,portadatain_unconnected_wire_923,portadatain_unconnected_wire_924,portadatain_unconnected_wire_925,portadatain_unconnected_wire_926, portadatain_unconnected_wire_927,portadatain_unconnected_wire_928,portadatain_unconnected_wire_929,portadatain_unconnected_wire_930,portadatain_unconnected_wire_931,portadatain_unconnected_wire_932,portadatain_unconnected_wire_933,portadatain_unconnected_wire_934, portadatain_unconnected_wire_935,portadatain_unconnected_wire_936,portadatain_unconnected_wire_937,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][10] }), .portaaddr({portaaddr_unconnected_wire_938,portaaddr_unconnected_wire_939,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_940,portbaddr_unconnected_wire_941,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[10] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10 .first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama10 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][10]~I .is_wysiwyg = "true"; assign \a[11]~input0 = a[11]; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\a[11]~input0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_942,portadatain_unconnected_wire_943,portadatain_unconnected_wire_944,portadatain_unconnected_wire_945,portadatain_unconnected_wire_946,portadatain_unconnected_wire_947,portadatain_unconnected_wire_948,portadatain_unconnected_wire_949, portadatain_unconnected_wire_950,portadatain_unconnected_wire_951,portadatain_unconnected_wire_952,portadatain_unconnected_wire_953,portadatain_unconnected_wire_954,portadatain_unconnected_wire_955,portadatain_unconnected_wire_956,portadatain_unconnected_wire_957, portadatain_unconnected_wire_958,portadatain_unconnected_wire_959,portadatain_unconnected_wire_960,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][11] }), .portaaddr({portaaddr_unconnected_wire_961,portaaddr_unconnected_wire_962,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_963,portbaddr_unconnected_wire_964,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[11] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11 .first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama11 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][11]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[11] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][11]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][11]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][11]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][11]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][11]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][11]~I .is_wysiwyg = "true"; assign \a[9]~input0 = a[9]; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][9]~feeder_I ( .dataf(\__ALT_INV__a[9]~input0 ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][9]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][9]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][9]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][9]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][9]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][9]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[1][9] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][9]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][9]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][9]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][9]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][9]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_965,portadatain_unconnected_wire_966,portadatain_unconnected_wire_967,portadatain_unconnected_wire_968,portadatain_unconnected_wire_969,portadatain_unconnected_wire_970,portadatain_unconnected_wire_971,portadatain_unconnected_wire_972, portadatain_unconnected_wire_973,portadatain_unconnected_wire_974,portadatain_unconnected_wire_975,portadatain_unconnected_wire_976,portadatain_unconnected_wire_977,portadatain_unconnected_wire_978,portadatain_unconnected_wire_979,portadatain_unconnected_wire_980, portadatain_unconnected_wire_981,portadatain_unconnected_wire_982,portadatain_unconnected_wire_983,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][9] }), .portaaddr({portaaddr_unconnected_wire_984,portaaddr_unconnected_wire_985,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_986,portbaddr_unconnected_wire_987,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[9] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9 .first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama9 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][9]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[9] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][9]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][9]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][9]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][9]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][9]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][9]~I .is_wysiwyg = "true"; assign \a[8]~input0 = a[8]; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][8]~feeder_I ( .dataf(\__ALT_INV__a[8]~input0 ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][8]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][8]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][8]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][8]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][8]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_988,portadatain_unconnected_wire_989,portadatain_unconnected_wire_990,portadatain_unconnected_wire_991,portadatain_unconnected_wire_992,portadatain_unconnected_wire_993,portadatain_unconnected_wire_994,portadatain_unconnected_wire_995, portadatain_unconnected_wire_996,portadatain_unconnected_wire_997,portadatain_unconnected_wire_998,portadatain_unconnected_wire_999,portadatain_unconnected_wire_1000,portadatain_unconnected_wire_1001,portadatain_unconnected_wire_1002, portadatain_unconnected_wire_1003,portadatain_unconnected_wire_1004,portadatain_unconnected_wire_1005,portadatain_unconnected_wire_1006,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][8] }), .portaaddr({portaaddr_unconnected_wire_1007,portaaddr_unconnected_wire_1008,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1009,portbaddr_unconnected_wire_1010,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[8] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8 .first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama8 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal22~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][10] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][11] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][9] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][8] ), .combout(\fp_pow_0002:fp_pow_inst|Equal22~2 )); defparam \fp_pow_0002:fp_pow_inst|Equal22~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal22~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal22~2_I .lut_mask = "A000A00000000000"; assign \a[6]~input0 = a[6]; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][6]~feeder_I ( .dataf(\__ALT_INV__a[6]~input0 ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][6]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1011,portadatain_unconnected_wire_1012,portadatain_unconnected_wire_1013,portadatain_unconnected_wire_1014,portadatain_unconnected_wire_1015,portadatain_unconnected_wire_1016,portadatain_unconnected_wire_1017, portadatain_unconnected_wire_1018,portadatain_unconnected_wire_1019,portadatain_unconnected_wire_1020,portadatain_unconnected_wire_1021,portadatain_unconnected_wire_1022,portadatain_unconnected_wire_1023,portadatain_unconnected_wire_1024, portadatain_unconnected_wire_1025,portadatain_unconnected_wire_1026,portadatain_unconnected_wire_1027,portadatain_unconnected_wire_1028,portadatain_unconnected_wire_1029,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][6] }), .portaaddr({portaaddr_unconnected_wire_1030,portaaddr_unconnected_wire_1031,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1032,portbaddr_unconnected_wire_1033,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[6] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6 .first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama6 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][6]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][6]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][6]~I .is_wysiwyg = "true"; assign \a[12]~input0 = a[12]; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][12]~feeder_I ( .dataf(\__ALT_INV__a[12]~input0 ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][12]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][12]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][12]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][12]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][12]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][12]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[1][12] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][12]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][12]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][12]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][12]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][12]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1034,portadatain_unconnected_wire_1035,portadatain_unconnected_wire_1036,portadatain_unconnected_wire_1037,portadatain_unconnected_wire_1038,portadatain_unconnected_wire_1039,portadatain_unconnected_wire_1040, portadatain_unconnected_wire_1041,portadatain_unconnected_wire_1042,portadatain_unconnected_wire_1043,portadatain_unconnected_wire_1044,portadatain_unconnected_wire_1045,portadatain_unconnected_wire_1046,portadatain_unconnected_wire_1047, portadatain_unconnected_wire_1048,portadatain_unconnected_wire_1049,portadatain_unconnected_wire_1050,portadatain_unconnected_wire_1051,portadatain_unconnected_wire_1052,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][12] }), .portaaddr({portaaddr_unconnected_wire_1053,portaaddr_unconnected_wire_1054,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1055,portbaddr_unconnected_wire_1056,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[12] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12 .first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama12 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][12]~I .is_wysiwyg = "true"; assign \a[18]~input0 = a[18]; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][3]~feeder_I ( .dataf(\__ALT_INV__a[18]~input0 ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|__ALT_INV__delay_signals[1][3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1057,portadatain_unconnected_wire_1058,portadatain_unconnected_wire_1059,portadatain_unconnected_wire_1060,portadatain_unconnected_wire_1061,portadatain_unconnected_wire_1062,portadatain_unconnected_wire_1063, portadatain_unconnected_wire_1064,portadatain_unconnected_wire_1065,portadatain_unconnected_wire_1066,portadatain_unconnected_wire_1067,portadatain_unconnected_wire_1068,portadatain_unconnected_wire_1069,portadatain_unconnected_wire_1070, portadatain_unconnected_wire_1071,portadatain_unconnected_wire_1072,portadatain_unconnected_wire_1073,portadatain_unconnected_wire_1074,portadatain_unconnected_wire_1075,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] }), .portaaddr({portaaddr_unconnected_wire_1076,portaaddr_unconnected_wire_1077,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1078,portbaddr_unconnected_wire_1079,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[18] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18 .first_bit_number = 18; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama18 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][18]~I .is_wysiwyg = "true"; assign \a[13]~input0 = a[13]; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][13]~feeder_I ( .dataf(\__ALT_INV__a[13]~input0 ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][13]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][13]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][13]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][13]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][13]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][13]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][13]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][13]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][13]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][13]~DUPLICATE_I .created_from = "Q(delay_signals[0][13])"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1080,portadatain_unconnected_wire_1081,portadatain_unconnected_wire_1082,portadatain_unconnected_wire_1083,portadatain_unconnected_wire_1084,portadatain_unconnected_wire_1085,portadatain_unconnected_wire_1086, portadatain_unconnected_wire_1087,portadatain_unconnected_wire_1088,portadatain_unconnected_wire_1089,portadatain_unconnected_wire_1090,portadatain_unconnected_wire_1091,portadatain_unconnected_wire_1092,portadatain_unconnected_wire_1093, portadatain_unconnected_wire_1094,portadatain_unconnected_wire_1095,portadatain_unconnected_wire_1096,portadatain_unconnected_wire_1097,portadatain_unconnected_wire_1098,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][13]~DUPLICATE }), .portaaddr({portaaddr_unconnected_wire_1099,portaaddr_unconnected_wire_1100,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1101,portbaddr_unconnected_wire_1102,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[13] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13 .first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama13 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][13]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[13] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][13]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][13]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][13]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][13]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][13]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][13]~I .is_wysiwyg = "true"; assign \a[22]~input0 = a[22]; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][7]~feeder_I ( .dataf(\__ALT_INV__a[22]~input0 ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][7]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1103,portadatain_unconnected_wire_1104,portadatain_unconnected_wire_1105,portadatain_unconnected_wire_1106,portadatain_unconnected_wire_1107,portadatain_unconnected_wire_1108,portadatain_unconnected_wire_1109, portadatain_unconnected_wire_1110,portadatain_unconnected_wire_1111,portadatain_unconnected_wire_1112,portadatain_unconnected_wire_1113,portadatain_unconnected_wire_1114,portadatain_unconnected_wire_1115,portadatain_unconnected_wire_1116, portadatain_unconnected_wire_1117,portadatain_unconnected_wire_1118,portadatain_unconnected_wire_1119,portadatain_unconnected_wire_1120,portadatain_unconnected_wire_1121,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] }), .portaaddr({portaaddr_unconnected_wire_1122,portaaddr_unconnected_wire_1123,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1124,portbaddr_unconnected_wire_1125,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[22] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22 .first_bit_number = 22; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama22 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][22]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[22] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][22]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][22]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][22]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][22]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][22]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][22] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][22]~I .is_wysiwyg = "true"; assign \a[20]~input0 = a[20]; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\a[20]~input0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|__ALT_INV__delay_signals[1][5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1126,portadatain_unconnected_wire_1127,portadatain_unconnected_wire_1128,portadatain_unconnected_wire_1129,portadatain_unconnected_wire_1130,portadatain_unconnected_wire_1131,portadatain_unconnected_wire_1132, portadatain_unconnected_wire_1133,portadatain_unconnected_wire_1134,portadatain_unconnected_wire_1135,portadatain_unconnected_wire_1136,portadatain_unconnected_wire_1137,portadatain_unconnected_wire_1138,portadatain_unconnected_wire_1139, portadatain_unconnected_wire_1140,portadatain_unconnected_wire_1141,portadatain_unconnected_wire_1142,portadatain_unconnected_wire_1143,portadatain_unconnected_wire_1144,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] }), .portaaddr({portaaddr_unconnected_wire_1145,portaaddr_unconnected_wire_1146,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1147,portbaddr_unconnected_wire_1148,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[20] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20 .first_bit_number = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama20 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][20]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[20] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][20]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][20]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][20]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][20]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][20]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][20] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][20]~I .is_wysiwyg = "true"; assign \a[19]~input0 = a[19]; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\a[19]~input0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1149,portadatain_unconnected_wire_1150,portadatain_unconnected_wire_1151,portadatain_unconnected_wire_1152,portadatain_unconnected_wire_1153,portadatain_unconnected_wire_1154,portadatain_unconnected_wire_1155, portadatain_unconnected_wire_1156,portadatain_unconnected_wire_1157,portadatain_unconnected_wire_1158,portadatain_unconnected_wire_1159,portadatain_unconnected_wire_1160,portadatain_unconnected_wire_1161,portadatain_unconnected_wire_1162, portadatain_unconnected_wire_1163,portadatain_unconnected_wire_1164,portadatain_unconnected_wire_1165,portadatain_unconnected_wire_1166,portadatain_unconnected_wire_1167,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] }), .portaaddr({portaaddr_unconnected_wire_1168,portaaddr_unconnected_wire_1169,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1170,portbaddr_unconnected_wire_1171,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[19] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19 .first_bit_number = 19; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama19 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][19]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[19] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][19]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][19]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][19]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][19]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][19]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][19]~I .is_wysiwyg = "true"; assign \a[21]~input0 = a[21]; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][6]~feeder_I ( .dataf(\__ALT_INV__a[21]~input0 ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][6]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|__ALT_INV__delay_signals[1][6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE_I .created_from = "Q(delay_signals[0][6])"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1172,portadatain_unconnected_wire_1173,portadatain_unconnected_wire_1174,portadatain_unconnected_wire_1175,portadatain_unconnected_wire_1176,portadatain_unconnected_wire_1177,portadatain_unconnected_wire_1178, portadatain_unconnected_wire_1179,portadatain_unconnected_wire_1180,portadatain_unconnected_wire_1181,portadatain_unconnected_wire_1182,portadatain_unconnected_wire_1183,portadatain_unconnected_wire_1184,portadatain_unconnected_wire_1185, portadatain_unconnected_wire_1186,portadatain_unconnected_wire_1187,portadatain_unconnected_wire_1188,portadatain_unconnected_wire_1189,portadatain_unconnected_wire_1190,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE }), .portaaddr({portaaddr_unconnected_wire_1191,portaaddr_unconnected_wire_1192,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1193,portbaddr_unconnected_wire_1194,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[21] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21 .first_bit_number = 21; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama21 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][21]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[21] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][21]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][21]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][21]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][21]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][21]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][21]~I .is_wysiwyg = "true"; assign \a[0]~input0 = a[0]; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][0]~feeder_I ( .dataf(\__ALT_INV__a[0]~input0 ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1195,portadatain_unconnected_wire_1196,portadatain_unconnected_wire_1197,portadatain_unconnected_wire_1198,portadatain_unconnected_wire_1199,portadatain_unconnected_wire_1200,portadatain_unconnected_wire_1201, portadatain_unconnected_wire_1202,portadatain_unconnected_wire_1203,portadatain_unconnected_wire_1204,portadatain_unconnected_wire_1205,portadatain_unconnected_wire_1206,portadatain_unconnected_wire_1207,portadatain_unconnected_wire_1208, portadatain_unconnected_wire_1209,portadatain_unconnected_wire_1210,portadatain_unconnected_wire_1211,portadatain_unconnected_wire_1212,portadatain_unconnected_wire_1213,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][0] }), .portaaddr({portaaddr_unconnected_wire_1214,portaaddr_unconnected_wire_1215,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1216,portbaddr_unconnected_wire_1217,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[0] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal22~3_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][22] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][20] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][19] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][21] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[0] ), .combout(\fp_pow_0002:fp_pow_inst|Equal22~3 )); defparam \fp_pow_0002:fp_pow_inst|Equal22~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal22~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal22~3_I .lut_mask = "8000800000000000"; assign \a[16]~input0 = a[16]; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\a[16]~input0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1218,portadatain_unconnected_wire_1219,portadatain_unconnected_wire_1220,portadatain_unconnected_wire_1221,portadatain_unconnected_wire_1222,portadatain_unconnected_wire_1223,portadatain_unconnected_wire_1224, portadatain_unconnected_wire_1225,portadatain_unconnected_wire_1226,portadatain_unconnected_wire_1227,portadatain_unconnected_wire_1228,portadatain_unconnected_wire_1229,portadatain_unconnected_wire_1230,portadatain_unconnected_wire_1231, portadatain_unconnected_wire_1232,portadatain_unconnected_wire_1233,portadatain_unconnected_wire_1234,portadatain_unconnected_wire_1235,portadatain_unconnected_wire_1236,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] }), .portaaddr({portaaddr_unconnected_wire_1237,portaaddr_unconnected_wire_1238,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1239,portbaddr_unconnected_wire_1240,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[16] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16 .first_bit_number = 16; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama16 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][16]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][16] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][16]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][16]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][16]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][16]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][16]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][16]~I .is_wysiwyg = "true"; assign \a[17]~input0 = a[17]; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\a[17]~input0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1241,portadatain_unconnected_wire_1242,portadatain_unconnected_wire_1243,portadatain_unconnected_wire_1244,portadatain_unconnected_wire_1245,portadatain_unconnected_wire_1246,portadatain_unconnected_wire_1247, portadatain_unconnected_wire_1248,portadatain_unconnected_wire_1249,portadatain_unconnected_wire_1250,portadatain_unconnected_wire_1251,portadatain_unconnected_wire_1252,portadatain_unconnected_wire_1253,portadatain_unconnected_wire_1254, portadatain_unconnected_wire_1255,portadatain_unconnected_wire_1256,portadatain_unconnected_wire_1257,portadatain_unconnected_wire_1258,portadatain_unconnected_wire_1259,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] }), .portaaddr({portaaddr_unconnected_wire_1260,portaaddr_unconnected_wire_1261,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1262,portbaddr_unconnected_wire_1263,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[17] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17 .first_bit_number = 17; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama17 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][17]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[17] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][17]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][17]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][17]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][17]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][17]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][17]~I .is_wysiwyg = "true"; assign \a[15]~input0 = a[15]; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\a[15]~input0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|__ALT_INV__delay_signals[1][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1264,portadatain_unconnected_wire_1265,portadatain_unconnected_wire_1266,portadatain_unconnected_wire_1267,portadatain_unconnected_wire_1268,portadatain_unconnected_wire_1269,portadatain_unconnected_wire_1270, portadatain_unconnected_wire_1271,portadatain_unconnected_wire_1272,portadatain_unconnected_wire_1273,portadatain_unconnected_wire_1274,portadatain_unconnected_wire_1275,portadatain_unconnected_wire_1276,portadatain_unconnected_wire_1277, portadatain_unconnected_wire_1278,portadatain_unconnected_wire_1279,portadatain_unconnected_wire_1280,portadatain_unconnected_wire_1281,portadatain_unconnected_wire_1282,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portaaddr({portaaddr_unconnected_wire_1283,portaaddr_unconnected_wire_1284,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1285,portbaddr_unconnected_wire_1286,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[15] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15 .first_bit_number = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama15 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][15]~I .is_wysiwyg = "true"; assign \a[14]~input0 = a[14]; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][14]~feeder_I ( .dataf(\__ALT_INV__a[14]~input0 ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][14]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][14]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][14]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][14]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][14]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][14] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1287,portadatain_unconnected_wire_1288,portadatain_unconnected_wire_1289,portadatain_unconnected_wire_1290,portadatain_unconnected_wire_1291,portadatain_unconnected_wire_1292,portadatain_unconnected_wire_1293, portadatain_unconnected_wire_1294,portadatain_unconnected_wire_1295,portadatain_unconnected_wire_1296,portadatain_unconnected_wire_1297,portadatain_unconnected_wire_1298,portadatain_unconnected_wire_1299,portadatain_unconnected_wire_1300, portadatain_unconnected_wire_1301,portadatain_unconnected_wire_1302,portadatain_unconnected_wire_1303,portadatain_unconnected_wire_1304,portadatain_unconnected_wire_1305,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][14] }), .portaaddr({portaaddr_unconnected_wire_1306,portaaddr_unconnected_wire_1307,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1308,portbaddr_unconnected_wire_1309,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[14] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14 .first_bit_number = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama14 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][14]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[14] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][14]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][14]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][14]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][14]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][14]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][14] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal22~4_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][16] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][17] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][15] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][14] ), .combout(\fp_pow_0002:fp_pow_inst|Equal22~4 )); defparam \fp_pow_0002:fp_pow_inst|Equal22~4_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal22~4_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal22~4_I .lut_mask = "C0C0000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal22~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][12] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][18] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][13] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal22~3 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal22~4 ), .combout(\fp_pow_0002:fp_pow_inst|Equal22~5 )); defparam \fp_pow_0002:fp_pow_inst|Equal22~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal22~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal22~5_I .lut_mask = "0000000000800080"; assign \a[7]~input0 = a[7]; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][7]~feeder_I ( .dataf(\__ALT_INV__a[7]~input0 ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][7]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][7]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[1][7] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][7]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1310,portadatain_unconnected_wire_1311,portadatain_unconnected_wire_1312,portadatain_unconnected_wire_1313,portadatain_unconnected_wire_1314,portadatain_unconnected_wire_1315,portadatain_unconnected_wire_1316, portadatain_unconnected_wire_1317,portadatain_unconnected_wire_1318,portadatain_unconnected_wire_1319,portadatain_unconnected_wire_1320,portadatain_unconnected_wire_1321,portadatain_unconnected_wire_1322,portadatain_unconnected_wire_1323, portadatain_unconnected_wire_1324,portadatain_unconnected_wire_1325,portadatain_unconnected_wire_1326,portadatain_unconnected_wire_1327,portadatain_unconnected_wire_1328,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][7] }), .portaaddr({portaaddr_unconnected_wire_1329,portaaddr_unconnected_wire_1330,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1331,portbaddr_unconnected_wire_1332,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[7] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7 .first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama7 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][7]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[7] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][7]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][7]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][7]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][7]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][7]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][7]~DUPLICATE_I .created_from = "Q(delay_signals[0][7])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal22~6_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal22~2 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][6] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal22~5 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][7]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Equal22~6 )); defparam \fp_pow_0002:fp_pow_inst|Equal22~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal22~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal22~6_I .lut_mask = "0030003000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal22~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][6] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][2] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Equal22~1 )); defparam \fp_pow_0002:fp_pow_inst|Equal22~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal22~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal22~1_I .lut_mask = "0000000000000101"; assign \a[1]~input0 = a[1]; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][1]~feeder_I ( .dataf(\__ALT_INV__a[1]~input0 ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1333,portadatain_unconnected_wire_1334,portadatain_unconnected_wire_1335,portadatain_unconnected_wire_1336,portadatain_unconnected_wire_1337,portadatain_unconnected_wire_1338,portadatain_unconnected_wire_1339, portadatain_unconnected_wire_1340,portadatain_unconnected_wire_1341,portadatain_unconnected_wire_1342,portadatain_unconnected_wire_1343,portadatain_unconnected_wire_1344,portadatain_unconnected_wire_1345,portadatain_unconnected_wire_1346, portadatain_unconnected_wire_1347,portadatain_unconnected_wire_1348,portadatain_unconnected_wire_1349,portadatain_unconnected_wire_1350,portadatain_unconnected_wire_1351,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][1] }), .portaaddr({portaaddr_unconnected_wire_1352,portaaddr_unconnected_wire_1353,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1354,portbaddr_unconnected_wire_1355,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[1] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1 .first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama1 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[1] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][1]~I .is_wysiwyg = "true"; assign \a[5]~input0 = a[5]; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][5]~feeder_I ( .dataf(\__ALT_INV__a[5]~input0 ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][5]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1356,portadatain_unconnected_wire_1357,portadatain_unconnected_wire_1358,portadatain_unconnected_wire_1359,portadatain_unconnected_wire_1360,portadatain_unconnected_wire_1361,portadatain_unconnected_wire_1362, portadatain_unconnected_wire_1363,portadatain_unconnected_wire_1364,portadatain_unconnected_wire_1365,portadatain_unconnected_wire_1366,portadatain_unconnected_wire_1367,portadatain_unconnected_wire_1368,portadatain_unconnected_wire_1369, portadatain_unconnected_wire_1370,portadatain_unconnected_wire_1371,portadatain_unconnected_wire_1372,portadatain_unconnected_wire_1373,portadatain_unconnected_wire_1374,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][5] }), .portaaddr({portaaddr_unconnected_wire_1375,portaaddr_unconnected_wire_1376,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1377,portbaddr_unconnected_wire_1378,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[5] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5 .first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama5 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][5]~I .is_wysiwyg = "true"; assign \a[2]~input0 = a[2]; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][2]~feeder_I ( .dataf(\__ALT_INV__a[2]~input0 ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][2]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][2]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[1][2] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][2]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1379,portadatain_unconnected_wire_1380,portadatain_unconnected_wire_1381,portadatain_unconnected_wire_1382,portadatain_unconnected_wire_1383,portadatain_unconnected_wire_1384,portadatain_unconnected_wire_1385, portadatain_unconnected_wire_1386,portadatain_unconnected_wire_1387,portadatain_unconnected_wire_1388,portadatain_unconnected_wire_1389,portadatain_unconnected_wire_1390,portadatain_unconnected_wire_1391,portadatain_unconnected_wire_1392, portadatain_unconnected_wire_1393,portadatain_unconnected_wire_1394,portadatain_unconnected_wire_1395,portadatain_unconnected_wire_1396,portadatain_unconnected_wire_1397,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][2] }), .portaaddr({portaaddr_unconnected_wire_1398,portaaddr_unconnected_wire_1399,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1400,portbaddr_unconnected_wire_1401,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[2] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2 .first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama2 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][2]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][2]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][2]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][2]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][2]~DUPLICATE_I .created_from = "Q(delay_signals[0][2])"; assign \a[3]~input0 = a[3]; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][3]~feeder_I ( .dataf(\__ALT_INV__a[3]~input0 ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][3]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[1][3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][3]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][3]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][3]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][3]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][3]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][3]~DUPLICATE_I .created_from = "Q(delay_signals[0][3])"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1402,portadatain_unconnected_wire_1403,portadatain_unconnected_wire_1404,portadatain_unconnected_wire_1405,portadatain_unconnected_wire_1406,portadatain_unconnected_wire_1407,portadatain_unconnected_wire_1408, portadatain_unconnected_wire_1409,portadatain_unconnected_wire_1410,portadatain_unconnected_wire_1411,portadatain_unconnected_wire_1412,portadatain_unconnected_wire_1413,portadatain_unconnected_wire_1414,portadatain_unconnected_wire_1415, portadatain_unconnected_wire_1416,portadatain_unconnected_wire_1417,portadatain_unconnected_wire_1418,portadatain_unconnected_wire_1419,portadatain_unconnected_wire_1420,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][3]~DUPLICATE }), .portaaddr({portaaddr_unconnected_wire_1421,portaaddr_unconnected_wire_1422,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1423,portbaddr_unconnected_wire_1424,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[3] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3 .first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama3 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|__ALT_INV__dataout_reg[3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][3]~I .is_wysiwyg = "true"; assign \a[4]~input0 = a[4]; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][4]~feeder_I ( .dataf(\__ALT_INV__a[4]~input0 ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][4]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][4]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist137_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1425,portadatain_unconnected_wire_1426,portadatain_unconnected_wire_1427,portadatain_unconnected_wire_1428,portadatain_unconnected_wire_1429,portadatain_unconnected_wire_1430,portadatain_unconnected_wire_1431, portadatain_unconnected_wire_1432,portadatain_unconnected_wire_1433,portadatain_unconnected_wire_1434,portadatain_unconnected_wire_1435,portadatain_unconnected_wire_1436,portadatain_unconnected_wire_1437,portadatain_unconnected_wire_1438, portadatain_unconnected_wire_1439,portadatain_unconnected_wire_1440,portadatain_unconnected_wire_1441,portadatain_unconnected_wire_1442,portadatain_unconnected_wire_1443,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][4] }), .portaaddr({portaaddr_unconnected_wire_1444,portaaddr_unconnected_wire_1445,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist137_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1446,portbaddr_unconnected_wire_1447,\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[4] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4 .logical_ram_depth = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4 .logical_ram_width = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4 .first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4 .last_address = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|lutrama4 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal22~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][3] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Equal22~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal22~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal22~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal22~0_I .lut_mask = "8000000080000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist134_replace_mem_dmem|altera_syncram_4eg3:auto_generated|altsyncram_vmb4:altsyncram1|dataout_reg[1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal22~7_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][7] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal22~6 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal22~1 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal22~0 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Equal22~7 )); defparam \fp_pow_0002:fp_pow_inst|Equal22~7_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal22~7_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal22~7_I .lut_mask = "0000000000000002"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:xEQOneAbs_uid19_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal22~7 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:xEQOneAbs_uid19_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:xEQOneAbs_uid19_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:xEQOneAbs_uid19_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist128_inputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:xEQOneAbs_uid19_fpPowrTest_delay|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128_inputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128_inputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128_inputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[19][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128_inputreg|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[19][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[19][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[19][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[18][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[19][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[18][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[18][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[18][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[17][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[18][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[17][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[17][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[17][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[16][0]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[17][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[16][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[16][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[16][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[16][0]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[16][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[16][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[16][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[16][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[16][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[15][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[16][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[15][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[15][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[15][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[14][0]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[15][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[14][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[14][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[14][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[14][0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[14][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[14][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[14][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[14][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[14][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[13][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[14][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[13][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[13][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[13][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[12][0]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[13][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[12][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[12][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[12][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[12][0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[12][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[12][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[12][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[12][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[12][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[11][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[12][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[11][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[11][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[11][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[10][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[11][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[10][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[10][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[10][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[10][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[10][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[10][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[10][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[10][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[10][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[9][0]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[10][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[9][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[9][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[9][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[9][0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[9][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[9][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[9][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[9][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[9][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[8][0]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[9][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[8][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[8][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[8][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[8][0]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[8][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[8][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[8][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[8][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[8][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[7][0]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[8][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[7][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[7][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[7][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[7][0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[7][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[7][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[7][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[7][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[7][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[6][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[7][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[6][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[6][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[6][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[6][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[6][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[6][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[6][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[6][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[6][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[5][0]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[6][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[5][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[5][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[5][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[5][0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[5][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[5][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[5][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[5][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[5][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[4][0]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[5][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[4][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[4][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[4][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[4][0]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[4][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[4][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[4][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[4][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[4][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[3][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[4][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[3][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[3][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[3][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[3][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist128|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[0][0]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[0][0]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[0][0]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[0][0]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist125|delay_signals[0][0]~DUPLICATE_I .created_from = "Q(delay_signals[0][0])"; assign \a[31]~input0 = a[31]; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[35][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\a[31]~input0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[35][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[35][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[35][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[34][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[35][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[34][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[34][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[34][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[33][0]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|__ALT_INV__delay_signals[34][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[33][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[33][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[33][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[33][0]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[33][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[33][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[33][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[33][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[33][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[32][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[33][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[32][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[32][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[32][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[31][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[32][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[31][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[31][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[31][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[30][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[31][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[30][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[30][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[30][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[29][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[30][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[29][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[29][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[29][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[28][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[29][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[28][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[28][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[28][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[27][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[28][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[27][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[27][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[27][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[26][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[27][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[26][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[26][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[26][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[25][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[26][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[25][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[25][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[25][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[24][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[25][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[24][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[24][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[24][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[23][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[24][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[23][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[23][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[23][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[22][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[23][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[22][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[22][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[22][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[21][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[22][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[21][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[21][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[21][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[20][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[21][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[20][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[20][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[20][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[19][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|__ALT_INV__delay_signals[20][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[19][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[19][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[19][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[19][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[19][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[19][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[19][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[19][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[19][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[18][0]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|__ALT_INV__delay_signals[19][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[18][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[18][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[18][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[18][0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[18][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[18][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[18][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[18][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[18][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[17][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[18][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[17][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[17][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[17][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[16][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[17][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[16][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[16][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[16][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[15][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[16][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[15][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[15][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[15][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[14][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[15][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[14][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[14][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[14][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[13][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[14][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[13][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[13][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[13][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[12][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[13][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[12][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[12][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[12][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[11][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[12][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[11][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[11][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[11][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[10][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[11][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[10][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[10][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[10][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[9][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[10][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[9][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[9][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[9][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[8][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[9][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[8][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[8][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[8][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[7][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[8][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[7][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[7][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[7][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[6][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[7][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[6][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[6][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[6][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[5][0]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|__ALT_INV__delay_signals[6][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[5][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[5][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[5][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[5][0]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[5][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[5][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[5][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[5][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[5][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[4][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[5][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[4][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[4][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[4][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[3][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[4][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[3][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[3][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[3][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[2][0]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|__ALT_INV__delay_signals[3][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[2][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[2][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[2][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[2][0]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[2][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~94_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[0] ), .cin(gnd), .cout(\fp_pow_0002:fp_pow_inst|Add56~94 )); defparam \fp_pow_0002:fp_pow_inst|Add56~94_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~94_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~94_I .lut_mask = "0000000000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~90_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][1] ), .cin(\fp_pow_0002:fp_pow_inst|Add56~94 ), .cout(\fp_pow_0002:fp_pow_inst|Add56~90 )); defparam \fp_pow_0002:fp_pow_inst|Add56~90_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~90_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~90_I .lut_mask = "0000000000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~86_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .cin(\fp_pow_0002:fp_pow_inst|Add56~90 ), .cout(\fp_pow_0002:fp_pow_inst|Add56~86 )); defparam \fp_pow_0002:fp_pow_inst|Add56~86_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~86_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~86_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~82_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][3] ), .cin(\fp_pow_0002:fp_pow_inst|Add56~86 ), .cout(\fp_pow_0002:fp_pow_inst|Add56~82 )); defparam \fp_pow_0002:fp_pow_inst|Add56~82_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~82_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~82_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~78_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][4] ), .cin(\fp_pow_0002:fp_pow_inst|Add56~82 ), .cout(\fp_pow_0002:fp_pow_inst|Add56~78 )); defparam \fp_pow_0002:fp_pow_inst|Add56~78_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~78_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~78_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~74_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add56~78 ), .cout(\fp_pow_0002:fp_pow_inst|Add56~74 )); defparam \fp_pow_0002:fp_pow_inst|Add56~74_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~74_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~74_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~70_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][6] ), .cin(\fp_pow_0002:fp_pow_inst|Add56~74 ), .cout(\fp_pow_0002:fp_pow_inst|Add56~70 )); defparam \fp_pow_0002:fp_pow_inst|Add56~70_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~70_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~70_I .lut_mask = "0000000000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~66_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][7]~DUPLICATE ), .cin(\fp_pow_0002:fp_pow_inst|Add56~70 ), .cout(\fp_pow_0002:fp_pow_inst|Add56~66 )); defparam \fp_pow_0002:fp_pow_inst|Add56~66_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~66_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~66_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~62_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][8] ), .cin(\fp_pow_0002:fp_pow_inst|Add56~66 ), .cout(\fp_pow_0002:fp_pow_inst|Add56~62 )); defparam \fp_pow_0002:fp_pow_inst|Add56~62_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~62_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~62_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~58_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][9] ), .cin(\fp_pow_0002:fp_pow_inst|Add56~62 ), .cout(\fp_pow_0002:fp_pow_inst|Add56~58 )); defparam \fp_pow_0002:fp_pow_inst|Add56~58_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~58_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~58_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~54_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][10] ), .cin(\fp_pow_0002:fp_pow_inst|Add56~58 ), .cout(\fp_pow_0002:fp_pow_inst|Add56~54 )); defparam \fp_pow_0002:fp_pow_inst|Add56~54_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~54_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~54_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~50_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][11] ), .cin(\fp_pow_0002:fp_pow_inst|Add56~54 ), .cout(\fp_pow_0002:fp_pow_inst|Add56~50 )); defparam \fp_pow_0002:fp_pow_inst|Add56~50_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~50_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~50_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~46_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][12] ), .cin(\fp_pow_0002:fp_pow_inst|Add56~50 ), .cout(\fp_pow_0002:fp_pow_inst|Add56~46 )); defparam \fp_pow_0002:fp_pow_inst|Add56~46_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~46_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~46_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~42_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][13] ), .cin(\fp_pow_0002:fp_pow_inst|Add56~46 ), .cout(\fp_pow_0002:fp_pow_inst|Add56~42 )); defparam \fp_pow_0002:fp_pow_inst|Add56~42_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~42_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~42_I .lut_mask = "0000000000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~38_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][14] ), .cin(\fp_pow_0002:fp_pow_inst|Add56~42 ), .cout(\fp_pow_0002:fp_pow_inst|Add56~38 )); defparam \fp_pow_0002:fp_pow_inst|Add56~38_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~38_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~38_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~34_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][15] ), .cin(\fp_pow_0002:fp_pow_inst|Add56~38 ), .cout(\fp_pow_0002:fp_pow_inst|Add56~34 )); defparam \fp_pow_0002:fp_pow_inst|Add56~34_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~34_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~34_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~30_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][16] ), .cin(\fp_pow_0002:fp_pow_inst|Add56~34 ), .cout(\fp_pow_0002:fp_pow_inst|Add56~30 )); defparam \fp_pow_0002:fp_pow_inst|Add56~30_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~30_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~30_I .lut_mask = "0000000000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~26_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][17] ), .cin(\fp_pow_0002:fp_pow_inst|Add56~30 ), .cout(\fp_pow_0002:fp_pow_inst|Add56~26 )); defparam \fp_pow_0002:fp_pow_inst|Add56~26_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~26_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~26_I .lut_mask = "0000000000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~22_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][18] ), .cin(\fp_pow_0002:fp_pow_inst|Add56~26 ), .cout(\fp_pow_0002:fp_pow_inst|Add56~22 )); defparam \fp_pow_0002:fp_pow_inst|Add56~22_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~22_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~22_I .lut_mask = "0000000000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~18_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][19] ), .cin(\fp_pow_0002:fp_pow_inst|Add56~22 ), .cout(\fp_pow_0002:fp_pow_inst|Add56~18 )); defparam \fp_pow_0002:fp_pow_inst|Add56~18_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~18_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~18_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~14_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][20] ), .cin(\fp_pow_0002:fp_pow_inst|Add56~18 ), .cout(\fp_pow_0002:fp_pow_inst|Add56~14 )); defparam \fp_pow_0002:fp_pow_inst|Add56~14_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~14_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~14_I .lut_mask = "0000000000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~10_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][21] ), .cin(\fp_pow_0002:fp_pow_inst|Add56~14 ), .cout(\fp_pow_0002:fp_pow_inst|Add56~10 )); defparam \fp_pow_0002:fp_pow_inst|Add56~10_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~10_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~10_I .lut_mask = "0000000000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~6_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][22] ), .cin(\fp_pow_0002:fp_pow_inst|Add56~10 ), .cout(\fp_pow_0002:fp_pow_inst|Add56~6 )); defparam \fp_pow_0002:fp_pow_inst|Add56~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~6_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add56~1_I ( .cin(\fp_pow_0002:fp_pow_inst|Add56~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add56~1 )); defparam \fp_pow_0002:fp_pow_inst|Add56~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add56~1_I .lut_mask = "0000FFFF0000FFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:fracXIsZero_uid29_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add56~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:fracXIsZero_uid29_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:fracXIsZero_uid29_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:fracXIsZero_uid29_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[19][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:fracXIsZero_uid29_fpPowrTest_delay|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[19][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[19][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[19][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[18][0]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|__ALT_INV__delay_signals[19][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[18][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[18][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[18][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[18][0]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[18][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[18][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[18][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[18][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[18][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[17][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[18][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[17][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[17][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[17][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[16][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[17][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[16][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[16][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[16][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[15][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[16][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[15][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[15][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[15][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[14][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[15][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[14][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[14][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[14][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[13][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[14][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[13][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[13][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[13][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[12][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[13][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[12][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[12][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[12][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[11][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[12][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[11][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[11][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[11][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[10][0]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|__ALT_INV__delay_signals[11][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[10][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[10][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[10][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[10][0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[10][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[10][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[10][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[10][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[10][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[9][0]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|__ALT_INV__delay_signals[10][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[9][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[9][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[9][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[9][0]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[9][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[9][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[9][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[9][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[9][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[8][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[9][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[8][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[8][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[8][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[7][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[8][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[7][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[7][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[7][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[6][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[7][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[6][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[6][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[6][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[5][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[6][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[5][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[5][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[5][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[4][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[5][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[4][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[4][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[4][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[3][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[4][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[3][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[3][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[3][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[3][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist124_outputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124_outputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124_outputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist124_outputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|excRNaN_uid204_fpPowrTest_q_i[0]~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124_outputreg|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist121|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|excRNaN_uid204_fpPowrTest_q_i[0]~1 )); defparam \fp_pow_0002:fp_pow_inst|excRNaN_uid204_fpPowrTest_q_i[0]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|excRNaN_uid204_fpPowrTest_q_i[0]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|excRNaN_uid204_fpPowrTest_q_i[0]~1_I .lut_mask = "AAEEAAEEA0A0A0A0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|excRNaN_uid204_fpPowrTest_q_i[0]~0_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist120|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist119|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist126|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|excRNaN_uid204_fpPowrTest_q_i[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|excRNaN_uid204_fpPowrTest_q_i[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|excRNaN_uid204_fpPowrTest_q_i[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|excRNaN_uid204_fpPowrTest_q_i[0]~0_I .lut_mask = "3F0F3F0F33003300"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|excRNaN_uid204_fpPowrTest_q_i[0]~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__exc_R_uid35_fpPowrTest_q[0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist118_replace_mem_ia[0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRNaN_uid204_fpPowrTest_q_i[0]~1 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRNaN_uid204_fpPowrTest_q_i[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|excRNaN_uid204_fpPowrTest_q_i[0]~2 )); defparam \fp_pow_0002:fp_pow_inst|excRNaN_uid204_fpPowrTest_q_i[0]~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|excRNaN_uid204_fpPowrTest_q_i[0]~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|excRNaN_uid204_fpPowrTest_q_i[0]~2_I .lut_mask = "FFFF0101FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:excRNaN_uid204_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|excRNaN_uid204_fpPowrTest_q_i[0]~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:excRNaN_uid204_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:excRNaN_uid204_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:excRNaN_uid204_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0]~0_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "FFFFFFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[1]~DUPLICATE ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[1] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[3] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[3] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist77_replace_rdcnt_i[4] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[4] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist77_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1448,portadatain_unconnected_wire_1449,portadatain_unconnected_wire_1450,portadatain_unconnected_wire_1451,portadatain_unconnected_wire_1452,portadatain_unconnected_wire_1453,portadatain_unconnected_wire_1454, portadatain_unconnected_wire_1455,portadatain_unconnected_wire_1456,portadatain_unconnected_wire_1457,portadatain_unconnected_wire_1458,portadatain_unconnected_wire_1459,portadatain_unconnected_wire_1460,portadatain_unconnected_wire_1461, portadatain_unconnected_wire_1462,portadatain_unconnected_wire_1463,portadatain_unconnected_wire_1464,portadatain_unconnected_wire_1465,portadatain_unconnected_wire_1466,\fp_pow_0002:fp_pow_inst|dspba_delay:excRNaN_uid204_fpPowrTest_delay|delay_signals[0][0] }), .portaaddr({portaaddr_unconnected_wire_1467,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1468,\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .logical_ram_depth = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .logical_ram_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .last_address = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist82_sticky_ena_q[0]~feeder_I ( .combout(\fp_pow_0002:fp_pow_inst|redist82_sticky_ena_q[0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist82_sticky_ena_q[0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist82_sticky_ena_q[0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist82_sticky_ena_q[0]~feeder_I .lut_mask = "FFFFFFFFFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist82_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist82_sticky_ena_q[0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|redist78_cmpReg_q[0] ), .q(\fp_pow_0002:fp_pow_inst|redist82_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist82_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist82_sticky_ena_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[0][0]~_wirecell_I ( .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[0][0]~_wirecell )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[0][0]~_wirecell_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[0][0]~_wirecell_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[0][0]~_wirecell_I .lut_mask = "FFFF0000FFFF0000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "AAAAAAAAAAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[1] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~DUPLICATE ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[4] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist82_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1469,portadatain_unconnected_wire_1470,portadatain_unconnected_wire_1471,portadatain_unconnected_wire_1472,portadatain_unconnected_wire_1473,portadatain_unconnected_wire_1474,portadatain_unconnected_wire_1475, portadatain_unconnected_wire_1476,portadatain_unconnected_wire_1477,portadatain_unconnected_wire_1478,portadatain_unconnected_wire_1479,portadatain_unconnected_wire_1480,portadatain_unconnected_wire_1481,portadatain_unconnected_wire_1482, portadatain_unconnected_wire_1483,portadatain_unconnected_wire_1484,portadatain_unconnected_wire_1485,portadatain_unconnected_wire_1486,portadatain_unconnected_wire_1487,\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|delay_signals[0][0]~_wirecell }), .portaaddr({portaaddr_unconnected_wire_1488,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~DUPLICATE , \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1489,\fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_depth = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .last_address = 22; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist82_outputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist82_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist82_outputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist82_outputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist82_outputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|zeroCase1_uid177_fpPowrTest_q_i[0]~I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist130_outputreg|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist82_outputreg|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|zeroCase1_uid177_fpPowrTest_q_i[0] )); defparam \fp_pow_0002:fp_pow_inst|zeroCase1_uid177_fpPowrTest_q_i[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|zeroCase1_uid177_fpPowrTest_q_i[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|zeroCase1_uid177_fpPowrTest_q_i[0]~I .lut_mask = "0000000000300030"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|zeroCase1_uid177_fpPowrTest_q_i[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist122_sticky_ena_q[0]~feeder_I ( .combout(\fp_pow_0002:fp_pow_inst|redist122_sticky_ena_q[0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist122_sticky_ena_q[0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist122_sticky_ena_q[0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist122_sticky_ena_q[0]~feeder_I .lut_mask = "FFFFFFFFFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist122_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist122_sticky_ena_q[0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|redist78_cmpReg_q[0] ), .q(\fp_pow_0002:fp_pow_inst|redist122_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist122_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist122_sticky_ena_q[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist122_inputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|exc_R_uid35_fpPowrTest_q[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist122_inputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist122_inputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist122_inputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "FFFFFFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[1] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[2] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~DUPLICATE ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[4] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist122_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1490,portadatain_unconnected_wire_1491,portadatain_unconnected_wire_1492,portadatain_unconnected_wire_1493,portadatain_unconnected_wire_1494,portadatain_unconnected_wire_1495,portadatain_unconnected_wire_1496, portadatain_unconnected_wire_1497,portadatain_unconnected_wire_1498,portadatain_unconnected_wire_1499,portadatain_unconnected_wire_1500,portadatain_unconnected_wire_1501,portadatain_unconnected_wire_1502,portadatain_unconnected_wire_1503, portadatain_unconnected_wire_1504,portadatain_unconnected_wire_1505,portadatain_unconnected_wire_1506,portadatain_unconnected_wire_1507,portadatain_unconnected_wire_1508,\fp_pow_0002:fp_pow_inst|dspba_delay:redist122_inputreg|delay_signals[0][0] }), .portaaddr({portaaddr_unconnected_wire_1509,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~DUPLICATE , \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1510,\fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_depth = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .last_address = 22; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist79_sticky_ena_q[0]~feeder_I ( .combout(\fp_pow_0002:fp_pow_inst|redist79_sticky_ena_q[0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist79_sticky_ena_q[0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist79_sticky_ena_q[0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist79_sticky_ena_q[0]~feeder_I .lut_mask = "FFFFFFFFFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist79_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist79_sticky_ena_q[0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|redist78_cmpReg_q[0] ), .q(\fp_pow_0002:fp_pow_inst|redist79_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist79_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist79_sticky_ena_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add62~30_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][1] ), .cin(gnd), .cout(\fp_pow_0002:fp_pow_inst|Add62~30 )); defparam \fp_pow_0002:fp_pow_inst|Add62~30_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add62~30_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add62~30_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add62~26_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][2] ), .cin(\fp_pow_0002:fp_pow_inst|Add62~30 ), .cout(\fp_pow_0002:fp_pow_inst|Add62~26 )); defparam \fp_pow_0002:fp_pow_inst|Add62~26_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add62~26_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add62~26_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add62~22_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][3] ), .cin(\fp_pow_0002:fp_pow_inst|Add62~26 ), .cout(\fp_pow_0002:fp_pow_inst|Add62~22 )); defparam \fp_pow_0002:fp_pow_inst|Add62~22_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add62~22_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add62~22_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add62~18_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][4] ), .cin(\fp_pow_0002:fp_pow_inst|Add62~22 ), .cout(\fp_pow_0002:fp_pow_inst|Add62~18 )); defparam \fp_pow_0002:fp_pow_inst|Add62~18_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add62~18_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add62~18_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add62~14_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add62~18 ), .cout(\fp_pow_0002:fp_pow_inst|Add62~14 )); defparam \fp_pow_0002:fp_pow_inst|Add62~14_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add62~14_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add62~14_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add62~10_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][6] ), .cin(\fp_pow_0002:fp_pow_inst|Add62~14 ), .cout(\fp_pow_0002:fp_pow_inst|Add62~10 )); defparam \fp_pow_0002:fp_pow_inst|Add62~10_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add62~10_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add62~10_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add62~6_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add62~10 ), .cout(\fp_pow_0002:fp_pow_inst|Add62~6 )); defparam \fp_pow_0002:fp_pow_inst|Add62~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add62~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add62~6_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add62~1_I ( .cin(\fp_pow_0002:fp_pow_inst|Add62~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add62~1 )); defparam \fp_pow_0002:fp_pow_inst|Add62~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add62~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add62~1_I .lut_mask = "0000FFFF0000FFFF"; dffeas \fp_pow_0002:fp_pow_inst|xInZO_uid159_fpPowrTest_o[10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add62~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|xInZO_uid159_fpPowrTest_o[10] )); defparam \fp_pow_0002:fp_pow_inst|xInZO_uid159_fpPowrTest_o[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|xInZO_uid159_fpPowrTest_o[10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[17][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__xInZO_uid159_fpPowrTest_o[10] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[17][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[17][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[17][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[17][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[17][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[17][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[17][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[17][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[17][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[16][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[17][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[16][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[16][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[16][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[15][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[16][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[15][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[15][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[15][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[14][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[15][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[14][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[14][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[14][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[13][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[14][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[13][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[13][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[13][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[12][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[13][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[12][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[12][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[12][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[11][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[12][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[11][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[11][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[11][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[10][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[11][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[10][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[10][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[10][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[9][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[10][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[9][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[9][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[9][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[8][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[9][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[8][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[8][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[8][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[7][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[8][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[7][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[7][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[7][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[6][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[7][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[6][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[6][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[6][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[5][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[6][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[5][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[5][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[5][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[4][0]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|__ALT_INV__delay_signals[5][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[4][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[4][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[4][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[4][0]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[4][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[4][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[4][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[4][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[4][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[3][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[4][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[3][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[3][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[3][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[3][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist80|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|xInZOZPos_uid161_fpPowrTest_q_i[0]~I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist80|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|xInZOZPos_uid161_fpPowrTest_q_i[0] )); defparam \fp_pow_0002:fp_pow_inst|xInZOZPos_uid161_fpPowrTest_q_i[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|xInZOZPos_uid161_fpPowrTest_q_i[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|xInZOZPos_uid161_fpPowrTest_q_i[0]~I .lut_mask = "0F0F0F0F00000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:xInZOZPos_uid161_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|xInZOZPos_uid161_fpPowrTest_q_i[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:xInZOZPos_uid161_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:xInZOZPos_uid161_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:xInZOZPos_uid161_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "FFFFFFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[1] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~DUPLICATE ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[4] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist79_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1511,portadatain_unconnected_wire_1512,portadatain_unconnected_wire_1513,portadatain_unconnected_wire_1514,portadatain_unconnected_wire_1515,portadatain_unconnected_wire_1516,portadatain_unconnected_wire_1517, portadatain_unconnected_wire_1518,portadatain_unconnected_wire_1519,portadatain_unconnected_wire_1520,portadatain_unconnected_wire_1521,portadatain_unconnected_wire_1522,portadatain_unconnected_wire_1523,portadatain_unconnected_wire_1524, portadatain_unconnected_wire_1525,portadatain_unconnected_wire_1526,portadatain_unconnected_wire_1527,portadatain_unconnected_wire_1528,portadatain_unconnected_wire_1529,\fp_pow_0002:fp_pow_inst|dspba_delay:xInZOZPos_uid161_fpPowrTest_delay|delay_signals[0][0] }), .portaaddr({portaaddr_unconnected_wire_1530,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~DUPLICATE , \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1531,\fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_depth = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .last_address = 22; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|infCase2_uid192_fpPowrTest_q_i[0]~I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist130_outputreg|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|infCase2_uid192_fpPowrTest_q_i[0] )); defparam \fp_pow_0002:fp_pow_inst|infCase2_uid192_fpPowrTest_q_i[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|infCase2_uid192_fpPowrTest_q_i[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|infCase2_uid192_fpPowrTest_q_i[0]~I .lut_mask = "0000000000030003"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:infCase2_uid192_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|infCase2_uid192_fpPowrTest_q_i[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:infCase2_uid192_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:infCase2_uid192_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:infCase2_uid192_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist97_sticky_ena_q[0]~feeder_I ( .combout(\fp_pow_0002:fp_pow_inst|redist97_sticky_ena_q[0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist97_sticky_ena_q[0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist97_sticky_ena_q[0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist97_sticky_ena_q[0]~feeder_I .lut_mask = "FFFFFFFFFFFFFFFF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add52~0_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[1] ), .combout(\fp_pow_0002:fp_pow_inst|Add52~0 )); defparam \fp_pow_0002:fp_pow_inst|Add52~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add52~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add52~0_I .lut_mask = "CC33CC33CC33CC33"; dffeas \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add52~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_eq ), .q(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[1] )); defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[1]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add52~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_eq ), .q(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[1]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[1]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[1]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[1]~DUPLICATE_I .created_from = "Q(redist75_replace_rdcnt_i[1])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i~0_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_eq ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[2] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[1]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i~0 )); defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i~0_I .lut_mask = "0FF00FF0CF30CF30"; dffeas \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[2] )); defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[2]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[2]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[2]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[2]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[2]~DUPLICATE_I .created_from = "Q(redist75_replace_rdcnt_i[2])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[0]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[1] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_eq ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[3] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i~1 )); defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i~1_I .lut_mask = "0FF00FF020DF20DF"; dffeas \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[3] )); defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal21~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[0]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[1] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[2] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[4] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[3] ), .combout(\fp_pow_0002:fp_pow_inst|Equal21~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal21~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal21~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal21~0_I .lut_mask = "0020002000000000"; dffeas \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_eq~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal21~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_eq )); defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_eq~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_eq~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[0]~3 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_eq ), .q(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[0] )); defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[0]~3_I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[0] ), .combout(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[0]~3 )); defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[0]~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[0]~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[0]~3_I .lut_mask = "FF00FF00FF00FF00"; dffeas \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[0]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[0]~3 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_eq ), .q(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[0]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[0]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[0]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[0]~DUPLICATE_I .created_from = "Q(redist75_replace_rdcnt_i[0])"; dffeas \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[3]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[3]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[3]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[3]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[3]~DUPLICATE_I .created_from = "Q(redist75_replace_rdcnt_i[3])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4]~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[0]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[1] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[2] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_eq ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[4] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[3]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4]~2 )); defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4]~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4]~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4]~2_I .lut_mask = "000FFFF002FFFD00"; dffeas \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4]~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4] )); defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal20~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[4] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[1] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[2] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[3] ), .combout(\fp_pow_0002:fp_pow_inst|Equal20~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal20~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal20~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal20~0_I .lut_mask = "0000101000000000"; dffeas \fp_pow_0002:fp_pow_inst|redist75_cmpReg_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal20~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist75_cmpReg_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist75_cmpReg_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist75_cmpReg_q[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist97_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist97_sticky_ena_q[0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|redist75_cmpReg_q[0] ), .q(\fp_pow_0002:fp_pow_inst|redist97_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist97_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist97_sticky_ena_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q[0]~feeder_I ( .combout(\fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q[0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q[0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q[0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q[0]~feeder_I .lut_mask = "FFFFFFFFFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[0]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[0] )); defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[0]~0_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist9_replace_rdcnt_eq ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist9_replace_rdcnt_i[0] ), .combout(\fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[0]~0_I .lut_mask = "CC33CC33CC33CC33"; dffeas \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[0]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[0]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[0]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[0]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[0]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[0]~DUPLICATE_I .created_from = "Q(redist9_replace_rdcnt_i[0])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal16~0_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist9_replace_rdcnt_i[1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist9_replace_rdcnt_i[0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Equal16~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal16~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal16~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal16~0_I .lut_mask = "F000F000F000F000"; dffeas \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_eq~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal16~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_eq )); defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_eq~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_eq~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i~1_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist9_replace_rdcnt_eq ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist9_replace_rdcnt_i[0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist9_replace_rdcnt_i[1] ), .combout(\fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i~1 )); defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i~1_I .lut_mask = "F3F30C0CF3F30C0C"; dffeas \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[1] )); defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal15~0_I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist9_replace_rdcnt_i[1] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist9_replace_rdcnt_i[0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Equal15~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal15~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal15~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal15~0_I .lut_mask = "000000FF000000FF"; dffeas \fp_pow_0002:fp_pow_inst|redist9_cmpReg_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal15~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist9_cmpReg_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist9_cmpReg_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist9_cmpReg_q[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q[0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|redist9_cmpReg_q[0] ), .q(\fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][1]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[1][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][1]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][1]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][1]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist135|delay_signals[0][1]~DUPLICATE_I .created_from = "Q(delay_signals[0][1])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add13~1_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][0] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add13~1 ), .cout(\fp_pow_0002:fp_pow_inst|Add13~2 )); defparam \fp_pow_0002:fp_pow_inst|Add13~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add13~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add13~1_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add13~5_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .cin(\fp_pow_0002:fp_pow_inst|Add13~2 ), .sumout(\fp_pow_0002:fp_pow_inst|Add13~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add13~6 )); defparam \fp_pow_0002:fp_pow_inst|Add13~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add13~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add13~5_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add13~9_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][2] ), .cin(\fp_pow_0002:fp_pow_inst|Add13~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add13~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add13~10 )); defparam \fp_pow_0002:fp_pow_inst|Add13~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add13~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add13~9_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add13~13_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][3] ), .cin(\fp_pow_0002:fp_pow_inst|Add13~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add13~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add13~14 )); defparam \fp_pow_0002:fp_pow_inst|Add13~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add13~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add13~13_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add13~17_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][4] ), .cin(\fp_pow_0002:fp_pow_inst|Add13~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add13~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add13~18 )); defparam \fp_pow_0002:fp_pow_inst|Add13~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add13~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add13~17_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add13~21_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add13~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add13~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add13~22 )); defparam \fp_pow_0002:fp_pow_inst|Add13~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add13~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add13~21_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add13~29_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][6] ), .cin(\fp_pow_0002:fp_pow_inst|Add13~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add13~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add13~30 )); defparam \fp_pow_0002:fp_pow_inst|Add13~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add13~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add13~29_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add13~33_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist135|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add13~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add13~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add13~34 )); defparam \fp_pow_0002:fp_pow_inst|Add13~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add13~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add13~33_I .lut_mask = "00000000000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add13~25_I ( .cin(\fp_pow_0002:fp_pow_inst|Add13~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add13~25 )); defparam \fp_pow_0002:fp_pow_inst|Add13~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add13~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add13~25_I .lut_mask = "0000FFFF0000FFFF"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[46]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add13~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[46] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[46]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[46]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux0~0_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~33 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~25 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~29 ), .combout(\fp_pow_0002:fp_pow_inst|Mux0~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux0~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux0~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux0~0_I .lut_mask = "00000F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[45]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux0~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[45] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[45]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[45]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux1~0_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~29 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~25 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~33 ), .combout(\fp_pow_0002:fp_pow_inst|Mux1~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux1~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux1~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux1~0_I .lut_mask = "0000FFFFF0F00F0F"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[44]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux1~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[44] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[44]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[44]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~31_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~31 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~31_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~31_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~31_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][43]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~31 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][43] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][43]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][43]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux2~0_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~33 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~25 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~29 ), .combout(\fp_pow_0002:fp_pow_inst|Mux2~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux2~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux2~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux2~0_I .lut_mask = "00000F0FF0F0F0F0"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[43]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux2~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[43] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[43]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[43]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~28_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~28 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~28_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~28_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~28_I .lut_mask = "03030303F0F0F0E0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][42]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~28 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][42] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][42]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux3~0_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~29 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~25 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~33 ), .combout(\fp_pow_0002:fp_pow_inst|Mux3~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux3~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux3~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux3~0_I .lut_mask = "00000F0FF0F00F0F"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[42]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux3~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[42] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[42]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~32_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~32 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~32_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~32_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~32_I .lut_mask = "1177899915768999"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][41]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~32 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][41] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][41]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux4~0_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~29 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~25 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~33 ), .combout(\fp_pow_0002:fp_pow_inst|Mux4~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux4~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux4~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux4~0_I .lut_mask = "33FF33FFCC00CC00"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[41]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux4~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[41] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[41]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~33_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~33 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~33_I .lut_mask = "3D3B03C003C2DCFC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][40]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][40] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][40]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux5~0_I ( .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~25 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~29 ), .combout(\fp_pow_0002:fp_pow_inst|Mux5~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux5~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux5~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux5~0_I .lut_mask = "0000FFFFFFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[40]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux5~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[40] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[40]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~34_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~34 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~34_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~34_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~34_I .lut_mask = "496C26B6B293D94D"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][39]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~34 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][39] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][39]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~35_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~35 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~35_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~35_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~35_I .lut_mask = "2D5A942D295AB469"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][38]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~35 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][38] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][38]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~29_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~29 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~29_I .lut_mask = "36C33493C349D3C9"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][37] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][37]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~30_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~30 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~30_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~30_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~30_I .lut_mask = "554AA9555AA955AA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][36]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~30 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][36] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][36]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~23_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~23 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~23_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~23_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~23_I .lut_mask = "5A5B2D2DB0D24B4B"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~23 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][35]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux6~0_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~29 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~25 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~33 ), .combout(\fp_pow_0002:fp_pow_inst|Mux6~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux6~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux6~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux6~0_I .lut_mask = "0F0F0000FFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux6~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[34] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~24_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~24 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~24_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~24_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~24_I .lut_mask = "15769999EA99666E"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~24 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~25_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~25 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~25_I .lut_mask = "771008EF338CCCF7"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~26_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~26 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~26_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~26_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~26_I .lut_mask = "43D6C29C6BC263C6"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~26 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~27_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~27 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~27_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~27_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~27_I .lut_mask = "6A15A95E57A95A85"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~27 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux7~0_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~33 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~25 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~29 ), .combout(\fp_pow_0002:fp_pow_inst|Mux7~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux7~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux7~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux7~0_I .lut_mask = "00000F0F0000FFFF"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux7~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[31] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~16_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~16 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~16_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~16_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~16_I .lut_mask = "34B0C34BF2D30F2D"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~16 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux8~0_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~29 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~25 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~33 ), .combout(\fp_pow_0002:fp_pow_inst|Mux8~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux8~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux8~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux8~0_I .lut_mask = "0000F0F0FFFF0F0F"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux8~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[30] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~18_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~18 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~18_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~18_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~18_I .lut_mask = "40BF2F40F40F03F4"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~18 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~19_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~19 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~19_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~19_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~19_I .lut_mask = "2DF00F2FD20BF0D0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~19 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~20_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~20 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~20_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~20_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~20_I .lut_mask = "0FF0C3380FE1C378"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~20 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~21_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~21 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~21_I .lut_mask = "0F0FF0E10F1AF0A5"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~22_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~22 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~22_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~22_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~22_I .lut_mask = "5555555255554AAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~22 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~17_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~17 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~17_I .lut_mask = "05FA1FE007F81FA0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~10_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~10 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~10_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~10_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~10_I .lut_mask = "5544222AABBBDDD5"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~10 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~11_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~11 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~11_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~11_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~11_I .lut_mask = "1C1C183863E3E7C7"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~11 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~12_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~12 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~12_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~12_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~12_I .lut_mask = "3B2244DD00CCFF33"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~12 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~13_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~13 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~13_I .lut_mask = "4C663399CC663399"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~14_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~14 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~14_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~14_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~14_I .lut_mask = "700FF00FF00FF00F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~14 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~15_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~15 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~15_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~15_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~15_I .lut_mask = "7FFFFFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~15 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~5 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~5_I .lut_mask = "7FFF0000FFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux9~0_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~29 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~25 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~33 ), .combout(\fp_pow_0002:fp_pow_inst|Mux9~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux9~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux9~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux9~0_I .lut_mask = "0F0FF0F0FFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux9~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[17] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~6_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~6 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~6_I .lut_mask = "7FFFFFFFFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~6 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~7_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~7 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~7_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~7_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~7_I .lut_mask = "7FFF0000FFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~7 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~8_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~8 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~8_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~8_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~8_I .lut_mask = "7FFF0000FFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~8 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~9_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~9 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~9_I .lut_mask = "7FFF0000FFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~36_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~36 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~36_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~36_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~36_I .lut_mask = "7FFFFFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~36 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux10~0_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~29 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~33 ), .combout(\fp_pow_0002:fp_pow_inst|Mux10~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux10~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux10~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux10~0_I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux10~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[10] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add13~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[9] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid222_eLn2_uid54_fpPowrTest_q[9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~149_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][17] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[9] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add14~149 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~150 )); defparam \fp_pow_0002:fp_pow_inst|Add14~149_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~149_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~149_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~145_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][18] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[10] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~150 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~145 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~146 )); defparam \fp_pow_0002:fp_pow_inst|Add14~145_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~145_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~145_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~141_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][11] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[17] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~146 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~141 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~142 )); defparam \fp_pow_0002:fp_pow_inst|Add14~141_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~141_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~141_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~25_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][12] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[34] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~142 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~26 )); defparam \fp_pow_0002:fp_pow_inst|Add14~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~25_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~21_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][13] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[34] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~22 )); defparam \fp_pow_0002:fp_pow_inst|Add14~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~21_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~17_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][14] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[34] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~18 )); defparam \fp_pow_0002:fp_pow_inst|Add14~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~17_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~13_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][16] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[42] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~14 )); defparam \fp_pow_0002:fp_pow_inst|Add14~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~13_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~9_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][16] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[43] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~10 )); defparam \fp_pow_0002:fp_pow_inst|Add14~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~9_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~5_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][17] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[17] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~6 )); defparam \fp_pow_0002:fp_pow_inst|Add14~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~5_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~49_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][18] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[34] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~50 )); defparam \fp_pow_0002:fp_pow_inst|Add14~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~49_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~45_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][19] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[34] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~46 )); defparam \fp_pow_0002:fp_pow_inst|Add14~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~45_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~41_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][20] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[34] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~42 )); defparam \fp_pow_0002:fp_pow_inst|Add14~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~41_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~37_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[34] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][21] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~38 )); defparam \fp_pow_0002:fp_pow_inst|Add14~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~37_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~33_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][22] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[34] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~34 )); defparam \fp_pow_0002:fp_pow_inst|Add14~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~33_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~29_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[42] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][23] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~30 )); defparam \fp_pow_0002:fp_pow_inst|Add14~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~29_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~57_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][24] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[43] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~57 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~58 )); defparam \fp_pow_0002:fp_pow_inst|Add14~57_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~57_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~57_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~77_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][25] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[44] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~58 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~78 )); defparam \fp_pow_0002:fp_pow_inst|Add14~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~77_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~73_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][26] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[45] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~73 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~74 )); defparam \fp_pow_0002:fp_pow_inst|Add14~73_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~73_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~73_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~69_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[46] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][27] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~74 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~69 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~70 )); defparam \fp_pow_0002:fp_pow_inst|Add14~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~69_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~65_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[46] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][28] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~70 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~65 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~66 )); defparam \fp_pow_0002:fp_pow_inst|Add14~65_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~65_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~65_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~61_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][29] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[40] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~66 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~62 )); defparam \fp_pow_0002:fp_pow_inst|Add14~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~61_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~53_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][30] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[30] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~54 )); defparam \fp_pow_0002:fp_pow_inst|Add14~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~53_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~97_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][31] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[31] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~97 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~98 )); defparam \fp_pow_0002:fp_pow_inst|Add14~97_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~97_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~97_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~93_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[40] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][32] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~98 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~93 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~94 )); defparam \fp_pow_0002:fp_pow_inst|Add14~93_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~93_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~93_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~89_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][33] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[41] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~94 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~89 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~90 )); defparam \fp_pow_0002:fp_pow_inst|Add14~89_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~89_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~89_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~85_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[34] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][34] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~90 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~85 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~86 )); defparam \fp_pow_0002:fp_pow_inst|Add14~85_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~85_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~85_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~81_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][35] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[42] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~86 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~81 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~82 )); defparam \fp_pow_0002:fp_pow_inst|Add14~81_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~81_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~81_I .lut_mask = "0000FF0000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~109_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][36] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~82 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~109 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~110 )); defparam \fp_pow_0002:fp_pow_inst|Add14~109_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~109_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~109_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~105_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[44] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][37] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~110 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~105 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~106 )); defparam \fp_pow_0002:fp_pow_inst|Add14~105_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~105_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~105_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~137_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][38] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[45] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~106 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~137 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~138 )); defparam \fp_pow_0002:fp_pow_inst|Add14~137_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~137_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~137_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~133_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][39] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[46] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~138 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~133 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~134 )); defparam \fp_pow_0002:fp_pow_inst|Add14~133_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~133_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~133_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~129_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][40] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[40] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~134 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~129 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~130 )); defparam \fp_pow_0002:fp_pow_inst|Add14~129_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~129_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~129_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~125_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][41] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[41] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~130 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~125 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~126 )); defparam \fp_pow_0002:fp_pow_inst|Add14~125_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~125_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~125_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~101_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][42] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[42] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~126 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~101 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~102 )); defparam \fp_pow_0002:fp_pow_inst|Add14~101_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~101_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~101_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~121_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[43] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~102 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~121 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~122 )); defparam \fp_pow_0002:fp_pow_inst|Add14~121_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~121_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~121_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~117_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[44] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~122 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~117 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~118 )); defparam \fp_pow_0002:fp_pow_inst|Add14~117_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~117_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~117_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~113_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[45] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~118 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~113 ), .cout(\fp_pow_0002:fp_pow_inst|Add14~114 )); defparam \fp_pow_0002:fp_pow_inst|Add14~113_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~113_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~113_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add14~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid222_eLn2_uid54_fpPowrTest_q[46] ), .cin(\fp_pow_0002:fp_pow_inst|Add14~114 ), .sumout(\fp_pow_0002:fp_pow_inst|Add14~1 )); defparam \fp_pow_0002:fp_pow_inst|Add14~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add14~1_I .lut_mask = "0000FFFF00005555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][44]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][44] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][44]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][44]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal0~0_I ( .datab(\__ALT_INV__a[26]~input0 ), .datac(\__ALT_INV__a[24]~input0 ), .datae(\__ALT_INV__a[23]~input0 ), .dataf(\__ALT_INV__a[25]~input0 ), .combout(\fp_pow_0002:fp_pow_inst|Equal0~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal0~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal0~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal0~0_I .lut_mask = "0000000003030000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal0~1_I ( .dataa(\__ALT_INV__a[29]~input0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal0~0 ), .datad(\__ALT_INV__a[28]~input0 ), .datae(\__ALT_INV__a[27]~input0 ), .dataf(\__ALT_INV__a[30]~input0 ), .combout(\fp_pow_0002:fp_pow_inst|Equal0~1 )); defparam \fp_pow_0002:fp_pow_inst|Equal0~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal0~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal0~1_I .lut_mask = "0000000500000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][0]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[2][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][0]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][0]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][0]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[1][1] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][1]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][1]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][1]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[2][1] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][1]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][2]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[2][2] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][2]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[1][2] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][2]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[1][2] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][2]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][3]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][3]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][3]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[2][3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][3]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][4]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][4]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][4]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][5]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|__ALT_INV__delay_signals[0][5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][5]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[1][5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][5]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[0][5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][5]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][5]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[1][5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][5]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[0][5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][6]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[2][6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][6]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][6]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][6]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][6]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[2][6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][6]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][7]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|__ALT_INV__delay_signals[0][7] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][7]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][7]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[2][7] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][7]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[0][7] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal0~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[1][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[2][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[1][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_inputreg|delay_signals[0][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[2][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[1][8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][8]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|__ALT_INV__delay_signals[1][8] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][8]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][8]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][8]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][8]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][8]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113|delay_signals[0][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[5] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .init_file = "fp_pow_0002_memoryC0_uid254_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_a_first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_b_first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a5 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[6] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .init_file = "fp_pow_0002_memoryC0_uid254_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_a_first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_b_first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a6 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[7] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .init_file = "fp_pow_0002_memoryC0_uid254_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_a_first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_b_first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a7 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[8] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .init_file = "fp_pow_0002_memoryC0_uid254_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_a_first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_b_first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a8 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[9] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .init_file = "fp_pow_0002_memoryC0_uid254_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_a_first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_b_first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a9 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[10] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .init_file = "fp_pow_0002_memoryC0_uid254_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_a_first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_b_first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a10 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[11] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .init_file = "fp_pow_0002_memoryC0_uid254_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_a_first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_b_first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a11 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[12] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .init_file = "fp_pow_0002_memoryC0_uid254_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_a_first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_b_first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a12 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[13] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .init_file = "fp_pow_0002_memoryC0_uid254_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_a_first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_b_first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a13 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[14] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .init_file = "fp_pow_0002_memoryC0_uid254_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_a_first_bit_number = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_b_first_bit_number = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a14 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[15] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .init_file = "fp_pow_0002_memoryC0_uid254_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_a_first_bit_number = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_b_first_bit_number = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a15 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[16] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .init_file = "fp_pow_0002_memoryC0_uid254_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_a_first_bit_number = 16; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_b_first_bit_number = 16; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a16 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[17] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .init_file = "fp_pow_0002_memoryC0_uid254_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_a_first_bit_number = 17; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_b_first_bit_number = 17; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a17 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[18] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .init_file = "fp_pow_0002_memoryC0_uid254_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_a_first_bit_number = 18; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_b_first_bit_number = 18; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a18 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[19] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .init_file = "fp_pow_0002_memoryC0_uid254_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_a_first_bit_number = 19; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_b_first_bit_number = 19; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a19 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .init_file = "fp_pow_0002_memoryC0_uid255_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_a_first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_b_first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a0 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[1] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .init_file = "fp_pow_0002_memoryC0_uid255_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_a_first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_b_first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a1 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[2] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .init_file = "fp_pow_0002_memoryC0_uid255_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_a_first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_b_first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a2 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[3] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .init_file = "fp_pow_0002_memoryC0_uid255_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_a_first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_b_first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a3 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[4] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .init_file = "fp_pow_0002_memoryC0_uid255_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_a_first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_b_first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a4 .port_b_read_during_write_mode = "new_data_no_nbe_read"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][0]~0_I ( .combout(\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][0]~0 )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][0]~0_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][1]~1_I ( .combout(\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][1]~1 )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][1]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][1]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][1]~1_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][2]~2_I ( .combout(\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][2]~2 )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][2]~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][2]~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][2]~2_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][3]~3_I ( .combout(\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][3]~3 )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][3]~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][3]~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][3]~3_I .lut_mask = "0000000000000000"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .init_file = "fp_pow_0002_memoryC3_uid263_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_a_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_a_first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_b_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_b_first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a0 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[1] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .init_file = "fp_pow_0002_memoryC3_uid263_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_a_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_a_first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_b_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_b_first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a1 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[2] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .init_file = "fp_pow_0002_memoryC3_uid263_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_a_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_a_first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_b_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_b_first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a2 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[3] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .init_file = "fp_pow_0002_memoryC3_uid263_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_a_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_a_first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_b_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_b_first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a3 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[4] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .init_file = "fp_pow_0002_memoryC3_uid263_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_a_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_a_first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_b_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_b_first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a4 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[5] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .init_file = "fp_pow_0002_memoryC3_uid263_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_a_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_a_first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_b_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_b_first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a5 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[6] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .init_file = "fp_pow_0002_memoryC3_uid263_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_a_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_a_first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_b_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_b_first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a6 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[7] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .init_file = "fp_pow_0002_memoryC3_uid263_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_a_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_a_first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_b_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_b_first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a7 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[8] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .init_file = "fp_pow_0002_memoryC3_uid263_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_a_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_a_first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_b_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_b_first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a8 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[9] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .init_file = "fp_pow_0002_memoryC3_uid263_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_a_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_a_first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_b_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_b_first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a9 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[10] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .init_file = "fp_pow_0002_memoryC3_uid263_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_a_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_a_first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_b_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_b_first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a10 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[11] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .init_file = "fp_pow_0002_memoryC3_uid263_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_a_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_a_first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_b_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_b_first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a11 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[12] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .init_file = "fp_pow_0002_memoryC3_uid263_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_a_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_a_first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_b_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_b_first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a12 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[13] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .init_file = "fp_pow_0002_memoryC3_uid263_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_a_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_a_first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_b_logical_ram_width = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_b_first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|ram_block2a13 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_mac \fp_pow_0002:fp_pow_inst|Mult0~8_I ( .sub(gnd), .negate(gnd), .ax({ax_unconnected_wire_1532,ax_unconnected_wire_1533,ax_unconnected_wire_1534,ax_unconnected_wire_1535,ax_unconnected_wire_1536,ax_unconnected_wire_1537,ax_unconnected_wire_1538,ax_unconnected_wire_1539,ax_unconnected_wire_1540, \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[13] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[13] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[13] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[13] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[13] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[12] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[11] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[10] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[9] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[8] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[7] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[6] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[5] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid263_natLogTabGen_lutmem_dmem|altera_syncram_p5m3:auto_generated|altsyncram_uve4:altsyncram1|q_b[0] }), .ay({ay_unconnected_wire_1541,ay_unconnected_wire_1542,ay_unconnected_wire_1543,ay_unconnected_wire_1544,ay_unconnected_wire_1545,ay_unconnected_wire_1546,ay_unconnected_wire_1547,ay_unconnected_wire_1548,ay_unconnected_wire_1549,ay_unconnected_wire_1550, ay_unconnected_wire_1551,ay_unconnected_wire_1552,ay_unconnected_wire_1553,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][14] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][13]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][12] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][11] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][10] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][9] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][7] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][4] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][3]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][1] }), .clk({clk_unconnected_wire_1554,clk_unconnected_wire_1555,\clk~CLKENA0 }), .aclr({\areset~CLKENA0 ,\areset~CLKENA0 }), .ena({ena_unconnected_wire_1556,ena_unconnected_wire_1557,\vcc }), .resulta({\fp_pow_0002:fp_pow_inst|Mult0~57 ,\fp_pow_0002:fp_pow_inst|Mult0~56 ,\fp_pow_0002:fp_pow_inst|Mult0~55 ,\fp_pow_0002:fp_pow_inst|Mult0~54 ,\fp_pow_0002:fp_pow_inst|Mult0~53 ,\fp_pow_0002:fp_pow_inst|Mult0~52 ,\fp_pow_0002:fp_pow_inst|Mult0~51 , \fp_pow_0002:fp_pow_inst|Mult0~50 ,\fp_pow_0002:fp_pow_inst|Mult0~49 ,\fp_pow_0002:fp_pow_inst|Mult0~48 ,\fp_pow_0002:fp_pow_inst|Mult0~47 ,\fp_pow_0002:fp_pow_inst|Mult0~46 ,\fp_pow_0002:fp_pow_inst|Mult0~45 ,\fp_pow_0002:fp_pow_inst|Mult0~44 , \fp_pow_0002:fp_pow_inst|Mult0~43 ,\fp_pow_0002:fp_pow_inst|Mult0~42 ,\fp_pow_0002:fp_pow_inst|Mult0~41 ,\fp_pow_0002:fp_pow_inst|Mult0~40 ,\fp_pow_0002:fp_pow_inst|Mult0~39 ,\fp_pow_0002:fp_pow_inst|Mult0~38 ,\fp_pow_0002:fp_pow_inst|Mult0~37 , \fp_pow_0002:fp_pow_inst|Mult0~36 ,\fp_pow_0002:fp_pow_inst|Mult0~35 ,\fp_pow_0002:fp_pow_inst|Mult0~34 ,\fp_pow_0002:fp_pow_inst|Mult0~33 ,\fp_pow_0002:fp_pow_inst|Mult0~32 ,\fp_pow_0002:fp_pow_inst|Mult0~31 ,\fp_pow_0002:fp_pow_inst|Mult0~30 , \fp_pow_0002:fp_pow_inst|Mult0~29 ,\fp_pow_0002:fp_pow_inst|Mult0~28 ,\fp_pow_0002:fp_pow_inst|Mult0~27 ,\fp_pow_0002:fp_pow_inst|Mult0~26 ,\fp_pow_0002:fp_pow_inst|Mult0~25 ,\fp_pow_0002:fp_pow_inst|Mult0~24 ,\fp_pow_0002:fp_pow_inst|Mult0~23 , \fp_pow_0002:fp_pow_inst|Mult0~22 ,\fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][27] ,\fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][26] , \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][25] ,\fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][24] ,\fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][23] , \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][22] ,\fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][21] ,\fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][20] , \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][19] ,\fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][18] ,\fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][17] , \fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][16] ,\fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][15] ,\fp_pow_0002:fp_pow_inst|prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][14] , \fp_pow_0002:fp_pow_inst|Mult0~21 ,\fp_pow_0002:fp_pow_inst|Mult0~20 ,\fp_pow_0002:fp_pow_inst|Mult0~19 ,\fp_pow_0002:fp_pow_inst|Mult0~18 ,\fp_pow_0002:fp_pow_inst|Mult0~17 ,\fp_pow_0002:fp_pow_inst|Mult0~16 ,\fp_pow_0002:fp_pow_inst|Mult0~15 , \fp_pow_0002:fp_pow_inst|Mult0~14 ,\fp_pow_0002:fp_pow_inst|Mult0~13 ,\fp_pow_0002:fp_pow_inst|Mult0~12 ,\fp_pow_0002:fp_pow_inst|Mult0~11 ,\fp_pow_0002:fp_pow_inst|Mult0~10 ,\fp_pow_0002:fp_pow_inst|Mult0~9 ,\fp_pow_0002:fp_pow_inst|Mult0~8 })); defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .signed_max = "true"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .signed_may = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .signed_mbx = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .signed_mby = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .preadder_subtract_a = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .preadder_subtract_b = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .ay_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .by_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .delay_scan_out_ay = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .delay_scan_out_by = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .use_chainadder = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .enable_double_accum = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .operation_mode = "M18X18_FULL"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .operand_source_max = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .operand_source_may = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .operand_source_mbx = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .operand_source_mby = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .ax_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .ay_scan_in_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .az_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .bx_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .by_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .bz_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .coef_sel_a_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .coef_sel_b_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .sub_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .negate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .accumulate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .load_const_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .output_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .coef_a_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .coef_a_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .coef_a_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .coef_a_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .coef_a_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .coef_a_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .coef_a_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .coef_a_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .coef_b_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .coef_b_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .coef_b_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .coef_b_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .coef_b_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .coef_b_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .coef_b_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .coef_b_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .ax_width = 18; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .ay_scan_in_width = 14; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .mode_sub_location = 0; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .load_const_value = 0; defparam \fp_pow_0002:fp_pow_inst|Mult0~8_I .result_a_width = 64; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist68|delay_signals[0][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][14] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist68|delay_signals[0][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist68|delay_signals[0][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist68|delay_signals[0][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist68|delay_signals[0][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist68|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist68|delay_signals[0][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist68|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist68|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist68|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .init_file = "fp_pow_0002_memoryC2_uid260_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_a_first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_b_first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a0 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[1] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .init_file = "fp_pow_0002_memoryC2_uid260_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_a_first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_b_first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a1 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[2] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .init_file = "fp_pow_0002_memoryC2_uid260_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_a_first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_b_first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a2 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[3] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .init_file = "fp_pow_0002_memoryC2_uid260_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_a_first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_b_first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a3 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[4] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .init_file = "fp_pow_0002_memoryC2_uid260_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_a_first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_b_first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a4 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[5] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .init_file = "fp_pow_0002_memoryC2_uid260_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_a_first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_b_first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a5 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[6] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .init_file = "fp_pow_0002_memoryC2_uid260_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_a_first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_b_first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a6 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[7] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .init_file = "fp_pow_0002_memoryC2_uid260_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_a_first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_b_first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a7 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[8] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .init_file = "fp_pow_0002_memoryC2_uid260_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_a_first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_b_first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a8 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[9] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .init_file = "fp_pow_0002_memoryC2_uid260_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_a_first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_b_first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a9 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[10] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .init_file = "fp_pow_0002_memoryC2_uid260_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_a_first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_b_first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a10 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[11] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .init_file = "fp_pow_0002_memoryC2_uid260_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_a_first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_b_first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a11 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[12] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .init_file = "fp_pow_0002_memoryC2_uid260_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_a_first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_b_first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a12 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[13] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .init_file = "fp_pow_0002_memoryC2_uid260_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_a_first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_b_first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a13 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[14] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .init_file = "fp_pow_0002_memoryC2_uid260_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_a_first_bit_number = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_b_first_bit_number = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a14 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[15] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .init_file = "fp_pow_0002_memoryC2_uid260_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_a_first_bit_number = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_b_first_bit_number = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a15 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[16] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .init_file = "fp_pow_0002_memoryC2_uid260_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_a_first_bit_number = 16; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_b_first_bit_number = 16; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a16 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[17] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .init_file = "fp_pow_0002_memoryC2_uid260_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_a_first_bit_number = 17; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_b_first_bit_number = 17; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a17 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[18] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .init_file = "fp_pow_0002_memoryC2_uid260_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_a_first_bit_number = 18; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_b_first_bit_number = 18; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a18 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|q_b[19] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .init_file = "fp_pow_0002_memoryC2_uid260_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_a_first_bit_number = 19; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_b_first_bit_number = 19; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|ram_block2a19 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~1_I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][15] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add1~1 ), .cout(\fp_pow_0002:fp_pow_inst|Add1~2 )); defparam \fp_pow_0002:fp_pow_inst|Add1~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~1_I .lut_mask = "0000F0F000003333"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[0] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~5_I ( .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][16] ), .cin(\fp_pow_0002:fp_pow_inst|Add1~2 ), .sumout(\fp_pow_0002:fp_pow_inst|Add1~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add1~6 )); defparam \fp_pow_0002:fp_pow_inst|Add1~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~5_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[1] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~9_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][17] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[2] ), .cin(\fp_pow_0002:fp_pow_inst|Add1~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add1~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add1~10 )); defparam \fp_pow_0002:fp_pow_inst|Add1~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~9_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[2] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~13_I ( .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[3] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][18] ), .cin(\fp_pow_0002:fp_pow_inst|Add1~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add1~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add1~14 )); defparam \fp_pow_0002:fp_pow_inst|Add1~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~13_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[3] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~17_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][19] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[4] ), .cin(\fp_pow_0002:fp_pow_inst|Add1~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add1~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add1~18 )); defparam \fp_pow_0002:fp_pow_inst|Add1~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~17_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[4] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~21_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][20] ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[5] ), .cin(\fp_pow_0002:fp_pow_inst|Add1~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add1~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add1~22 )); defparam \fp_pow_0002:fp_pow_inst|Add1~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~21_I .lut_mask = "0000CCCC00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[5] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~25_I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[6] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][21] ), .cin(\fp_pow_0002:fp_pow_inst|Add1~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add1~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add1~26 )); defparam \fp_pow_0002:fp_pow_inst|Add1~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~25_I .lut_mask = "0000F0F000003333"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[6] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~29_I ( .dataa(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[7] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][22] ), .cin(\fp_pow_0002:fp_pow_inst|Add1~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add1~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add1~30 )); defparam \fp_pow_0002:fp_pow_inst|Add1~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~29_I .lut_mask = "0000F0F000005555"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[7] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~33_I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[8] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][23] ), .cin(\fp_pow_0002:fp_pow_inst|Add1~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add1~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add1~34 )); defparam \fp_pow_0002:fp_pow_inst|Add1~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~33_I .lut_mask = "0000F0F000003333"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[8] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~37_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][24] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[9] ), .cin(\fp_pow_0002:fp_pow_inst|Add1~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add1~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add1~38 )); defparam \fp_pow_0002:fp_pow_inst|Add1~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~37_I .lut_mask = "0000AAAA000000FF"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[9] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~41_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][25] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[10] ), .cin(\fp_pow_0002:fp_pow_inst|Add1~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add1~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add1~42 )); defparam \fp_pow_0002:fp_pow_inst|Add1~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~41_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[10] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~45_I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[11] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][26] ), .cin(\fp_pow_0002:fp_pow_inst|Add1~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add1~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add1~46 )); defparam \fp_pow_0002:fp_pow_inst|Add1~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~45_I .lut_mask = "0000F0F000003333"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[11] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~49_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][27] ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[12] ), .cin(\fp_pow_0002:fp_pow_inst|Add1~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add1~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add1~50 )); defparam \fp_pow_0002:fp_pow_inst|Add1~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~49_I .lut_mask = "0000FF0000000F0F"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[12] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~53_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][27] ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[13] ), .cin(\fp_pow_0002:fp_pow_inst|Add1~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add1~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add1~54 )); defparam \fp_pow_0002:fp_pow_inst|Add1~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~53_I .lut_mask = "0000AAAA00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[13] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~57_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][27] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[14] ), .cin(\fp_pow_0002:fp_pow_inst|Add1~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add1~57 ), .cout(\fp_pow_0002:fp_pow_inst|Add1~58 )); defparam \fp_pow_0002:fp_pow_inst|Add1~57_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~57_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~57_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~57 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[14] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~61_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][27] ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[15] ), .cin(\fp_pow_0002:fp_pow_inst|Add1~58 ), .sumout(\fp_pow_0002:fp_pow_inst|Add1~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add1~62 )); defparam \fp_pow_0002:fp_pow_inst|Add1~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~61_I .lut_mask = "0000AAAA00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~61 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[15] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~65_I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[16] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][27] ), .cin(\fp_pow_0002:fp_pow_inst|Add1~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add1~65 ), .cout(\fp_pow_0002:fp_pow_inst|Add1~66 )); defparam \fp_pow_0002:fp_pow_inst|Add1~65_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~65_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~65_I .lut_mask = "0000F0F000003333"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~65 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[16] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~69_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][27] ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[17] ), .cin(\fp_pow_0002:fp_pow_inst|Add1~66 ), .sumout(\fp_pow_0002:fp_pow_inst|Add1~69 ), .cout(\fp_pow_0002:fp_pow_inst|Add1~70 )); defparam \fp_pow_0002:fp_pow_inst|Add1~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~69_I .lut_mask = "0000FF0000005555"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~69 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[17] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~73_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][27] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[18] ), .cin(\fp_pow_0002:fp_pow_inst|Add1~70 ), .sumout(\fp_pow_0002:fp_pow_inst|Add1~73 ), .cout(\fp_pow_0002:fp_pow_inst|Add1~74 )); defparam \fp_pow_0002:fp_pow_inst|Add1~73_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~73_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~73_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~73 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[18] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~77_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][27] ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid260_natLogTabGen_lutmem_dmem|altera_syncram_f5m3:auto_generated|altsyncram_kve4:altsyncram1|__ALT_INV__q_b[19] ), .cin(\fp_pow_0002:fp_pow_inst|Add1~74 ), .sumout(\fp_pow_0002:fp_pow_inst|Add1~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add1~78 )); defparam \fp_pow_0002:fp_pow_inst|Add1~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~77_I .lut_mask = "0000FF0000005555"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~77 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[19] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[19]~I .is_wysiwyg = "true"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|q_b[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .init_file = "fp_pow_0002_memoryC2_uid261_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_a_logical_ram_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_a_first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_b_logical_ram_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_b_first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a0 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][6]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist111|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|q_b[1] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .init_file = "fp_pow_0002_memoryC2_uid261_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_a_logical_ram_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_a_first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_b_logical_ram_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_b_first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|ram_block2a1 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~81_I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|__ALT_INV__q_b[0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][27] ), .cin(\fp_pow_0002:fp_pow_inst|Add1~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add1~81 ), .cout(\fp_pow_0002:fp_pow_inst|Add1~82 )); defparam \fp_pow_0002:fp_pow_inst|Add1~81_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~81_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~81_I .lut_mask = "0000F0F000003333"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~81 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[20] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~85_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][27] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|__ALT_INV__q_b[1] ), .cin(\fp_pow_0002:fp_pow_inst|Add1~82 ), .sumout(\fp_pow_0002:fp_pow_inst|Add1~85 ), .cout(\fp_pow_0002:fp_pow_inst|Add1~86 )); defparam \fp_pow_0002:fp_pow_inst|Add1~85_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~85_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~85_I .lut_mask = "0000AAAA000000FF"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~85 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[21] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add1~89_I ( .dataa(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid261_natLogTabGen_lutmem_dmem|altera_syncram_g2m3:auto_generated|altsyncram_lse4:altsyncram1|__ALT_INV__q_b[1] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid447_pT1_uid266_natLogPolyEval_cma_s[0][27] ), .cin(\fp_pow_0002:fp_pow_inst|Add1~86 ), .sumout(\fp_pow_0002:fp_pow_inst|Add1~89 )); defparam \fp_pow_0002:fp_pow_inst|Add1~89_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~89_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add1~89_I .lut_mask = "0000F0F000005555"; dffeas \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add1~89 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[22] )); defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][0]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][0]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][1]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][1]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][2]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][2]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][2]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][2]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][2]~DUPLICATE_I .created_from = "Q(delay_signals[0][2])"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[1][3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][3]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][3]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][3]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][3]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][3]~DUPLICATE_I .created_from = "Q(delay_signals[0][3])"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][4]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][4]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][4]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][5]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][5]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][5]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][5]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][5]~DUPLICATE_I .created_from = "Q(delay_signals[0][5])"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][6]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[1][6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][6]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][6]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][6]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][7]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[0][7] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][7]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][7]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[1][7] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][7]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][7]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[0][7] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][7]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][8]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[1][8] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][8]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][8]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][8]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][8]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][8]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][9]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[1][9] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][9]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][9]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][9]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][9]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][9]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][9]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[0][9] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][9]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][9]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][9]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][9]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][9]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][11]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[1][11] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][11]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][11]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][11]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][11]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][11]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][11]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|__ALT_INV__delay_signals[0][11] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][11]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][11]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][11]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][11]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][11]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][12]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[0][12] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][12]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][12]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][12]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][12]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][12]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[1][13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist136|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][13]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[0][13] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][13]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][13]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][13]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][13]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][13]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][14]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist136|__ALT_INV__delay_signals[0][14] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][14]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][14]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][14]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][14]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][14]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[1][14] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][14] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_mac \fp_pow_0002:fp_pow_inst|Mult1~8_I ( .sub(gnd), .negate(gnd), .ax({\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[22] ,\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[22] ,\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[22] , \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[22] ,\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[21] ,\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[20] , \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[19] ,\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[18] ,\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[17] , \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[16] ,\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[15] ,\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[14] , \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[13] ,\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[12] ,\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[11] , \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[10] ,\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[9] ,\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[8] , \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[7] ,\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[6] ,\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[5] ,\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[4] , \fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[3] ,\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[2] ,\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[1] ,\fp_pow_0002:fp_pow_inst|s1sumAHighB_uid269_natLogPolyEval_o[0] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist68|delay_signals[0][0] }), .ay({ay_unconnected_wire_1558,ay_unconnected_wire_1559,ay_unconnected_wire_1560,ay_unconnected_wire_1561,ay_unconnected_wire_1562,ay_unconnected_wire_1563,ay_unconnected_wire_1564,ay_unconnected_wire_1565,ay_unconnected_wire_1566,ay_unconnected_wire_1567, ay_unconnected_wire_1568,ay_unconnected_wire_1569,\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][14] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][13] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][12] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][11] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][10] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][9] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][7] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][5]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][4] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][3]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][1] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][0] }), .clk({clk_unconnected_wire_1570,clk_unconnected_wire_1571,\clk~CLKENA0 }), .aclr({\areset~CLKENA0 ,\areset~CLKENA0 }), .ena({ena_unconnected_wire_1572,ena_unconnected_wire_1573,\vcc }), .resulta({\fp_pow_0002:fp_pow_inst|Mult1~47 ,\fp_pow_0002:fp_pow_inst|Mult1~46 ,\fp_pow_0002:fp_pow_inst|Mult1~45 ,\fp_pow_0002:fp_pow_inst|Mult1~44 ,\fp_pow_0002:fp_pow_inst|Mult1~43 ,\fp_pow_0002:fp_pow_inst|Mult1~42 ,\fp_pow_0002:fp_pow_inst|Mult1~41 , \fp_pow_0002:fp_pow_inst|Mult1~40 ,\fp_pow_0002:fp_pow_inst|Mult1~39 ,\fp_pow_0002:fp_pow_inst|Mult1~38 ,\fp_pow_0002:fp_pow_inst|Mult1~37 ,\fp_pow_0002:fp_pow_inst|Mult1~36 ,\fp_pow_0002:fp_pow_inst|Mult1~35 ,\fp_pow_0002:fp_pow_inst|Mult1~34 , \fp_pow_0002:fp_pow_inst|Mult1~33 ,\fp_pow_0002:fp_pow_inst|Mult1~32 ,\fp_pow_0002:fp_pow_inst|Mult1~31 ,\fp_pow_0002:fp_pow_inst|Mult1~30 ,\fp_pow_0002:fp_pow_inst|Mult1~29 ,\fp_pow_0002:fp_pow_inst|Mult1~28 ,\fp_pow_0002:fp_pow_inst|Mult1~27 , \fp_pow_0002:fp_pow_inst|Mult1~26 ,\fp_pow_0002:fp_pow_inst|Mult1~25 ,\fp_pow_0002:fp_pow_inst|Mult1~24 ,\fp_pow_0002:fp_pow_inst|Mult1~23 ,\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][38] , \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][37] ,\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][36] ,\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][35] , \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][34] ,\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][33] ,\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][32] , \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][31] ,\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][30] ,\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][29] , \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][28] ,\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][27] ,\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][26] , \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][25] ,\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][24] ,\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][23] , \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][22] ,\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][21] ,\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][20] , \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][19] ,\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][18] ,\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][17] , \fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][16] ,\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][15] ,\fp_pow_0002:fp_pow_inst|Mult1~22 ,\fp_pow_0002:fp_pow_inst|Mult1~21 , \fp_pow_0002:fp_pow_inst|Mult1~20 ,\fp_pow_0002:fp_pow_inst|Mult1~19 ,\fp_pow_0002:fp_pow_inst|Mult1~18 ,\fp_pow_0002:fp_pow_inst|Mult1~17 ,\fp_pow_0002:fp_pow_inst|Mult1~16 ,\fp_pow_0002:fp_pow_inst|Mult1~15 ,\fp_pow_0002:fp_pow_inst|Mult1~14 , \fp_pow_0002:fp_pow_inst|Mult1~13 ,\fp_pow_0002:fp_pow_inst|Mult1~12 ,\fp_pow_0002:fp_pow_inst|Mult1~11 ,\fp_pow_0002:fp_pow_inst|Mult1~10 ,\fp_pow_0002:fp_pow_inst|Mult1~9 ,\fp_pow_0002:fp_pow_inst|Mult1~8 })); defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .signed_max = "true"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .signed_may = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .signed_mbx = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .signed_mby = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .preadder_subtract_a = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .preadder_subtract_b = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .ay_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .by_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .delay_scan_out_ay = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .delay_scan_out_by = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .use_chainadder = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .enable_double_accum = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .operation_mode = "M27X27"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .operand_source_max = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .operand_source_may = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .operand_source_mbx = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .operand_source_mby = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .ax_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .ay_scan_in_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .az_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .bx_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .by_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .bz_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .coef_sel_a_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .coef_sel_b_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .sub_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .negate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .accumulate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .load_const_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .output_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .coef_a_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .coef_a_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .coef_a_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .coef_a_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .coef_a_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .coef_a_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .coef_a_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .coef_a_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .coef_b_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .coef_b_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .coef_b_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .coef_b_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .coef_b_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .coef_b_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .coef_b_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .coef_b_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .ax_width = 27; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .ay_scan_in_width = 15; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .mode_sub_location = 0; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .load_const_value = 0; defparam \fp_pow_0002:fp_pow_inst|Mult1~8_I .result_a_width = 64; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist67|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist67|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist67|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist67|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist67|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE_I .created_from = "Q(delay_signals[0][2])"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .init_file = "fp_pow_0002_memoryC1_uid257_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_a_first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_b_first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a0 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[1] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .init_file = "fp_pow_0002_memoryC1_uid257_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_a_first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_b_first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a1 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[2] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .init_file = "fp_pow_0002_memoryC1_uid257_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_a_first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_b_first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a2 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[13] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .init_file = "fp_pow_0002_memoryC1_uid257_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_a_first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_b_first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a13 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[14] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .init_file = "fp_pow_0002_memoryC1_uid257_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_a_first_bit_number = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_b_first_bit_number = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a14 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[15] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .init_file = "fp_pow_0002_memoryC1_uid257_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_a_first_bit_number = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_b_first_bit_number = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a15 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[16] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .init_file = "fp_pow_0002_memoryC1_uid257_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_a_first_bit_number = 16; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_b_first_bit_number = 16; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a16 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[17] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .init_file = "fp_pow_0002_memoryC1_uid257_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_a_first_bit_number = 17; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_b_first_bit_number = 17; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a17 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[18] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .init_file = "fp_pow_0002_memoryC1_uid257_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_a_first_bit_number = 18; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_b_first_bit_number = 18; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a18 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[19] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .init_file = "fp_pow_0002_memoryC1_uid257_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_a_first_bit_number = 19; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_b_first_bit_number = 19; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a19 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .init_file = "fp_pow_0002_memoryC1_uid258_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_a_logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_a_first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_b_logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_b_first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a0 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[1] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .init_file = "fp_pow_0002_memoryC1_uid258_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_a_logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_a_first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_b_logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_b_first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a1 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[2] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .init_file = "fp_pow_0002_memoryC1_uid258_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_a_logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_a_first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_b_logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_b_first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a2 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[3] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .init_file = "fp_pow_0002_memoryC1_uid258_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_a_logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_a_first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_b_logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_b_first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a3 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[4] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .init_file = "fp_pow_0002_memoryC1_uid258_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_a_logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_a_first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_b_logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_b_first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a4 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[5] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .init_file = "fp_pow_0002_memoryC1_uid258_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_a_logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_a_first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_b_logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_b_first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a5 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[6] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .init_file = "fp_pow_0002_memoryC1_uid258_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_a_logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_a_first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_b_logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_b_first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a6 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[7] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .init_file = "fp_pow_0002_memoryC1_uid258_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_a_logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_a_first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_b_logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_b_first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a7 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[8] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .init_file = "fp_pow_0002_memoryC1_uid258_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_a_logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_a_first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_b_logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_b_first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a8 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[9] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .init_file = "fp_pow_0002_memoryC1_uid258_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_a_logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_a_first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_b_logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_b_first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|ram_block2a9 .port_b_read_during_write_mode = "new_data_no_nbe_read"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][16] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~73_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][0] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add2~73 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~74 )); defparam \fp_pow_0002:fp_pow_inst|Add2~73_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~73_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~73_I .lut_mask = "0000CCCC000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~73 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][17] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[1] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~77_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][1] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~74 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~78 )); defparam \fp_pow_0002:fp_pow_inst|Add2~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~77_I .lut_mask = "0000AAAA000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~77 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~81_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][2] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~81 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~82 )); defparam \fp_pow_0002:fp_pow_inst|Add2~81_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~81_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~81_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~81 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[3] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .init_file = "fp_pow_0002_memoryC1_uid257_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_a_first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_b_first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a3 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[4] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .init_file = "fp_pow_0002_memoryC1_uid257_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_a_first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_b_first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a4 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[5] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .init_file = "fp_pow_0002_memoryC1_uid257_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_a_first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_b_first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a5 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[6] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .init_file = "fp_pow_0002_memoryC1_uid257_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_a_first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_b_first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a6 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[7] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .init_file = "fp_pow_0002_memoryC1_uid257_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_a_first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_b_first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a7 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[8] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .init_file = "fp_pow_0002_memoryC1_uid257_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_a_first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_b_first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a8 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[9] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .init_file = "fp_pow_0002_memoryC1_uid257_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_a_first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_b_first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a9 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[10] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .init_file = "fp_pow_0002_memoryC1_uid257_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_a_first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_b_first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a10 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[11] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .init_file = "fp_pow_0002_memoryC1_uid257_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_a_first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_b_first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a11 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][2]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist112|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[12] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .init_file = "fp_pow_0002_memoryC1_uid257_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_a_first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_b_first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|ram_block2a12 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][19] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~85_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][3] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~82 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~85 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~86 )); defparam \fp_pow_0002:fp_pow_inst|Add2~85_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~85_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~85_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~85 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][20] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~89_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][4] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~86 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~89 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~90 )); defparam \fp_pow_0002:fp_pow_inst|Add2~89_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~89_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~89_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~89 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][5]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][5]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][5]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][21] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][5]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~93_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~90 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~93 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~94 )); defparam \fp_pow_0002:fp_pow_inst|Add2~93_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~93_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~93_I .lut_mask = "0000AAAA000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~93 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][6]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][6]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][6]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][22] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][6]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~97_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][6] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][6] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~94 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~97 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~98 )); defparam \fp_pow_0002:fp_pow_inst|Add2~97_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~97_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~97_I .lut_mask = "0000F0F000003333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~97 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][23] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][7]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[7] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][7]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~101_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][7] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~98 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~101 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~102 )); defparam \fp_pow_0002:fp_pow_inst|Add2~101_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~101_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~101_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~101 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][8]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][24] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][8]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][8]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][8]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][8]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][8]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~105_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][8] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][8] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~102 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~105 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~106 )); defparam \fp_pow_0002:fp_pow_inst|Add2~105_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~105_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~105_I .lut_mask = "0000F0F000003333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~105 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][9]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[9] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][9]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][9]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][9]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][9]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][9]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][25] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~109_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][9] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][9] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~106 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~109 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~110 )); defparam \fp_pow_0002:fp_pow_inst|Add2~109_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~109_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~109_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~109 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][10]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][26] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][10]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][10]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][10]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][10]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][10]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~113_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][10] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][10] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~110 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~113 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~114 )); defparam \fp_pow_0002:fp_pow_inst|Add2~113_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~113_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~113_I .lut_mask = "0000F0F000005555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~113 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][11]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[11] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][11]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][11]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][11]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][11]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][11]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][11]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][27] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][11]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][11]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][11]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][11]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][11]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~117_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][11] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][11] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~114 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~117 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~118 )); defparam \fp_pow_0002:fp_pow_inst|Add2~117_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~117_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~117_I .lut_mask = "0000FF0000000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~117 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][12]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][28] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][12]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][12]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][12]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][12]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][12]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][12]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[12] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][12]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][12]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][12]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][12]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][12]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~121_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][12] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][12] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~118 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~121 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~122 )); defparam \fp_pow_0002:fp_pow_inst|Add2~121_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~121_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~121_I .lut_mask = "0000AAAA00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~121 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_a0[0][0]~0_I ( .combout(\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_a0[0][0]~0 )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_a0[0][0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_a0[0][0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_a0[0][0]~0_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_a0[0][1]~1_I ( .combout(\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_a0[0][1]~1 )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_a0[0][1]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_a0[0][1]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_a0[0][1]~1_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0]~feeder_I ( .combout(\fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0]~feeder_I .lut_mask = "FFFFFFFFFFFFFFFF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist88_cmpReg_q[0]~feeder_I ( .combout(\fp_pow_0002:fp_pow_inst|redist88_cmpReg_q[0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist88_cmpReg_q[0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist88_cmpReg_q[0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist88_cmpReg_q[0]~feeder_I .lut_mask = "FFFFFFFFFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist88_cmpReg_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist88_cmpReg_q[0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist88_cmpReg_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist88_cmpReg_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist88_cmpReg_q[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|redist88_cmpReg_q[0] ), .q(\fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0]~0_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "FFFFFFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1574,portadatain_unconnected_wire_1575,portadatain_unconnected_wire_1576,portadatain_unconnected_wire_1577,portadatain_unconnected_wire_1578,portadatain_unconnected_wire_1579,portadatain_unconnected_wire_1580, portadatain_unconnected_wire_1581,portadatain_unconnected_wire_1582,portadatain_unconnected_wire_1583,portadatain_unconnected_wire_1584,portadatain_unconnected_wire_1585,portadatain_unconnected_wire_1586,portadatain_unconnected_wire_1587, portadatain_unconnected_wire_1588,portadatain_unconnected_wire_1589,portadatain_unconnected_wire_1590,portadatain_unconnected_wire_1591,portadatain_unconnected_wire_1592,\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][0] }), .portaaddr({portaaddr_unconnected_wire_1593,portaaddr_unconnected_wire_1594,portaaddr_unconnected_wire_1595,portaaddr_unconnected_wire_1596,portaaddr_unconnected_wire_1597,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1598,portbaddr_unconnected_wire_1599,portbaddr_unconnected_wire_1600,portbaddr_unconnected_wire_1601,portbaddr_unconnected_wire_1602, \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0 .logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1603,portadatain_unconnected_wire_1604,portadatain_unconnected_wire_1605,portadatain_unconnected_wire_1606,portadatain_unconnected_wire_1607,portadatain_unconnected_wire_1608,portadatain_unconnected_wire_1609, portadatain_unconnected_wire_1610,portadatain_unconnected_wire_1611,portadatain_unconnected_wire_1612,portadatain_unconnected_wire_1613,portadatain_unconnected_wire_1614,portadatain_unconnected_wire_1615,portadatain_unconnected_wire_1616, portadatain_unconnected_wire_1617,portadatain_unconnected_wire_1618,portadatain_unconnected_wire_1619,portadatain_unconnected_wire_1620,portadatain_unconnected_wire_1621,\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][1] }), .portaaddr({portaaddr_unconnected_wire_1622,portaaddr_unconnected_wire_1623,portaaddr_unconnected_wire_1624,portaaddr_unconnected_wire_1625,portaaddr_unconnected_wire_1626,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1627,portbaddr_unconnected_wire_1628,portbaddr_unconnected_wire_1629,portbaddr_unconnected_wire_1630,portbaddr_unconnected_wire_1631, \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[1] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1 .logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1 .first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama1 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1632,portadatain_unconnected_wire_1633,portadatain_unconnected_wire_1634,portadatain_unconnected_wire_1635,portadatain_unconnected_wire_1636,portadatain_unconnected_wire_1637,portadatain_unconnected_wire_1638, portadatain_unconnected_wire_1639,portadatain_unconnected_wire_1640,portadatain_unconnected_wire_1641,portadatain_unconnected_wire_1642,portadatain_unconnected_wire_1643,portadatain_unconnected_wire_1644,portadatain_unconnected_wire_1645, portadatain_unconnected_wire_1646,portadatain_unconnected_wire_1647,portadatain_unconnected_wire_1648,portadatain_unconnected_wire_1649,portadatain_unconnected_wire_1650,\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][2] }), .portaaddr({portaaddr_unconnected_wire_1651,portaaddr_unconnected_wire_1652,portaaddr_unconnected_wire_1653,portaaddr_unconnected_wire_1654,portaaddr_unconnected_wire_1655,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1656,portbaddr_unconnected_wire_1657,portbaddr_unconnected_wire_1658,portbaddr_unconnected_wire_1659,portbaddr_unconnected_wire_1660, \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[2] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2 .logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2 .first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama2 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1661,portadatain_unconnected_wire_1662,portadatain_unconnected_wire_1663,portadatain_unconnected_wire_1664,portadatain_unconnected_wire_1665,portadatain_unconnected_wire_1666,portadatain_unconnected_wire_1667, portadatain_unconnected_wire_1668,portadatain_unconnected_wire_1669,portadatain_unconnected_wire_1670,portadatain_unconnected_wire_1671,portadatain_unconnected_wire_1672,portadatain_unconnected_wire_1673,portadatain_unconnected_wire_1674, portadatain_unconnected_wire_1675,portadatain_unconnected_wire_1676,portadatain_unconnected_wire_1677,portadatain_unconnected_wire_1678,portadatain_unconnected_wire_1679,\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][3] }), .portaaddr({portaaddr_unconnected_wire_1680,portaaddr_unconnected_wire_1681,portaaddr_unconnected_wire_1682,portaaddr_unconnected_wire_1683,portaaddr_unconnected_wire_1684,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1685,portbaddr_unconnected_wire_1686,portbaddr_unconnected_wire_1687,portbaddr_unconnected_wire_1688,portbaddr_unconnected_wire_1689, \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[3] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3 .logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3 .first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama3 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][4]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][4]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][4]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1690,portadatain_unconnected_wire_1691,portadatain_unconnected_wire_1692,portadatain_unconnected_wire_1693,portadatain_unconnected_wire_1694,portadatain_unconnected_wire_1695,portadatain_unconnected_wire_1696, portadatain_unconnected_wire_1697,portadatain_unconnected_wire_1698,portadatain_unconnected_wire_1699,portadatain_unconnected_wire_1700,portadatain_unconnected_wire_1701,portadatain_unconnected_wire_1702,portadatain_unconnected_wire_1703, portadatain_unconnected_wire_1704,portadatain_unconnected_wire_1705,portadatain_unconnected_wire_1706,portadatain_unconnected_wire_1707,portadatain_unconnected_wire_1708,\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][4] }), .portaaddr({portaaddr_unconnected_wire_1709,portaaddr_unconnected_wire_1710,portaaddr_unconnected_wire_1711,portaaddr_unconnected_wire_1712,portaaddr_unconnected_wire_1713,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1714,portbaddr_unconnected_wire_1715,portbaddr_unconnected_wire_1716,portbaddr_unconnected_wire_1717,portbaddr_unconnected_wire_1718, \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[4] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4 .logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4 .first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama4 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109|delay_signals[0][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1719,portadatain_unconnected_wire_1720,portadatain_unconnected_wire_1721,portadatain_unconnected_wire_1722,portadatain_unconnected_wire_1723,portadatain_unconnected_wire_1724,portadatain_unconnected_wire_1725, portadatain_unconnected_wire_1726,portadatain_unconnected_wire_1727,portadatain_unconnected_wire_1728,portadatain_unconnected_wire_1729,portadatain_unconnected_wire_1730,portadatain_unconnected_wire_1731,portadatain_unconnected_wire_1732, portadatain_unconnected_wire_1733,portadatain_unconnected_wire_1734,portadatain_unconnected_wire_1735,portadatain_unconnected_wire_1736,portadatain_unconnected_wire_1737,\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][5] }), .portaaddr({portaaddr_unconnected_wire_1738,portaaddr_unconnected_wire_1739,portaaddr_unconnected_wire_1740,portaaddr_unconnected_wire_1741,portaaddr_unconnected_wire_1742,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1743,portbaddr_unconnected_wire_1744,portbaddr_unconnected_wire_1745,portbaddr_unconnected_wire_1746,portbaddr_unconnected_wire_1747, \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[5] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5 .logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5 .first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama5 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1748,portadatain_unconnected_wire_1749,portadatain_unconnected_wire_1750,portadatain_unconnected_wire_1751,portadatain_unconnected_wire_1752,portadatain_unconnected_wire_1753,portadatain_unconnected_wire_1754, portadatain_unconnected_wire_1755,portadatain_unconnected_wire_1756,portadatain_unconnected_wire_1757,portadatain_unconnected_wire_1758,portadatain_unconnected_wire_1759,portadatain_unconnected_wire_1760,portadatain_unconnected_wire_1761, portadatain_unconnected_wire_1762,portadatain_unconnected_wire_1763,portadatain_unconnected_wire_1764,portadatain_unconnected_wire_1765,portadatain_unconnected_wire_1766,\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][6] }), .portaaddr({portaaddr_unconnected_wire_1767,portaaddr_unconnected_wire_1768,portaaddr_unconnected_wire_1769,portaaddr_unconnected_wire_1770,portaaddr_unconnected_wire_1771,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1772,portbaddr_unconnected_wire_1773,portbaddr_unconnected_wire_1774,portbaddr_unconnected_wire_1775,portbaddr_unconnected_wire_1776, \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[6] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6 .logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6 .first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama6 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1777,portadatain_unconnected_wire_1778,portadatain_unconnected_wire_1779,portadatain_unconnected_wire_1780,portadatain_unconnected_wire_1781,portadatain_unconnected_wire_1782,portadatain_unconnected_wire_1783, portadatain_unconnected_wire_1784,portadatain_unconnected_wire_1785,portadatain_unconnected_wire_1786,portadatain_unconnected_wire_1787,portadatain_unconnected_wire_1788,portadatain_unconnected_wire_1789,portadatain_unconnected_wire_1790, portadatain_unconnected_wire_1791,portadatain_unconnected_wire_1792,portadatain_unconnected_wire_1793,portadatain_unconnected_wire_1794,portadatain_unconnected_wire_1795,\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][7] }), .portaaddr({portaaddr_unconnected_wire_1796,portaaddr_unconnected_wire_1797,portaaddr_unconnected_wire_1798,portaaddr_unconnected_wire_1799,portaaddr_unconnected_wire_1800,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1801,portbaddr_unconnected_wire_1802,portbaddr_unconnected_wire_1803,portbaddr_unconnected_wire_1804,portbaddr_unconnected_wire_1805, \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[7] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7 .logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7 .first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama7 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1806,portadatain_unconnected_wire_1807,portadatain_unconnected_wire_1808,portadatain_unconnected_wire_1809,portadatain_unconnected_wire_1810,portadatain_unconnected_wire_1811,portadatain_unconnected_wire_1812, portadatain_unconnected_wire_1813,portadatain_unconnected_wire_1814,portadatain_unconnected_wire_1815,portadatain_unconnected_wire_1816,portadatain_unconnected_wire_1817,portadatain_unconnected_wire_1818,portadatain_unconnected_wire_1819, portadatain_unconnected_wire_1820,portadatain_unconnected_wire_1821,portadatain_unconnected_wire_1822,portadatain_unconnected_wire_1823,portadatain_unconnected_wire_1824,\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][8] }), .portaaddr({portaaddr_unconnected_wire_1825,portaaddr_unconnected_wire_1826,portaaddr_unconnected_wire_1827,portaaddr_unconnected_wire_1828,portaaddr_unconnected_wire_1829,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1830,portbaddr_unconnected_wire_1831,portbaddr_unconnected_wire_1832,portbaddr_unconnected_wire_1833,portbaddr_unconnected_wire_1834, \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[8] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8 .logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8 .first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama8 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1835,portadatain_unconnected_wire_1836,portadatain_unconnected_wire_1837,portadatain_unconnected_wire_1838,portadatain_unconnected_wire_1839,portadatain_unconnected_wire_1840,portadatain_unconnected_wire_1841, portadatain_unconnected_wire_1842,portadatain_unconnected_wire_1843,portadatain_unconnected_wire_1844,portadatain_unconnected_wire_1845,portadatain_unconnected_wire_1846,portadatain_unconnected_wire_1847,portadatain_unconnected_wire_1848, portadatain_unconnected_wire_1849,portadatain_unconnected_wire_1850,portadatain_unconnected_wire_1851,portadatain_unconnected_wire_1852,portadatain_unconnected_wire_1853,\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][9] }), .portaaddr({portaaddr_unconnected_wire_1854,portaaddr_unconnected_wire_1855,portaaddr_unconnected_wire_1856,portaaddr_unconnected_wire_1857,portaaddr_unconnected_wire_1858,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1859,portbaddr_unconnected_wire_1860,portbaddr_unconnected_wire_1861,portbaddr_unconnected_wire_1862,portbaddr_unconnected_wire_1863, \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[9] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9 .logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9 .first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama9 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1864,portadatain_unconnected_wire_1865,portadatain_unconnected_wire_1866,portadatain_unconnected_wire_1867,portadatain_unconnected_wire_1868,portadatain_unconnected_wire_1869,portadatain_unconnected_wire_1870, portadatain_unconnected_wire_1871,portadatain_unconnected_wire_1872,portadatain_unconnected_wire_1873,portadatain_unconnected_wire_1874,portadatain_unconnected_wire_1875,portadatain_unconnected_wire_1876,portadatain_unconnected_wire_1877, portadatain_unconnected_wire_1878,portadatain_unconnected_wire_1879,portadatain_unconnected_wire_1880,portadatain_unconnected_wire_1881,portadatain_unconnected_wire_1882,\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][10] }), .portaaddr({portaaddr_unconnected_wire_1883,portaaddr_unconnected_wire_1884,portaaddr_unconnected_wire_1885,portaaddr_unconnected_wire_1886,portaaddr_unconnected_wire_1887,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1888,portbaddr_unconnected_wire_1889,portbaddr_unconnected_wire_1890,portbaddr_unconnected_wire_1891,portbaddr_unconnected_wire_1892, \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[10] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10 .logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10 .first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama10 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][11]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|__ALT_INV__delay_signals[0][11] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][11]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][11]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][11]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][11]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][11]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1893,portadatain_unconnected_wire_1894,portadatain_unconnected_wire_1895,portadatain_unconnected_wire_1896,portadatain_unconnected_wire_1897,portadatain_unconnected_wire_1898,portadatain_unconnected_wire_1899, portadatain_unconnected_wire_1900,portadatain_unconnected_wire_1901,portadatain_unconnected_wire_1902,portadatain_unconnected_wire_1903,portadatain_unconnected_wire_1904,portadatain_unconnected_wire_1905,portadatain_unconnected_wire_1906, portadatain_unconnected_wire_1907,portadatain_unconnected_wire_1908,portadatain_unconnected_wire_1909,portadatain_unconnected_wire_1910,portadatain_unconnected_wire_1911,\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][11] }), .portaaddr({portaaddr_unconnected_wire_1912,portaaddr_unconnected_wire_1913,portaaddr_unconnected_wire_1914,portaaddr_unconnected_wire_1915,portaaddr_unconnected_wire_1916,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1917,portbaddr_unconnected_wire_1918,portbaddr_unconnected_wire_1919,portbaddr_unconnected_wire_1920,portbaddr_unconnected_wire_1921, \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[11] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11 .logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11 .first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama11 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1922,portadatain_unconnected_wire_1923,portadatain_unconnected_wire_1924,portadatain_unconnected_wire_1925,portadatain_unconnected_wire_1926,portadatain_unconnected_wire_1927,portadatain_unconnected_wire_1928, portadatain_unconnected_wire_1929,portadatain_unconnected_wire_1930,portadatain_unconnected_wire_1931,portadatain_unconnected_wire_1932,portadatain_unconnected_wire_1933,portadatain_unconnected_wire_1934,portadatain_unconnected_wire_1935, portadatain_unconnected_wire_1936,portadatain_unconnected_wire_1937,portadatain_unconnected_wire_1938,portadatain_unconnected_wire_1939,portadatain_unconnected_wire_1940,\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][12] }), .portaaddr({portaaddr_unconnected_wire_1941,portaaddr_unconnected_wire_1942,portaaddr_unconnected_wire_1943,portaaddr_unconnected_wire_1944,portaaddr_unconnected_wire_1945,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1946,portbaddr_unconnected_wire_1947,portbaddr_unconnected_wire_1948,portbaddr_unconnected_wire_1949,portbaddr_unconnected_wire_1950, \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[12] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12 .logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12 .first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama12 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|delay_signals[0][13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1951,portadatain_unconnected_wire_1952,portadatain_unconnected_wire_1953,portadatain_unconnected_wire_1954,portadatain_unconnected_wire_1955,portadatain_unconnected_wire_1956,portadatain_unconnected_wire_1957, portadatain_unconnected_wire_1958,portadatain_unconnected_wire_1959,portadatain_unconnected_wire_1960,portadatain_unconnected_wire_1961,portadatain_unconnected_wire_1962,portadatain_unconnected_wire_1963,portadatain_unconnected_wire_1964, portadatain_unconnected_wire_1965,portadatain_unconnected_wire_1966,portadatain_unconnected_wire_1967,portadatain_unconnected_wire_1968,portadatain_unconnected_wire_1969,\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][13] }), .portaaddr({portaaddr_unconnected_wire_1970,portaaddr_unconnected_wire_1971,portaaddr_unconnected_wire_1972,portaaddr_unconnected_wire_1973,portaaddr_unconnected_wire_1974,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_1975,portbaddr_unconnected_wire_1976,portbaddr_unconnected_wire_1977,portbaddr_unconnected_wire_1978,portbaddr_unconnected_wire_1979, \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[13] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13 .logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13 .first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama13 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][14]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist109_outputreg|__ALT_INV__delay_signals[0][14] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][14]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][14]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][14]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][14]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][14]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist110_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_1980,portadatain_unconnected_wire_1981,portadatain_unconnected_wire_1982,portadatain_unconnected_wire_1983,portadatain_unconnected_wire_1984,portadatain_unconnected_wire_1985,portadatain_unconnected_wire_1986, portadatain_unconnected_wire_1987,portadatain_unconnected_wire_1988,portadatain_unconnected_wire_1989,portadatain_unconnected_wire_1990,portadatain_unconnected_wire_1991,portadatain_unconnected_wire_1992,portadatain_unconnected_wire_1993, portadatain_unconnected_wire_1994,portadatain_unconnected_wire_1995,portadatain_unconnected_wire_1996,portadatain_unconnected_wire_1997,portadatain_unconnected_wire_1998,\fp_pow_0002:fp_pow_inst|dspba_delay:redist110_inputreg|delay_signals[0][14] }), .portaaddr({portaaddr_unconnected_wire_1999,portaaddr_unconnected_wire_2000,portaaddr_unconnected_wire_2001,portaaddr_unconnected_wire_2002,portaaddr_unconnected_wire_2003,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2004,portbaddr_unconnected_wire_2005,portbaddr_unconnected_wire_2006,portbaddr_unconnected_wire_2007,portbaddr_unconnected_wire_2008, \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[14] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14 .logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14 .first_bit_number = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|lutrama14 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_a0[0][17]~2_I ( .combout(\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_a0[0][17]~2 )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_a0[0][17]~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_a0[0][17]~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_a0[0][17]~2_I .lut_mask = "0000000000000000"; cyclonev_mac \fp_pow_0002:fp_pow_inst|Mult2~8_I ( .sub(gnd), .negate(gnd), .ax({ax_unconnected_wire_2009,ax_unconnected_wire_2010,ax_unconnected_wire_2011,ax_unconnected_wire_2012,ax_unconnected_wire_2013,ax_unconnected_wire_2014,ax_unconnected_wire_2015,ax_unconnected_wire_2016,ax_unconnected_wire_2017, \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][13] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][12] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][11] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][10] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][9] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][8] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist32|delay_signals[0][0] ,\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][3]~3 , \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][2]~2 ,\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][1]~1 ,\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_c0[0][0]~0 }), .ay({ay_unconnected_wire_2018,ay_unconnected_wire_2019,ay_unconnected_wire_2020,ay_unconnected_wire_2021,ay_unconnected_wire_2022,ay_unconnected_wire_2023,ay_unconnected_wire_2024,ay_unconnected_wire_2025, \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_a0[0][17]~2 ,\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_a0[0][17]~2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[14] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[13] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[12] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[11] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[10] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[9] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[8] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[7] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[6] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[5] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[0] ,\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_a0[0][1]~1 , \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_a0[0][0]~0 }), .clk({clk_unconnected_wire_2026,clk_unconnected_wire_2027,\clk~CLKENA0 }), .aclr({\areset~CLKENA0 ,\areset~CLKENA0 }), .ena({ena_unconnected_wire_2028,ena_unconnected_wire_2029,\vcc }), .resulta({\fp_pow_0002:fp_pow_inst|Mult2~53 ,\fp_pow_0002:fp_pow_inst|Mult2~52 ,\fp_pow_0002:fp_pow_inst|Mult2~51 ,\fp_pow_0002:fp_pow_inst|Mult2~50 ,\fp_pow_0002:fp_pow_inst|Mult2~49 ,\fp_pow_0002:fp_pow_inst|Mult2~48 ,\fp_pow_0002:fp_pow_inst|Mult2~47 , \fp_pow_0002:fp_pow_inst|Mult2~46 ,\fp_pow_0002:fp_pow_inst|Mult2~45 ,\fp_pow_0002:fp_pow_inst|Mult2~44 ,\fp_pow_0002:fp_pow_inst|Mult2~43 ,\fp_pow_0002:fp_pow_inst|Mult2~42 ,\fp_pow_0002:fp_pow_inst|Mult2~41 ,\fp_pow_0002:fp_pow_inst|Mult2~40 , \fp_pow_0002:fp_pow_inst|Mult2~39 ,\fp_pow_0002:fp_pow_inst|Mult2~38 ,\fp_pow_0002:fp_pow_inst|Mult2~37 ,\fp_pow_0002:fp_pow_inst|Mult2~36 ,\fp_pow_0002:fp_pow_inst|Mult2~35 ,\fp_pow_0002:fp_pow_inst|Mult2~34 ,\fp_pow_0002:fp_pow_inst|Mult2~33 , \fp_pow_0002:fp_pow_inst|Mult2~32 ,\fp_pow_0002:fp_pow_inst|Mult2~31 ,\fp_pow_0002:fp_pow_inst|Mult2~30 ,\fp_pow_0002:fp_pow_inst|Mult2~29 ,\fp_pow_0002:fp_pow_inst|Mult2~28 ,\fp_pow_0002:fp_pow_inst|Mult2~27 ,\fp_pow_0002:fp_pow_inst|Mult2~26 , \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][35] ,\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][34] ,\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][33] , \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][32] ,\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][31] ,\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][30] , \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][29] ,\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][28] ,\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][27] , \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][26] ,\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][25] ,\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][24] , \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][23] ,\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][22] ,\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][21] , \fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][20] ,\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][19] ,\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][18] , \fp_pow_0002:fp_pow_inst|Mult2~25 ,\fp_pow_0002:fp_pow_inst|Mult2~24 ,\fp_pow_0002:fp_pow_inst|Mult2~23 ,\fp_pow_0002:fp_pow_inst|Mult2~22 ,\fp_pow_0002:fp_pow_inst|Mult2~21 ,\fp_pow_0002:fp_pow_inst|Mult2~20 ,\fp_pow_0002:fp_pow_inst|Mult2~19 , \fp_pow_0002:fp_pow_inst|Mult2~18 ,\fp_pow_0002:fp_pow_inst|Mult2~17 ,\fp_pow_0002:fp_pow_inst|Mult2~16 ,\fp_pow_0002:fp_pow_inst|Mult2~15 ,\fp_pow_0002:fp_pow_inst|Mult2~14 ,\fp_pow_0002:fp_pow_inst|Mult2~13 ,\fp_pow_0002:fp_pow_inst|Mult2~12 , \fp_pow_0002:fp_pow_inst|Mult2~11 ,\fp_pow_0002:fp_pow_inst|Mult2~10 ,\fp_pow_0002:fp_pow_inst|Mult2~9 ,\fp_pow_0002:fp_pow_inst|Mult2~8 })); defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .signed_max = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .signed_may = "true"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .signed_mbx = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .signed_mby = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .preadder_subtract_a = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .preadder_subtract_b = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .ay_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .by_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .delay_scan_out_ay = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .delay_scan_out_by = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .use_chainadder = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .enable_double_accum = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .operation_mode = "M18X18_FULL"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .operand_source_max = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .operand_source_may = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .operand_source_mbx = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .operand_source_mby = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .ax_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .ay_scan_in_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .az_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .bx_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .by_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .bz_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .coef_sel_a_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .coef_sel_b_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .sub_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .negate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .accumulate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .load_const_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .output_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .coef_a_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .coef_a_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .coef_a_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .coef_a_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .coef_a_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .coef_a_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .coef_a_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .coef_a_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .coef_b_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .coef_b_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .coef_b_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .coef_b_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .coef_b_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .coef_b_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .coef_b_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .coef_b_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .ax_width = 18; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .ay_scan_in_width = 19; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .mode_sub_location = 0; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .load_const_value = 0; defparam \fp_pow_0002:fp_pow_inst|Mult2~8_I .result_a_width = 64; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][17]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][35] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][17]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][17]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][17]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][17]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][17]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][13]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][29] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][13]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][13]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][13]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][13]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][13]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][13]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[13] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][13]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][13]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][13]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][13]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][13]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~1_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][13] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][13] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~122 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~1 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~2 )); defparam \fp_pow_0002:fp_pow_inst|Add2~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~1_I .lut_mask = "0000CCCC00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][30] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[14] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~5_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][14] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][14] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~2 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~6 )); defparam \fp_pow_0002:fp_pow_inst|Add2~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~5_I .lut_mask = "0000CCCC000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][15]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][31] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][15]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][15]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][15]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][15]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][15]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][15]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[15] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][15]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][15]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][15]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][15]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][15]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~9_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][15] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][15] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~10 )); defparam \fp_pow_0002:fp_pow_inst|Add2~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~9_I .lut_mask = "0000AAAA00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][16]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[16] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][16]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][16]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][16]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][16]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][16]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][16]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][32] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][16]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][16]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][16]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][16]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][16]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~13_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][16] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][16] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~14 )); defparam \fp_pow_0002:fp_pow_inst|Add2~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~13_I .lut_mask = "0000F0F000003333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][17]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[17] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][17]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][17]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][17]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][17]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][17]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][33] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~17_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][17] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][17] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~18 )); defparam \fp_pow_0002:fp_pow_inst|Add2~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~17_I .lut_mask = "0000F0F000005555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][18]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|__ALT_INV__q_b[18] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][18]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][18]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][18]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][18]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][18]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][34] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~21_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][18] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][18] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~22 )); defparam \fp_pow_0002:fp_pow_inst|Add2~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~21_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][35] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid257_natLogTabGen_lutmem_dmem|altera_syncram_k5m3:auto_generated|altsyncram_pve4:altsyncram1|q_b[19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~25_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][19] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][19] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~26 )); defparam \fp_pow_0002:fp_pow_inst|Add2~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~25_I .lut_mask = "0000AAAA00003333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][36] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][20]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][20]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][20]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][20]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][20]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][20]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~29_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][20] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][20] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~30 )); defparam \fp_pow_0002:fp_pow_inst|Add2~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~29_I .lut_mask = "0000FF0000003333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][21]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[1] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][21]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][21]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][21]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][21]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][21]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][21]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][37] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][21]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][21]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][21]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][21]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][21]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~33_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][21] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][21] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~34 )); defparam \fp_pow_0002:fp_pow_inst|Add2~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~33_I .lut_mask = "0000AAAA000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodXY_uid450_pT2_uid272_natLogPolyEval_cma_s[0][38] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist66|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][22]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[2] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][22]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][22]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][22]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][22]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][22]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~37_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][22] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][22] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~38 )); defparam \fp_pow_0002:fp_pow_inst|Add2~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~37_I .lut_mask = "0000AAAA00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][23]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][23]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][23]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][23]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][23]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][23]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~41_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][22] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][23] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~42 )); defparam \fp_pow_0002:fp_pow_inst|Add2~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~41_I .lut_mask = "0000AAAA00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][24]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[4] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][24]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][24]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][24]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][24]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][24]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~45_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][22] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~46 )); defparam \fp_pow_0002:fp_pow_inst|Add2~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~45_I .lut_mask = "0000AAAA00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][25]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][25]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][25]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][25]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][25]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][25]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~49_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][22] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][25] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~50 )); defparam \fp_pow_0002:fp_pow_inst|Add2~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~49_I .lut_mask = "0000AAAA00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][26]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][26]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][26]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][26]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][26]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][26]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~53_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][22] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][26] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~54 )); defparam \fp_pow_0002:fp_pow_inst|Add2~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~53_I .lut_mask = "0000FF0000005555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|q_b[7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~57_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][22] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][27] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~57 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~58 )); defparam \fp_pow_0002:fp_pow_inst|Add2~57_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~57_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~57_I .lut_mask = "0000AAAA00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~57 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][28]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[8] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][28]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][28]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][28]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][28]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][28]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~61_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][22] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][28] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~58 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~62 )); defparam \fp_pow_0002:fp_pow_inst|Add2~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~61_I .lut_mask = "0000AAAA000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~61 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][29]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid258_natLogTabGen_lutmem_dmem|altera_syncram_j5m3:auto_generated|altsyncram_ove4:altsyncram1|__ALT_INV__q_b[9] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][29]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][29]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][29]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][29]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][29]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist69|delay_signals[0][29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~65_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][22] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][29] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~65 ), .cout(\fp_pow_0002:fp_pow_inst|Add2~66 )); defparam \fp_pow_0002:fp_pow_inst|Add2~65_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~65_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~65_I .lut_mask = "0000AAAA00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~65 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add2~69_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist69|__ALT_INV__delay_signals[0][29] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist66|__ALT_INV__delay_signals[0][22] ), .cin(\fp_pow_0002:fp_pow_inst|Add2~66 ), .sumout(\fp_pow_0002:fp_pow_inst|Add2~69 )); defparam \fp_pow_0002:fp_pow_inst|Add2~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add2~69_I .lut_mask = "0000F0F000003333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add2~69 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_a0[0][0]~0_I ( .combout(\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_a0[0][0]~0 )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_a0[0][0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_a0[0][0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_a0[0][0]~0_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_a0[0][1]~1_I ( .combout(\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_a0[0][1]~1 )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_a0[0][1]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_a0[0][1]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_a0[0][1]~1_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_a0[0][17]~2_I ( .combout(\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_a0[0][17]~2 )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_a0[0][17]~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_a0[0][17]~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_a0[0][17]~2_I .lut_mask = "0000000000000000"; cyclonev_mac \fp_pow_0002:fp_pow_inst|Mult3~mac ( .sub(gnd), .negate(gnd), .ax({ax_unconnected_wire_2030,ax_unconnected_wire_2031,ax_unconnected_wire_2032,ax_unconnected_wire_2033,ax_unconnected_wire_2034,ax_unconnected_wire_2035,ax_unconnected_wire_2036,ax_unconnected_wire_2037,ax_unconnected_wire_2038, \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][17] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][16] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][15] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][14] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][13] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][12] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][11] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][10] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][9] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist33|delay_signals[0][0] }), .ay({ay_unconnected_wire_2039,ay_unconnected_wire_2040,ay_unconnected_wire_2041,ay_unconnected_wire_2042,ay_unconnected_wire_2043,ay_unconnected_wire_2044,ay_unconnected_wire_2045,ay_unconnected_wire_2046, \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_a0[0][17]~2 ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_a0[0][17]~2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[14] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[13] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[12] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[11] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[10] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[9] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[8] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[7] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[6] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[5] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist110_replace_mem_dmem|altera_syncram_odg3:auto_generated|altsyncram_jmb4:altsyncram1|dataout_reg[0] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_a0[0][1]~1 , \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_a0[0][0]~0 }), .clk({clk_unconnected_wire_2047,clk_unconnected_wire_2048,\clk~CLKENA0 }), .aclr({\areset~CLKENA0 ,\areset~CLKENA0 }), .ena({ena_unconnected_wire_2049,ena_unconnected_wire_2050,\vcc }), .resulta({\fp_pow_0002:fp_pow_inst|Mult3~35 ,\fp_pow_0002:fp_pow_inst|Mult3~34 ,\fp_pow_0002:fp_pow_inst|Mult3~33 ,\fp_pow_0002:fp_pow_inst|Mult3~32 ,\fp_pow_0002:fp_pow_inst|Mult3~31 ,\fp_pow_0002:fp_pow_inst|Mult3~30 ,\fp_pow_0002:fp_pow_inst|Mult3~29 , \fp_pow_0002:fp_pow_inst|Mult3~28 ,\fp_pow_0002:fp_pow_inst|Mult3~27 ,\fp_pow_0002:fp_pow_inst|Mult3~26 ,\fp_pow_0002:fp_pow_inst|Mult3~25 ,\fp_pow_0002:fp_pow_inst|Mult3~24 ,\fp_pow_0002:fp_pow_inst|Mult3~23 ,\fp_pow_0002:fp_pow_inst|Mult3~22 , \fp_pow_0002:fp_pow_inst|Mult3~21 ,\fp_pow_0002:fp_pow_inst|Mult3~20 ,\fp_pow_0002:fp_pow_inst|Mult3~19 ,\fp_pow_0002:fp_pow_inst|Mult3~18 ,\fp_pow_0002:fp_pow_inst|Mult3~17 ,\fp_pow_0002:fp_pow_inst|Mult3~16 ,\fp_pow_0002:fp_pow_inst|Mult3~15 , \fp_pow_0002:fp_pow_inst|Mult3~14 ,\fp_pow_0002:fp_pow_inst|Mult3~13 ,\fp_pow_0002:fp_pow_inst|Mult3~12 ,\fp_pow_0002:fp_pow_inst|Mult3~11 ,\fp_pow_0002:fp_pow_inst|Mult3~10 ,\fp_pow_0002:fp_pow_inst|Mult3~9 ,\fp_pow_0002:fp_pow_inst|Mult3~8 , \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_p[0][35] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][34] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][33] , \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][32] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][31] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][30] , \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][29] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][28] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][27] , \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][26] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][25] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][24] , \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][23] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][22] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][21] , \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][20] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][19] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][18] , \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][17] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][16] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][15] , \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][14] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][13] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][12] , \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][11] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][10] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][9] , \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][8] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][7] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][6] , \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][5] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][4] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][3] , \fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][2] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][1] ,\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][0] })); defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .signed_max = "true"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .signed_may = "true"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .signed_mbx = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .signed_mby = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .preadder_subtract_a = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .preadder_subtract_b = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .ay_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .by_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .delay_scan_out_ay = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .delay_scan_out_by = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .use_chainadder = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .enable_double_accum = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .operation_mode = "M18X18_FULL"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .operand_source_max = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .operand_source_may = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .operand_source_mbx = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .operand_source_mby = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .ax_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .ay_scan_in_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .az_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .bx_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .by_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .bz_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .coef_sel_a_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .coef_sel_b_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .sub_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .negate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .accumulate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .load_const_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .output_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .coef_a_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .coef_a_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .coef_a_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .coef_a_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .coef_a_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .coef_a_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .coef_a_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .coef_a_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .coef_b_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .coef_b_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .coef_b_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .coef_b_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .coef_b_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .coef_b_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .coef_b_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .coef_b_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .ax_width = 18; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .ay_scan_in_width = 19; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .mode_sub_location = 0; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .load_const_value = 0; defparam \fp_pow_0002:fp_pow_inst|Mult3~mac .result_a_width = 64; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][27] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][26]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][26] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][26]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][26]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][26]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][26]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][26]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][26]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][25] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][24]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][24] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][24]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][24]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][24]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][24]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][24]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][24]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][23] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][22]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][22] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][22]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][22]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][22]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][22]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][22]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][20]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][20] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][20]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][20]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][20]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][20]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][20]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][16]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][16] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][16]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][16]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][16]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][16]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][16]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][16]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][34] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][16]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][16]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][16]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][16]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][16]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][15]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][33] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][15]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][15]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][15]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][15]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][15]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][14]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][32] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][14]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][14]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][14]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][14]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][14]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][14]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][14] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][14]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][14]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][14]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][14]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][14]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][31] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][12]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][30] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][12]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][12]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][12]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][12]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][12]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][12]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][12] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][12]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][12]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][12]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][12]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][12]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][29] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][28] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][10]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][10] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][10]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][10]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][10]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][10]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][10]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][9]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][9] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][9]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][9]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][9]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][9]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][9]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][27] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][8]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][8] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][8]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][8]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][8]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][8]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][8]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][26] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][25] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][6]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][24] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][6]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][6]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][6]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][5]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][23] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][5]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][4]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][4]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][4]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][4]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][22] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][4]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][4]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][2]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][2]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][20] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid486_pT3_uid278_natLogPolyEval_cma_s[0][18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist30|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~138_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][0] ), .cin(gnd), .cout(\fp_pow_0002:fp_pow_inst|Add3~138 )); defparam \fp_pow_0002:fp_pow_inst|Add3~138_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~138_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~138_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~134_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][1] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~138 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~134 )); defparam \fp_pow_0002:fp_pow_inst|Add3~134_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~134_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~134_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~130_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][2] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~134 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~130 )); defparam \fp_pow_0002:fp_pow_inst|Add3~130_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~130_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~130_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~126_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][3] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~130 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~126 )); defparam \fp_pow_0002:fp_pow_inst|Add3~126_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~126_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~126_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~121_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][4] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~126 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~121 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~122 )); defparam \fp_pow_0002:fp_pow_inst|Add3~121_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~121_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~121_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~117_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~122 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~117 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~118 )); defparam \fp_pow_0002:fp_pow_inst|Add3~117_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~117_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~117_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~113_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][6] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][6] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~118 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~113 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~114 )); defparam \fp_pow_0002:fp_pow_inst|Add3~113_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~113_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~113_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~109_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][7] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~114 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~109 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~110 )); defparam \fp_pow_0002:fp_pow_inst|Add3~109_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~109_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~109_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~105_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][8] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][8] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~110 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~105 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~106 )); defparam \fp_pow_0002:fp_pow_inst|Add3~105_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~105_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~105_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][9] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][9] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~106 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~1 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~2 )); defparam \fp_pow_0002:fp_pow_inst|Add3~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~1_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~5_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][10] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][10] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~2 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~6 )); defparam \fp_pow_0002:fp_pow_inst|Add3~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~5_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~9_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][11] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][11] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~10 )); defparam \fp_pow_0002:fp_pow_inst|Add3~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~9_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~13_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][12] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][12] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~14 )); defparam \fp_pow_0002:fp_pow_inst|Add3~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~13_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~17_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][13] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][13] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~18 )); defparam \fp_pow_0002:fp_pow_inst|Add3~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~17_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~21_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][14] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][14] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~22 )); defparam \fp_pow_0002:fp_pow_inst|Add3~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~21_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~25_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][15] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][15] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~26 )); defparam \fp_pow_0002:fp_pow_inst|Add3~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~25_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~29_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][16] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][16] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~30 )); defparam \fp_pow_0002:fp_pow_inst|Add3~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~29_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~33_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][17] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][17] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~34 )); defparam \fp_pow_0002:fp_pow_inst|Add3~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~33_I .lut_mask = "0000FF0000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~37_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][17] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][18] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~38 )); defparam \fp_pow_0002:fp_pow_inst|Add3~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~37_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~41_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][17] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][19] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~42 )); defparam \fp_pow_0002:fp_pow_inst|Add3~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~41_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~45_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][17] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][20] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~46 )); defparam \fp_pow_0002:fp_pow_inst|Add3~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~45_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~49_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][17] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][21] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~50 )); defparam \fp_pow_0002:fp_pow_inst|Add3~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~49_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~53_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][17] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][22] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~54 )); defparam \fp_pow_0002:fp_pow_inst|Add3~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~53_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~57_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][23] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][17] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~57 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~58 )); defparam \fp_pow_0002:fp_pow_inst|Add3~57_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~57_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~57_I .lut_mask = "0000CCCC00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~61_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][17] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~58 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~62 )); defparam \fp_pow_0002:fp_pow_inst|Add3~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~61_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~65_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][17] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][25] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~65 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~66 )); defparam \fp_pow_0002:fp_pow_inst|Add3~65_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~65_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~65_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~69_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][26] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][17] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~66 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~69 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~70 )); defparam \fp_pow_0002:fp_pow_inst|Add3~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~69_I .lut_mask = "0000CCCC00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~73_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][17] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][27] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~70 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~73 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~74 )); defparam \fp_pow_0002:fp_pow_inst|Add3~73_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~73_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~73_I .lut_mask = "0000CCCC000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~73 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~69 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][24]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][21]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[1] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][21]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][21]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][21]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][21]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][21]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~65 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][20]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][20]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][20]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][20]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][20]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][20]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~61 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][19]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|__ALT_INV__q_b[19] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][19]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][19]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][19]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][19]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][19]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~57 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][18]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|__ALT_INV__q_b[18] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][18]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][18]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][18]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][18]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][18]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][16]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|__ALT_INV__q_b[16] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][16]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][16]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][16]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][16]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][16]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][14]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|__ALT_INV__q_b[14] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][14]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][14]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][14]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][14]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][14]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][13]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|__ALT_INV__q_b[13] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][13]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][13]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][13]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][13]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][13]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][8]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|__ALT_INV__q_b[8] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][8]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][8]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][8]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][8]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][8]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][6]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|__ALT_INV__q_b[6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][6]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|Add3~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~105 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .init_file = "fp_pow_0002_memoryC0_uid254_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_a_first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_b_first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a0 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[1] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .init_file = "fp_pow_0002_memoryC0_uid254_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_a_first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_b_first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a1 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[2] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .init_file = "fp_pow_0002_memoryC0_uid254_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_a_first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_b_first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a2 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[3] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .init_file = "fp_pow_0002_memoryC0_uid254_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_a_first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_b_first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a3 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[4] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .init_file = "fp_pow_0002_memoryC0_uid254_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_a_first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_b_first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|ram_block2a4 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[5] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .init_file = "fp_pow_0002_memoryC0_uid255_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_a_first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_b_first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a5 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[6] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .init_file = "fp_pow_0002_memoryC0_uid255_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_a_first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_b_first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a6 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[7] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .init_file = "fp_pow_0002_memoryC0_uid255_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_a_first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_b_first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a7 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[8] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .init_file = "fp_pow_0002_memoryC0_uid255_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_a_first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_b_first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a8 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[9] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .init_file = "fp_pow_0002_memoryC0_uid255_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_a_first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_b_first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a9 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[10] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .init_file = "fp_pow_0002_memoryC0_uid255_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_a_first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_b_first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a10 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[11] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .init_file = "fp_pow_0002_memoryC0_uid255_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_a_first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_b_first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a11 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[12] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .init_file = "fp_pow_0002_memoryC0_uid255_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_a_first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_b_first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a12 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[13] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .init_file = "fp_pow_0002_memoryC0_uid255_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_a_first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_b_first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a13 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[14] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .init_file = "fp_pow_0002_memoryC0_uid255_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_a_first_bit_number = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_b_first_bit_number = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a14 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[15] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .init_file = "fp_pow_0002_memoryC0_uid255_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_a_first_bit_number = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_b_first_bit_number = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a15 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[16] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .init_file = "fp_pow_0002_memoryC0_uid255_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_a_first_bit_number = 16; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_b_first_bit_number = 16; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a16 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[17] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .init_file = "fp_pow_0002_memoryC0_uid255_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_a_first_bit_number = 17; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_b_first_bit_number = 17; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a17 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[18] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .init_file = "fp_pow_0002_memoryC0_uid255_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_a_first_bit_number = 18; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_b_first_bit_number = 18; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a18 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|Equal0~1 ,\a[22]~input0 ,\a[21]~input0 ,\a[20]~input0 ,\a[19]~input0 ,\a[18]~input0 ,\a[17]~input0 ,\a[16]~input0 ,\a[15]~input0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[19] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .init_file = "fp_pow_0002_memoryC0_uid255_natLogTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_a_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_a_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_a_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_a_first_bit_number = 19; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_a_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_b_logical_ram_depth = 512; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_b_logical_ram_width = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_b_last_address = 511; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_b_first_bit_number = 19; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_b_address_width = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|ram_block2a19 .port_b_read_during_write_mode = "new_data_no_nbe_read"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~109 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~113 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add3~117 ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|Add3~121 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid254_natLogTabGen_lutmem_dmem|altera_syncram_g5m3:auto_generated|altsyncram_lve4:altsyncram1|q_b[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~158_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][0] ), .cin(gnd), .cout(\fp_pow_0002:fp_pow_inst|Add4~158 )); defparam \fp_pow_0002:fp_pow_inst|Add4~158_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~158_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~158_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~154_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][1] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~158 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~154 )); defparam \fp_pow_0002:fp_pow_inst|Add4~154_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~154_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~154_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~150_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][2] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~154 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~150 )); defparam \fp_pow_0002:fp_pow_inst|Add4~150_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~150_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~150_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~146_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][3] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~150 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~146 )); defparam \fp_pow_0002:fp_pow_inst|Add4~146_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~146_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~146_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~142_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][6] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][4] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~146 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~142 )); defparam \fp_pow_0002:fp_pow_inst|Add4~142_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~142_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~142_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][7] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~142 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~1 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~2 )); defparam \fp_pow_0002:fp_pow_inst|Add4~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~1_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~5_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][6] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][8] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~2 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~6 )); defparam \fp_pow_0002:fp_pow_inst|Add4~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~5_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~9_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][9] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~10 )); defparam \fp_pow_0002:fp_pow_inst|Add4~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~9_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~13_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][8] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][10] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~14 )); defparam \fp_pow_0002:fp_pow_inst|Add4~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~13_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~17_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][9] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][11] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~18 )); defparam \fp_pow_0002:fp_pow_inst|Add4~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~17_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~21_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][12] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][10] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~22 )); defparam \fp_pow_0002:fp_pow_inst|Add4~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~21_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~25_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][13] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][11] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~26 )); defparam \fp_pow_0002:fp_pow_inst|Add4~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~25_I .lut_mask = "0000FF0000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~29_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][12] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][14] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~30 )); defparam \fp_pow_0002:fp_pow_inst|Add4~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~29_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~33_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][15] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][13] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~34 )); defparam \fp_pow_0002:fp_pow_inst|Add4~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~33_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~37_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][16] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][14] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~38 )); defparam \fp_pow_0002:fp_pow_inst|Add4~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~37_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~41_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][15] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][17] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~42 )); defparam \fp_pow_0002:fp_pow_inst|Add4~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~41_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~45_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][16] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][18] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~46 )); defparam \fp_pow_0002:fp_pow_inst|Add4~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~45_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~49_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][17] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][19] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~50 )); defparam \fp_pow_0002:fp_pow_inst|Add4~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~49_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~53_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][18] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][20] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~54 )); defparam \fp_pow_0002:fp_pow_inst|Add4~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~53_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~57_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][19] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][21] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~57 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~58 )); defparam \fp_pow_0002:fp_pow_inst|Add4~57_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~57_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~57_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~61_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][20] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][22] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~58 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~62 )); defparam \fp_pow_0002:fp_pow_inst|Add4~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~61_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~65_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][21] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][23] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~65 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~66 )); defparam \fp_pow_0002:fp_pow_inst|Add4~65_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~65_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~65_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~69_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][24] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][22] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~66 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~69 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~70 )); defparam \fp_pow_0002:fp_pow_inst|Add4~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~69_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~73_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][23] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][25] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~70 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~73 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~74 )); defparam \fp_pow_0002:fp_pow_inst|Add4~73_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~73_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~73_I .lut_mask = "0000F0F000005555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~73 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][24]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[4] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][24]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][24]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][24]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][24]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][24]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][28]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][28] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][28]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][28]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][28]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][28]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][28]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~77_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][17] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][28] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~74 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~78 )); defparam \fp_pow_0002:fp_pow_inst|Add3~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~77_I .lut_mask = "0000CCCC000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~77 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~77_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][24] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][26] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~74 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~78 )); defparam \fp_pow_0002:fp_pow_inst|Add4~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~77_I .lut_mask = "0000FF0000000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~77 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][29]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][29] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][29]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][29]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][29]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][29]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][29]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~81_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][17] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][29] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~81 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~82 )); defparam \fp_pow_0002:fp_pow_inst|Add3~81_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~81_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~81_I .lut_mask = "0000CCCC00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~81 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][27]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~81_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][27] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][25] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~81 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~82 )); defparam \fp_pow_0002:fp_pow_inst|Add4~81_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~81_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~81_I .lut_mask = "0000CCCC00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~81 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][30]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][30] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][30]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][30]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][30]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][30]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][30]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~85_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][17] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][30] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~82 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~85 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~86 )); defparam \fp_pow_0002:fp_pow_inst|Add3~85_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~85_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~85_I .lut_mask = "0000CCCC00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~85 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~85_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][26] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][28] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~82 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~85 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~86 )); defparam \fp_pow_0002:fp_pow_inst|Add4~85_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~85_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~85_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~85 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][27]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[7] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][27]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][27]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][27]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][27]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][27]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][31]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][31] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][31]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][31]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][31]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][31]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][31]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~89_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][31] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][17] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~86 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~89 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~90 )); defparam \fp_pow_0002:fp_pow_inst|Add3~89_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~89_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~89_I .lut_mask = "0000CCCC00005555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~89 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~89_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][27] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][29] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~86 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~89 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~90 )); defparam \fp_pow_0002:fp_pow_inst|Add4~89_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~89_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~89_I .lut_mask = "0000AAAA000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~89 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][28]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[8] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][28]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][28]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][28]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][28]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][28]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][28]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][32] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~93_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][17] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][32] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~90 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~93 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~94 )); defparam \fp_pow_0002:fp_pow_inst|Add3~93_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~93_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~93_I .lut_mask = "0000CCCC00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~93 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~93_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][28] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][30] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~90 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~93 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~94 )); defparam \fp_pow_0002:fp_pow_inst|Add4~93_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~93_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~93_I .lut_mask = "0000F0F000003333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~93 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][29]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[9] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][29]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][29]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][29]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][29]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][29]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][33]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][33] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][33]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][33]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][33]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][33]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][33]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~97_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][33] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][17] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~94 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~97 ), .cout(\fp_pow_0002:fp_pow_inst|Add3~98 )); defparam \fp_pow_0002:fp_pow_inst|Add3~97_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~97_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~97_I .lut_mask = "0000CCCC00005555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~97 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~97_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][29] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][31] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~94 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~97 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~98 )); defparam \fp_pow_0002:fp_pow_inst|Add4~97_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~97_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~97_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~97 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][30]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[10] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][30]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][30]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][30]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][30]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][30]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][34]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid485_pT3_uid278_natLogPolyEval_cma_s[0][34] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][34]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][34]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][34]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][34]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][34]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist2|delay_signals[0][34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add3~101_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist30|__ALT_INV__delay_signals[0][17] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist2|__ALT_INV__delay_signals[0][34] ), .cin(\fp_pow_0002:fp_pow_inst|Add3~98 ), .sumout(\fp_pow_0002:fp_pow_inst|Add3~101 )); defparam \fp_pow_0002:fp_pow_inst|Add3~101_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~101_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add3~101_I .lut_mask = "0000FF0000003333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add3~101 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist29|delay_signals[0][32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~101_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][30] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][32] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~98 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~101 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~102 )); defparam \fp_pow_0002:fp_pow_inst|Add4~101_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~101_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~101_I .lut_mask = "0000FF0000003333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~101 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~105_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][31] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][32] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~102 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~105 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~106 )); defparam \fp_pow_0002:fp_pow_inst|Add4~105_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~105_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~105_I .lut_mask = "0000F0F000005555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~105 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~109_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][32] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][32] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~106 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~109 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~110 )); defparam \fp_pow_0002:fp_pow_inst|Add4~109_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~109_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~109_I .lut_mask = "0000FF0000003333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~109 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][33]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[13] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][33]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][33]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][33]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][33]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][33]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~113_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][33] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][32] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~110 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~113 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~114 )); defparam \fp_pow_0002:fp_pow_inst|Add4~113_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~113_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~113_I .lut_mask = "0000FF0000000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~113 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][34]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[14] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][34]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][34]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][34]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][34]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][34]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~117_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][32] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][34] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~114 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~117 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~118 )); defparam \fp_pow_0002:fp_pow_inst|Add4~117_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~117_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~117_I .lut_mask = "0000CCCC00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~117 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][35]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~121_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][32] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][35] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~118 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~121 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~122 )); defparam \fp_pow_0002:fp_pow_inst|Add4~121_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~121_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~121_I .lut_mask = "0000CCCC00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~121 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][36]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][36] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][36]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~125_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][32] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][36] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~122 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~125 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~126 )); defparam \fp_pow_0002:fp_pow_inst|Add4~125_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~125_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~125_I .lut_mask = "0000CCCC00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~125 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][37]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[17] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][37]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][37]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][37]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][37]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][37]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][37] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][37]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~129_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][37] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][32] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~126 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~129 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~130 )); defparam \fp_pow_0002:fp_pow_inst|Add4~129_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~129_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~129_I .lut_mask = "0000CCCC00005555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~129 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][38]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|q_b[18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][38] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][38]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~133_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][38] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][32] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~130 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~133 ), .cout(\fp_pow_0002:fp_pow_inst|Add4~134 )); defparam \fp_pow_0002:fp_pow_inst|Add4~133_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~133_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~133_I .lut_mask = "0000FF0000003333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~133 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][39]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid255_natLogTabGen_lutmem_dmem|altera_syncram_h5m3:auto_generated|altsyncram_mve4:altsyncram1|__ALT_INV__q_b[19] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][39]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][39]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][39]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][39]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][39]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][39]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][39] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist70|delay_signals[0][39]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add4~137_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist70|__ALT_INV__delay_signals[0][39] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist29|__ALT_INV__delay_signals[0][32] ), .cin(\fp_pow_0002:fp_pow_inst|Add4~134 ), .sumout(\fp_pow_0002:fp_pow_inst|Add4~137 )); defparam \fp_pow_0002:fp_pow_inst|Add4~137_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~137_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add4~137_I .lut_mask = "0000F0F000005555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~137 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[3][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist113_outputreg|delay_signals[0][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[3][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[3][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[3][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[3][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][1]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][1]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][1]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][1]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][1]~DUPLICATE_I .created_from = "Q(delay_signals[0][1])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~1_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][0] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add7~1 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~2 )); defparam \fp_pow_0002:fp_pow_inst|Add7~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~1_I .lut_mask = "000000FF0000CCCC"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[1] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[1]~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[1] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[1]~0 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[1]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[1]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[1]~0_I .lut_mask = "0A0A0A0A5F5F5F5F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~5_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][2] ), .cin(\fp_pow_0002:fp_pow_inst|Add7~2 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~6 )); defparam \fp_pow_0002:fp_pow_inst|Add7~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~5_I .lut_mask = "0000FFFF0000F0F0"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[2] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[2]~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[2] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[2]~1 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[2]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[2]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[2]~1_I .lut_mask = "0A0A0A0A5F5F5F5F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~9_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][3] ), .cin(\fp_pow_0002:fp_pow_inst|Add7~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~10 )); defparam \fp_pow_0002:fp_pow_inst|Add7~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~9_I .lut_mask = "0000FFFF0000F0F0"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[3] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[3]~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[3] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[3]~2 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[3]~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[3]~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[3]~2_I .lut_mask = "0A5F0A5F0A5F0A5F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][4]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist137_replace_mem_dmem|altera_syncram_aeg3:auto_generated|altsyncram_5nb4:altsyncram1|dataout_reg[4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][4]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][4]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][4]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][4]~DUPLICATE_I .created_from = "Q(delay_signals[0][4])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~13_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][4]~DUPLICATE ), .cin(\fp_pow_0002:fp_pow_inst|Add7~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~14 )); defparam \fp_pow_0002:fp_pow_inst|Add7~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~13_I .lut_mask = "0000FFFF0000F0F0"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[4] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[4]~3_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[4] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[4]~3 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[4]~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[4]~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[4]~3_I .lut_mask = "00AA00AA55FF55FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~17_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add7~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~18 )); defparam \fp_pow_0002:fp_pow_inst|Add7~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~17_I .lut_mask = "0000FFFF0000CCCC"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[5] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[5]~4_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[5] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[5]~4 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[5]~4_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[5]~4_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[5]~4_I .lut_mask = "00AA00AA55FF55FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~21_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][6] ), .cin(\fp_pow_0002:fp_pow_inst|Add7~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~22 )); defparam \fp_pow_0002:fp_pow_inst|Add7~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~21_I .lut_mask = "0000FFFF0000FF00"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[6] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[6]~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][6] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[6] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[6]~5 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[6]~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[6]~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[6]~5_I .lut_mask = "0A5F0A5F0A5F0A5F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|delay_signals[0][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist138|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~25_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add7~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~26 )); defparam \fp_pow_0002:fp_pow_inst|Add7~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~25_I .lut_mask = "0000FFFF0000F0F0"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[7] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[7]~6_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][7] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[7] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[7]~6 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[7]~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[7]~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[7]~6_I .lut_mask = "0A0A0A0A5F5F5F5F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~29_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][8] ), .cin(\fp_pow_0002:fp_pow_inst|Add7~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~30 )); defparam \fp_pow_0002:fp_pow_inst|Add7~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~29_I .lut_mask = "0000FFFF0000FF00"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[8] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[8]~7_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][8] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[8] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[8]~7 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[8]~7_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[8]~7_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[8]~7_I .lut_mask = "0A0A0A0A5F5F5F5F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~33_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][9] ), .cin(\fp_pow_0002:fp_pow_inst|Add7~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~34 )); defparam \fp_pow_0002:fp_pow_inst|Add7~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~33_I .lut_mask = "0000FFFF0000F0F0"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[9] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[9]~8_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][9] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[9] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[9]~8 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[9]~8_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[9]~8_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[9]~8_I .lut_mask = "0A5F0A5F0A5F0A5F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~37_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][10] ), .cin(\fp_pow_0002:fp_pow_inst|Add7~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~38 )); defparam \fp_pow_0002:fp_pow_inst|Add7~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~37_I .lut_mask = "0000FFFF0000F0F0"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[10] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[10]~9_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][10] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[10] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[10]~9 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[10]~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[10]~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[10]~9_I .lut_mask = "0A0A0A0A5F5F5F5F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~41_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][11] ), .cin(\fp_pow_0002:fp_pow_inst|Add7~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~42 )); defparam \fp_pow_0002:fp_pow_inst|Add7~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~41_I .lut_mask = "0000FFFF0000F0F0"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[11] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[11]~10_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][11] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[11] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[11]~10 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[11]~10_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[11]~10_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[11]~10_I .lut_mask = "0A0A0A0A5F5F5F5F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~45_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][12] ), .cin(\fp_pow_0002:fp_pow_inst|Add7~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~46 )); defparam \fp_pow_0002:fp_pow_inst|Add7~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~45_I .lut_mask = "0000FFFF0000F0F0"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[12] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[12]~11_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][12] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[12] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[12]~11 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[12]~11_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[12]~11_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[12]~11_I .lut_mask = "0000F0F00F0FFFFF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~49_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][13] ), .cin(\fp_pow_0002:fp_pow_inst|Add7~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~50 )); defparam \fp_pow_0002:fp_pow_inst|Add7~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~49_I .lut_mask = "0000FFFF0000CCCC"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[13] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[13]~12_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][13] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[13] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[13]~12 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[13]~12_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[13]~12_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[13]~12_I .lut_mask = "505050505F5F5F5F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~53_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][14] ), .cin(\fp_pow_0002:fp_pow_inst|Add7~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~54 )); defparam \fp_pow_0002:fp_pow_inst|Add7~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~53_I .lut_mask = "0000FFFF0000AAAA"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[14] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[14]~13_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][14] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[14] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[14]~13 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[14]~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[14]~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[14]~13_I .lut_mask = "0F0F00000F0FFFFF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~57_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][15] ), .cin(\fp_pow_0002:fp_pow_inst|Add7~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~57 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~58 )); defparam \fp_pow_0002:fp_pow_inst|Add7~57_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~57_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~57_I .lut_mask = "0000FFFF0000F0F0"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~57 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[15] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[15]~14_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[15] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][15] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[15]~14 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[15]~14_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[15]~14_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[15]~14_I .lut_mask = "0505F5F50505F5F5"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~61_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][16] ), .cin(\fp_pow_0002:fp_pow_inst|Add7~58 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~62 )); defparam \fp_pow_0002:fp_pow_inst|Add7~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~61_I .lut_mask = "0000FFFF0000AAAA"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~61 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[16] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[16]~15_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][16] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[16] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[16]~15 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[16]~15_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[16]~15_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[16]~15_I .lut_mask = "0F0F0F0F00FF00FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~65_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][17] ), .cin(\fp_pow_0002:fp_pow_inst|Add7~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~65 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~66 )); defparam \fp_pow_0002:fp_pow_inst|Add7~65_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~65_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~65_I .lut_mask = "0000FFFF0000F0F0"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~65 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[17] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[17]~16_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][17] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[17] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[17]~16 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[17]~16_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[17]~16_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[17]~16_I .lut_mask = "0A0A0A0A5F5F5F5F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~69_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][18] ), .cin(\fp_pow_0002:fp_pow_inst|Add7~66 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~69 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~70 )); defparam \fp_pow_0002:fp_pow_inst|Add7~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~69_I .lut_mask = "0000FFFF0000AAAA"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~69 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[18] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[18]~17_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][18] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[18] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[18]~17 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[18]~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[18]~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[18]~17_I .lut_mask = "30303F3F30303F3F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~73_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][19] ), .cin(\fp_pow_0002:fp_pow_inst|Add7~70 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~73 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~74 )); defparam \fp_pow_0002:fp_pow_inst|Add7~73_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~73_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~73_I .lut_mask = "0000FFFF0000F0F0"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~73 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[19] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[19]~18_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][19] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[19] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[19]~18 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[19]~18_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[19]~18_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[19]~18_I .lut_mask = "0A0A0A0A5F5F5F5F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~77_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][20] ), .cin(\fp_pow_0002:fp_pow_inst|Add7~74 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~78 )); defparam \fp_pow_0002:fp_pow_inst|Add7~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~77_I .lut_mask = "0000FFFF0000AAAA"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~77 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[20] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[20]~19_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][20] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[20] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[20]~19 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[20]~19_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[20]~19_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[20]~19_I .lut_mask = "00AA00AA55FF55FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~81_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][21] ), .cin(\fp_pow_0002:fp_pow_inst|Add7~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~81 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~82 )); defparam \fp_pow_0002:fp_pow_inst|Add7~81_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~81_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~81_I .lut_mask = "0000FFFF0000F0F0"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~81 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[21] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[21]~20_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[21] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][21] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[21]~20 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[21]~20_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[21]~20_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[21]~20_I .lut_mask = "000F000FFF0FFF0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~85_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist137_outputreg|__ALT_INV__delay_signals[0][22] ), .cin(\fp_pow_0002:fp_pow_inst|Add7~82 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~85 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~86 )); defparam \fp_pow_0002:fp_pow_inst|Add7~85_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~85_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~85_I .lut_mask = "0000FFFF0000F0F0"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~85 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[22] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[22]~21_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[22] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][22] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[22]~21 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[22]~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[22]~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[22]~21_I .lut_mask = "05050505AFAFAFAF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~89_I ( .cin(\fp_pow_0002:fp_pow_inst|Add7~86 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~89 ), .cout(\fp_pow_0002:fp_pow_inst|Add7~90 )); defparam \fp_pow_0002:fp_pow_inst|Add7~89_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~89_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~89_I .lut_mask = "000000000000FFFF"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~89 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[23] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[23]~22_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[23] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[23]~22 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[23]~22_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[23]~22_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[23]~22_I .lut_mask = "0000000055555555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add7~93_I ( .cin(\fp_pow_0002:fp_pow_inst|Add7~90 ), .sumout(\fp_pow_0002:fp_pow_inst|Add7~93 )); defparam \fp_pow_0002:fp_pow_inst|Add7~93_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~93_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add7~93_I .lut_mask = "0000FFFF0000FFFF"; dffeas \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add7~93 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[24] )); defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[24] ), .combout(\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 )); defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23_I .lut_mask = "1111111111111111"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~57 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~61 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~65 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add4~69 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_mac \fp_pow_0002:fp_pow_inst|Add8~mac ( .sub(gnd), .negate(gnd), .ax({ax_unconnected_wire_2051,ax_unconnected_wire_2052,ax_unconnected_wire_2053,ax_unconnected_wire_2054,ax_unconnected_wire_2055,ax_unconnected_wire_2056,ax_unconnected_wire_2057,ax_unconnected_wire_2058,ax_unconnected_wire_2059, \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][16] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][16] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][15] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][14] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][13] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][12] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][11] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][10] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][9] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][0] }), .ay({ay_unconnected_wire_2060,ay_unconnected_wire_2061,ay_unconnected_wire_2062,ay_unconnected_wire_2063,ay_unconnected_wire_2064,ay_unconnected_wire_2065,ay_unconnected_wire_2066,ay_unconnected_wire_2067,ay_unconnected_wire_2068, \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[17]~16 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[16]~15 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[15]~14 , \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[14]~13 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[13]~12 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[12]~11 , \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[11]~10 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[10]~9 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[9]~8 , \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[8]~7 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[7]~6 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[6]~5 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[5]~4 , \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[4]~3 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[3]~2 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[2]~1 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[1]~0 , \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[0] }), .bx({\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 , \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 , \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 , \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 , \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[23]~22 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[22]~21 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[21]~20 , \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[20]~19 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[19]~18 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[18]~17 }), .by({by_unconnected_wire_2069,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][17] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][16] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][15] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][14] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][13] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][12] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][11] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][10] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][9] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][0] }), .clk({clk_unconnected_wire_2070,clk_unconnected_wire_2071,\clk~CLKENA0 }), .aclr({\areset~CLKENA0 ,\areset~CLKENA0 }), .ena({ena_unconnected_wire_2072,ena_unconnected_wire_2073,\vcc }), .resulta({\fp_pow_0002:fp_pow_inst|Add8~35 ,\fp_pow_0002:fp_pow_inst|Add8~34 ,\fp_pow_0002:fp_pow_inst|Add8~33 ,\fp_pow_0002:fp_pow_inst|Add8~32 ,\fp_pow_0002:fp_pow_inst|Add8~31 ,\fp_pow_0002:fp_pow_inst|Add8~30 ,\fp_pow_0002:fp_pow_inst|Add8~29 , \fp_pow_0002:fp_pow_inst|Add8~28 ,\fp_pow_0002:fp_pow_inst|Add8~27 ,\fp_pow_0002:fp_pow_inst|Add8~26 ,\fp_pow_0002:fp_pow_inst|Add8~25 ,\fp_pow_0002:fp_pow_inst|Add8~24 ,\fp_pow_0002:fp_pow_inst|Add8~23 ,\fp_pow_0002:fp_pow_inst|Add8~22 , \fp_pow_0002:fp_pow_inst|Add8~21 ,\fp_pow_0002:fp_pow_inst|Add8~20 ,\fp_pow_0002:fp_pow_inst|Add8~19 ,\fp_pow_0002:fp_pow_inst|Add8~18 ,\fp_pow_0002:fp_pow_inst|Add8~17 ,\fp_pow_0002:fp_pow_inst|Add8~16 ,\fp_pow_0002:fp_pow_inst|Add8~15 , \fp_pow_0002:fp_pow_inst|Add8~14 ,\fp_pow_0002:fp_pow_inst|Add8~13 ,\fp_pow_0002:fp_pow_inst|Add8~12 ,\fp_pow_0002:fp_pow_inst|Add8~11 ,\fp_pow_0002:fp_pow_inst|Add8~10 ,\fp_pow_0002:fp_pow_inst|Add8~9 ,\fp_pow_0002:fp_pow_inst|Add8~8 , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][35] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][34] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][33] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][32] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][31] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][30] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][29] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][28] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][27] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][26] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][25] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][24] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][23] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][22] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][21] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][20] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][19] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][18] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][17] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][16] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][15] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][14] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][13] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][12] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][11] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][10] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][9] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][8] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][7] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][6] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][5] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][4] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][3] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][2] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][1] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][0] })); defparam \fp_pow_0002:fp_pow_inst|Add8~mac .signed_max = "true"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .signed_may = "false"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .signed_mbx = "true"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .signed_mby = "false"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .preadder_subtract_a = "false"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .preadder_subtract_b = "false"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .ay_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .by_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .delay_scan_out_ay = "false"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .delay_scan_out_by = "false"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .use_chainadder = "false"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .enable_double_accum = "false"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .operation_mode = "M18X18_SUMOF2"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .operand_source_max = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .operand_source_may = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .operand_source_mbx = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .operand_source_mby = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .ax_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .ay_scan_in_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .az_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .bx_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .by_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .bz_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .coef_sel_a_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .coef_sel_b_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .sub_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .negate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .accumulate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .load_const_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .output_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .coef_a_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .coef_a_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .coef_a_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .coef_a_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .coef_a_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .coef_a_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .coef_a_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .coef_a_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .coef_b_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .coef_b_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .coef_b_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .coef_b_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .coef_b_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .coef_b_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .coef_b_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .coef_b_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .ax_width = 18; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .ay_scan_in_width = 18; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .bx_width = 18; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .by_width = 18; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .mode_sub_location = 0; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .load_const_value = 0; defparam \fp_pow_0002:fp_pow_inst|Add8~mac .result_a_width = 64; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][35]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][35] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][35]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][35]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][35]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][35]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][35]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][35]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][7]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][35] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][7]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_mac \fp_pow_0002:fp_pow_inst|Mult6~mac ( .sub(gnd), .negate(gnd), .ax({ax_unconnected_wire_2074,ax_unconnected_wire_2075,ax_unconnected_wire_2076,ax_unconnected_wire_2077,ax_unconnected_wire_2078,ax_unconnected_wire_2079,ax_unconnected_wire_2080,ax_unconnected_wire_2081,ax_unconnected_wire_2082, \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 , \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 , \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 , \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[24]~23 , \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[23]~22 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[22]~21 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[21]~20 , \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[20]~19 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[19]~18 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[18]~17 }), .ay({ay_unconnected_wire_2083,ay_unconnected_wire_2084,ay_unconnected_wire_2085,ay_unconnected_wire_2086,ay_unconnected_wire_2087,ay_unconnected_wire_2088,ay_unconnected_wire_2089,ay_unconnected_wire_2090, \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][16] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][16] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][16] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][15] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][14] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][13] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][12] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][11] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][10] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][9] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][7] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][4] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][1] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist23|delay_signals[0][0] }), .clk({clk_unconnected_wire_2091,clk_unconnected_wire_2092,\clk~CLKENA0 }), .aclr({\areset~CLKENA0 ,\areset~CLKENA0 }), .ena({ena_unconnected_wire_2093,ena_unconnected_wire_2094,\vcc }), .resulta({\fp_pow_0002:fp_pow_inst|Mult6~47 ,\fp_pow_0002:fp_pow_inst|Mult6~46 ,\fp_pow_0002:fp_pow_inst|Mult6~45 ,\fp_pow_0002:fp_pow_inst|Mult6~44 ,\fp_pow_0002:fp_pow_inst|Mult6~43 ,\fp_pow_0002:fp_pow_inst|Mult6~42 ,\fp_pow_0002:fp_pow_inst|Mult6~41 , \fp_pow_0002:fp_pow_inst|Mult6~40 ,\fp_pow_0002:fp_pow_inst|Mult6~39 ,\fp_pow_0002:fp_pow_inst|Mult6~38 ,\fp_pow_0002:fp_pow_inst|Mult6~37 ,\fp_pow_0002:fp_pow_inst|Mult6~36 ,\fp_pow_0002:fp_pow_inst|Mult6~35 ,\fp_pow_0002:fp_pow_inst|Mult6~34 , \fp_pow_0002:fp_pow_inst|Mult6~33 ,\fp_pow_0002:fp_pow_inst|Mult6~32 ,\fp_pow_0002:fp_pow_inst|Mult6~31 ,\fp_pow_0002:fp_pow_inst|Mult6~30 ,\fp_pow_0002:fp_pow_inst|Mult6~29 ,\fp_pow_0002:fp_pow_inst|Mult6~28 ,\fp_pow_0002:fp_pow_inst|Mult6~27 , \fp_pow_0002:fp_pow_inst|Mult6~26 ,\fp_pow_0002:fp_pow_inst|Mult6~25 ,\fp_pow_0002:fp_pow_inst|Mult6~24 ,\fp_pow_0002:fp_pow_inst|Mult6~23 ,\fp_pow_0002:fp_pow_inst|Mult6~22 ,\fp_pow_0002:fp_pow_inst|Mult6~21 ,\fp_pow_0002:fp_pow_inst|Mult6~20 , \fp_pow_0002:fp_pow_inst|Mult6~19 ,\fp_pow_0002:fp_pow_inst|Mult6~18 ,\fp_pow_0002:fp_pow_inst|Mult6~17 ,\fp_pow_0002:fp_pow_inst|Mult6~16 ,\fp_pow_0002:fp_pow_inst|Mult6~15 ,\fp_pow_0002:fp_pow_inst|Mult6~14 ,\fp_pow_0002:fp_pow_inst|Mult6~13 , \fp_pow_0002:fp_pow_inst|Mult6~12 ,\fp_pow_0002:fp_pow_inst|Mult6~11 ,\fp_pow_0002:fp_pow_inst|Mult6~10 ,\fp_pow_0002:fp_pow_inst|Mult6~9 ,\fp_pow_0002:fp_pow_inst|Mult6~8 ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][23] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][22] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][21] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][20] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][19] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][18] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][17] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][16] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][15] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][14] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][13] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][12] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][11] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][10] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][9] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][8] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][7] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][6] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][5] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][4] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][3] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][2] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][1] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][0] })); defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .signed_max = "true"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .signed_may = "true"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .signed_mbx = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .signed_mby = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .preadder_subtract_a = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .preadder_subtract_b = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .ay_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .by_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .delay_scan_out_ay = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .delay_scan_out_by = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .use_chainadder = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .enable_double_accum = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .operation_mode = "M18X18_FULL"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .operand_source_max = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .operand_source_may = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .operand_source_mbx = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .operand_source_mby = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .ax_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .ay_scan_in_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .az_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .bx_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .by_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .bz_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .coef_sel_a_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .coef_sel_b_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .sub_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .negate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .accumulate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .load_const_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .output_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .coef_a_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .coef_a_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .coef_a_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .coef_a_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .coef_a_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .coef_a_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .coef_a_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .coef_a_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .coef_b_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .coef_b_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .coef_b_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .coef_b_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .coef_b_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .coef_b_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .coef_b_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .coef_b_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .ax_width = 18; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .ay_scan_in_width = 19; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .mode_sub_location = 0; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .load_const_value = 0; defparam \fp_pow_0002:fp_pow_inst|Mult6~mac .result_a_width = 64; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][59]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][23] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][59]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][59]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][59]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][59]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][59]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][59]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][59] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][59]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][59]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][59] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][58]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][22] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][58]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][58]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][58]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][58]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][58]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][58]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][58] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][58]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][58]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][58] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][57]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][21] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][57]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][57]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][57]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][57]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][57]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][57]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][57] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][57]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][57]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][57] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][56]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][20] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][56]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][56]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][56]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][56]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][56]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][56]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][56] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][56]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][56]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][4]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][56] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][4]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][4]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][55]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][19] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][55]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][55]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][55]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][55]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][55]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][55]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][55] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][55]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][55]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][3]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][55] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][3]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][54]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][18] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][54]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][54]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][54]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][54]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][54]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][54]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][54] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][54]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][54]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][54] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][53]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][17] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][53]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][53]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][53]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][53]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][53]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][53]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][53] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][53]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][53]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][53] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][52]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][16] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][52]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][52]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][52]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][52]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][52]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][52]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][52] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][52]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][52]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][0]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][52] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][0]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist8|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][34] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][34] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist7|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][51]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][15] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][51]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][51]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][51]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][51]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][51]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][51]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][51] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][51]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][51]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][33]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][33] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][33]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][33]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][33]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][33]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][33]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][32]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][32] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][32]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][32]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][32]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][32]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][32]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][50]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][14] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][50]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][50]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][50]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][50]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][50]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][50]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][50] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][50]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][50]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][49]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][49] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][49]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][49]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][31]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][31] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][31]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][31]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][31]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][31]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][31]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][30]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][30] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][30]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][30]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][30]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][30]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][30]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][48]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][12] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][48]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][48]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][48]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][48]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][48]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][48]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][48] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][48]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][48]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][47]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][11] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][47]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][47]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][47]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][47]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][47]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][47]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][47] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][47]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][47]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][29]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][29] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][29]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][29]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][29]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][29]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][29]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][29]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][28] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][46]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][10] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][46]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][46]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][46]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][46]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][46]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][46]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][46] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][46]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][46]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][45]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][9] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][45]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][45]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][45]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][45]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][45]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][45]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][45] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][45]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][45]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][27] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][27]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][44]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][44] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][44]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][44]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][26] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][43]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][7] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][43]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][43]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][43]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][43]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][43]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][43]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][43] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][43]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][43]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][25]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][25] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][25]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][25]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][25]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][25]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][25]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][42]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][42]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][42]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][42]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][42]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][42]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][42]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][42] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][42]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][24]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][24] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][24]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][24]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][24]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][24]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][24]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][41]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][41]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][41]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][41]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][41]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][41]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][41]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][41] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][41]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][23] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][22]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][22] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][22]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][22]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][22]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][22]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][22]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][40]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][40]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][40]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][40]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][40]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][40]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][40]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][40] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][40]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][39]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][39]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][39]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][39]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][39]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][39]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][39]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][39] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][39]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][21]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][21] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][21]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][21]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][21]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][21]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][21]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][20] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][38]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][38] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][38]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][19]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][19] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][19]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][19]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][19]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][19]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][19]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][37]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][37] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][37]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][36]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im8_cma_s[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][36]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][36]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][36]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][36]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][36]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][36]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][36] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][36]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_mac \fp_pow_0002:fp_pow_inst|Mult7~mac ( .sub(gnd), .negate(gnd), .ax({ax_unconnected_wire_2095,ax_unconnected_wire_2096,ax_unconnected_wire_2097,ax_unconnected_wire_2098,ax_unconnected_wire_2099,ax_unconnected_wire_2100,ax_unconnected_wire_2101,ax_unconnected_wire_2102,ax_unconnected_wire_2103, \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][17] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][16] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][15] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][14] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][13] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][12] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][11] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][10] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][9] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist24|delay_signals[0][0] }), .ay({ay_unconnected_wire_2104,ay_unconnected_wire_2105,ay_unconnected_wire_2106,ay_unconnected_wire_2107,ay_unconnected_wire_2108,ay_unconnected_wire_2109,ay_unconnected_wire_2110,ay_unconnected_wire_2111,ay_unconnected_wire_2112, \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[17]~16 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[16]~15 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[15]~14 , \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[14]~13 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[13]~12 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[12]~11 , \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[11]~10 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[10]~9 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[9]~8 , \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[8]~7 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[7]~6 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[6]~5 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[5]~4 , \fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[4]~3 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[3]~2 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[2]~1 ,\fp_pow_0002:fp_pow_inst|multTermOneLog_uid66_fpPowrTest_q[1]~0 , \fp_pow_0002:fp_pow_inst|oMzLog_uid62_fpPowrTest_o[0] }), .clk({clk_unconnected_wire_2113,clk_unconnected_wire_2114,\clk~CLKENA0 }), .aclr({\areset~CLKENA0 ,\areset~CLKENA0 }), .ena({ena_unconnected_wire_2115,ena_unconnected_wire_2116,\vcc }), .resulta({\fp_pow_0002:fp_pow_inst|Mult7~35 ,\fp_pow_0002:fp_pow_inst|Mult7~34 ,\fp_pow_0002:fp_pow_inst|Mult7~33 ,\fp_pow_0002:fp_pow_inst|Mult7~32 ,\fp_pow_0002:fp_pow_inst|Mult7~31 ,\fp_pow_0002:fp_pow_inst|Mult7~30 ,\fp_pow_0002:fp_pow_inst|Mult7~29 , \fp_pow_0002:fp_pow_inst|Mult7~28 ,\fp_pow_0002:fp_pow_inst|Mult7~27 ,\fp_pow_0002:fp_pow_inst|Mult7~26 ,\fp_pow_0002:fp_pow_inst|Mult7~25 ,\fp_pow_0002:fp_pow_inst|Mult7~24 ,\fp_pow_0002:fp_pow_inst|Mult7~23 ,\fp_pow_0002:fp_pow_inst|Mult7~22 , \fp_pow_0002:fp_pow_inst|Mult7~21 ,\fp_pow_0002:fp_pow_inst|Mult7~20 ,\fp_pow_0002:fp_pow_inst|Mult7~19 ,\fp_pow_0002:fp_pow_inst|Mult7~18 ,\fp_pow_0002:fp_pow_inst|Mult7~17 ,\fp_pow_0002:fp_pow_inst|Mult7~16 ,\fp_pow_0002:fp_pow_inst|Mult7~15 , \fp_pow_0002:fp_pow_inst|Mult7~14 ,\fp_pow_0002:fp_pow_inst|Mult7~13 ,\fp_pow_0002:fp_pow_inst|Mult7~12 ,\fp_pow_0002:fp_pow_inst|Mult7~11 ,\fp_pow_0002:fp_pow_inst|Mult7~10 ,\fp_pow_0002:fp_pow_inst|Mult7~9 ,\fp_pow_0002:fp_pow_inst|Mult7~8 , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][35] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][34] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][33] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][32] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][31] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][30] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][29] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][28] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][27] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][26] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][25] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][24] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][23] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][22] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][21] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][20] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][19] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][18] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][17] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][16] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][15] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][14] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][13] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][12] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][11] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][10] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][9] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][8] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][7] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][6] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][5] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][4] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][3] , \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][2] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][1] ,\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][0] })); defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .signed_max = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .signed_may = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .signed_mbx = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .signed_mby = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .preadder_subtract_a = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .preadder_subtract_b = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .ay_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .by_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .delay_scan_out_ay = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .delay_scan_out_by = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .use_chainadder = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .enable_double_accum = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .operation_mode = "M18X18_FULL"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .operand_source_max = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .operand_source_may = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .operand_source_mbx = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .operand_source_mby = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .ax_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .ay_scan_in_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .az_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .bx_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .by_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .bz_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .coef_sel_a_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .coef_sel_b_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .sub_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .negate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .accumulate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .load_const_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .output_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .coef_a_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .coef_a_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .coef_a_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .coef_a_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .coef_a_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .coef_a_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .coef_a_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .coef_a_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .coef_b_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .coef_b_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .coef_b_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .coef_b_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .coef_b_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .coef_b_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .coef_b_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .coef_b_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .ax_width = 18; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .ay_scan_in_width = 18; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .mode_sub_location = 0; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .load_const_value = 0; defparam \fp_pow_0002:fp_pow_inst|Mult7~mac .result_a_width = 64; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][35]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][35] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][35]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][35]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][35]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][35]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][35]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][35]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][16]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][16] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][16]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][16]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][16]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][16]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][16]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][34]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][34] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][34]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][34]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][34]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][34]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][34]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][33]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][33] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][33]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][33]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][33]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][33]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][33]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][33]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][14]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][14] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][14]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][14]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][14]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][14]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][14]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][32]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][32] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][32]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][32]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][32]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][32]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][32]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][32]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][31]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][31] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][31]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][31]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][31]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][31]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][31]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][31]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][30]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][30] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][30]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][30]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][30]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][30]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][30]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][11]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][11] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][11]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][11]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][11]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][11]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][11]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][29] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][10]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][10] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][10]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][10]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][10]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][10]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][10]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][28]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][28] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][28]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][28]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][28]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][28]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][28]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][28]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][27]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][27] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][27]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][27]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][27]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][27]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][27]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][26]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][26] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][26]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][26]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][26]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][26]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][26]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][8]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][8] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][8]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][8]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][8]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][8]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][8]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][25]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][25] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][25]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][25]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][25]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][25]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][25]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][6]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][6]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][24]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][24] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][24]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][24]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][24]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][24]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][24]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][5]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][5]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][23]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][23] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][23]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][23]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][23]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][23]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][23]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][4]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][4]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][4]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][22] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][2]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][2]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][20]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][20] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][20]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][20]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][20]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][20]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][20]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_ma3_cma_s[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist1|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][18]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][18] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][18]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][18]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][18]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][18]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][18]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~93_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][18] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add9~93 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~94 )); defparam \fp_pow_0002:fp_pow_inst|Add9~93_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~93_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~93_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~133_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][19] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~94 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~133 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~134 )); defparam \fp_pow_0002:fp_pow_inst|Add9~133_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~133_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~133_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~129_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][2] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][20] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~134 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~129 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~130 )); defparam \fp_pow_0002:fp_pow_inst|Add9~129_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~129_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~129_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~125_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][21] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~130 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~125 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~126 )); defparam \fp_pow_0002:fp_pow_inst|Add9~125_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~125_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~125_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~121_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][22] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~126 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~121 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~122 )); defparam \fp_pow_0002:fp_pow_inst|Add9~121_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~121_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~121_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~117_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][23] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~122 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~117 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~118 )); defparam \fp_pow_0002:fp_pow_inst|Add9~117_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~117_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~117_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~89_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][6] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~118 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~89 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~90 )); defparam \fp_pow_0002:fp_pow_inst|Add9~89_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~89_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~89_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~113_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][7] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][25] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~90 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~113 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~114 )); defparam \fp_pow_0002:fp_pow_inst|Add9~113_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~113_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~113_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~109_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][26] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][8] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~114 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~109 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~110 )); defparam \fp_pow_0002:fp_pow_inst|Add9~109_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~109_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~109_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~105_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][9] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][27] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~110 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~105 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~106 )); defparam \fp_pow_0002:fp_pow_inst|Add9~105_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~105_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~105_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~101_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][10] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][28] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~106 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~101 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~102 )); defparam \fp_pow_0002:fp_pow_inst|Add9~101_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~101_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~101_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~97_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][11] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][29] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~102 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~97 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~98 )); defparam \fp_pow_0002:fp_pow_inst|Add9~97_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~97_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~97_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~21_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][12] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][30] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~98 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~22 )); defparam \fp_pow_0002:fp_pow_inst|Add9~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~21_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~17_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][13] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][31] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~18 )); defparam \fp_pow_0002:fp_pow_inst|Add9~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~17_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~13_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][14] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][32] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~14 )); defparam \fp_pow_0002:fp_pow_inst|Add9~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~13_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~9_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][33] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][15] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~10 )); defparam \fp_pow_0002:fp_pow_inst|Add9~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~9_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~5_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][16] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][34] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~6 )); defparam \fp_pow_0002:fp_pow_inst|Add9~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~5_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][17] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][35] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~1 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~2 )); defparam \fp_pow_0002:fp_pow_inst|Add9~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~1_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~45_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][18] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][36] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~2 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~46 )); defparam \fp_pow_0002:fp_pow_inst|Add9~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~45_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~41_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][19] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][37] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~42 )); defparam \fp_pow_0002:fp_pow_inst|Add9~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~41_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~37_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][20] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][38] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~38 )); defparam \fp_pow_0002:fp_pow_inst|Add9~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~37_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~33_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][39] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][21] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~34 )); defparam \fp_pow_0002:fp_pow_inst|Add9~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~33_I .lut_mask = "0000FF0000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~29_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][22] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][40] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~30 )); defparam \fp_pow_0002:fp_pow_inst|Add9~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~29_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~25_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][41] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][23] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~26 )); defparam \fp_pow_0002:fp_pow_inst|Add9~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~25_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~53_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][42] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~54 )); defparam \fp_pow_0002:fp_pow_inst|Add9~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~53_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~73_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][25] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~73 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~74 )); defparam \fp_pow_0002:fp_pow_inst|Add9~73_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~73_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~73_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~69_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][44] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][26] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~74 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~69 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~70 )); defparam \fp_pow_0002:fp_pow_inst|Add9~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~69_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~65_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][45] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][27] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~70 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~65 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~66 )); defparam \fp_pow_0002:fp_pow_inst|Add9~65_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~65_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~65_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~61_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][28] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][46] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~66 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~62 )); defparam \fp_pow_0002:fp_pow_inst|Add9~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~61_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~57_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][47] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][29] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~57 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~58 )); defparam \fp_pow_0002:fp_pow_inst|Add9~57_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~57_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~57_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~49_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][30] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][48] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~58 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~50 )); defparam \fp_pow_0002:fp_pow_inst|Add9~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~49_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~85_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][49] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][31] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~85 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~86 )); defparam \fp_pow_0002:fp_pow_inst|Add9~85_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~85_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~85_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~81_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][32] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][50] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~86 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~81 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~82 )); defparam \fp_pow_0002:fp_pow_inst|Add9~81_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~81_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~81_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~77_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][51] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist1|__ALT_INV__delay_signals[0][33] ), .cin(\fp_pow_0002:fp_pow_inst|Add9~82 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add9~78 )); defparam \fp_pow_0002:fp_pow_inst|Add9~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~77_I .lut_mask = "0000FF0000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add9~137_I ( .cin(\fp_pow_0002:fp_pow_inst|Add9~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add9~137 )); defparam \fp_pow_0002:fp_pow_inst|Add9~137_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~137_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add9~137_I .lut_mask = "0000FFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[53]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~137 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[53] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[53]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[53]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add10~34_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[53] ), .cin(gnd), .cout(\fp_pow_0002:fp_pow_inst|Add10~34 )); defparam \fp_pow_0002:fp_pow_inst|Add10~34_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add10~34_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add10~34_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add10~9_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist7|__ALT_INV__delay_signals[0][0] ), .cin(\fp_pow_0002:fp_pow_inst|Add10~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add10~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add10~10 )); defparam \fp_pow_0002:fp_pow_inst|Add10~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add10~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add10~9_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add10~5_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist7|__ALT_INV__delay_signals[0][7] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][1] ), .cin(\fp_pow_0002:fp_pow_inst|Add10~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add10~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add10~6 )); defparam \fp_pow_0002:fp_pow_inst|Add10~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add10~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add10~5_I .lut_mask = "0000FF0000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add10~17_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist7|__ALT_INV__delay_signals[0][7] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][2] ), .cin(\fp_pow_0002:fp_pow_inst|Add10~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add10~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add10~18 )); defparam \fp_pow_0002:fp_pow_inst|Add10~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add10~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add10~17_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add10~13_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist7|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add10~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add10~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add10~14 )); defparam \fp_pow_0002:fp_pow_inst|Add10~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add10~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add10~13_I .lut_mask = "0000FF0000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add10~29_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist7|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add10~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add10~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add10~30 )); defparam \fp_pow_0002:fp_pow_inst|Add10~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add10~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add10~29_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add10~25_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist7|__ALT_INV__delay_signals[0][7] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add10~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add10~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add10~26 )); defparam \fp_pow_0002:fp_pow_inst|Add10~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add10~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add10~25_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add10~21_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][6] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist7|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add10~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add10~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add10~22 )); defparam \fp_pow_0002:fp_pow_inst|Add10~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add10~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add10~21_I .lut_mask = "0000CCCC00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add10~1_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist7|__ALT_INV__delay_signals[0][7] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist8|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add10~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add10~1 )); defparam \fp_pow_0002:fp_pow_inst|Add10~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add10~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add10~1_I .lut_mask = "0000CCCC00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add10~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[8] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][43]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~113 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][43] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][43]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][43]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][42]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~117 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][42] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][42]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][41]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~121 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][41] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][41]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][40]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~101 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][40] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][40]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][39]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~125 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][39] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][39]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add10~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[7] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][38]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~129 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][38] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][38]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~133 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][37] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][37]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add10~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[6] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][36]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~137 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][36] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][36]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add10~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[5] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~105 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][35]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add10~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[4] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~109 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][34]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add10~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[3] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~81 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][33]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add10~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[2] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~85 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][32]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add10~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[1] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~89 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][31]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[52]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~77 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[52] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[52]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[52]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][51]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[52] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][51] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][51]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][51]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[51]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~81 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[51] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[51]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[51]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][50]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[51] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][50] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][50]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][50]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~93 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][30]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[50]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~85 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[50] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[50]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[50]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][49]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[50] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][49]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][49]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][49]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][49]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][49]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][49]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][49]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][49]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][49]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][49]~DUPLICATE_I .created_from = "Q(delay_signals[0][49])"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~97 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][29]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][28]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[49]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[49] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[49]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[49]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][48]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[49] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][48]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][48]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][48]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][48]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][48]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][48]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][48] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][48]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][48]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[48]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~57 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[48] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[48]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[48]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][47]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[48] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][47] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][47]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][47]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~61 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][27]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~65 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][26]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[47]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~61 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[47] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[47]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[47]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][46]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[47] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][46] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][46]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][46]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[46]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~65 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[46] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[46]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[46]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][45]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[46] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][45]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][45]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][45]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][45]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][45]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][45]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][45] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][45]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][45]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~69 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[45]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~69 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[45] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[45]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[45]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][44]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[45] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][44]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][44]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][44]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][44]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][44]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][44]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][44] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][44]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][44]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~73 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][24]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[44]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~73 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[44] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[44]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[44]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][43]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[44] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][43] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][43]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][43]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~77 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][23]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~57 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[43]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[43] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[43]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[43]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][42]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[43] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][42]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][42]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][42]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][42]~DUPLICATE_I .created_from = "Q(delay_signals[0][42])"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[42]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[42] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[42]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][41]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[42] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][41]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][41]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][41]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][41]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][41]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][41]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][41] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][41]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[41]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[41] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[41]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][40]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[41] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][40] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][40]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[40]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[40] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[40]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][39]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[40] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][39] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][39]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[39]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[39] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[39]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][38]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[39] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][38] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][38]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[38]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[38] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[38]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][37]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[38] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][37]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][37]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][37]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][37]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][37]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][37] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][37]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[37] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[37]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][36]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[37] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][36] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][36]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[36]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[36] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[36]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[36] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][35]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[35] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[35]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][34]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[35] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][34]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][34]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][34]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][34]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][34]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][34]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[34] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[34]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[34] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][33]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[33] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][32]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[33] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][32]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][32]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][32]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][32]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][32]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][32]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[32] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[32]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[32] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][31]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[31] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[31]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[31] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][30]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~97 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[30] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[30]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[30] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][29]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~141 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~145 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~101 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[29] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][28]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[29] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][28]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][28]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][28]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][28]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][28]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][28]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add14~149 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~105 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[28] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[28]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[28] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~21 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~1 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~1_I .lut_mask = "7FFFFFFF80000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~109 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[27] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][26]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[27] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][26]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][26]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][26]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][26]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][26]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][26]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~113 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[26] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][25]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[26] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][25]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][25]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][25]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][25]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][25]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~17 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~2 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~2_I .lut_mask = "7F807F80FF00FF00"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~0 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~0_I .lut_mask = "6C6C6C6CCCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~89 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[25] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[25] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][24]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~117 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[24] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][23]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[24] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][23]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][23]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][23]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][23]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][23]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~3_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~9 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~3 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~3_I .lut_mask = "5A5A5A5AF0F0F0F0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~3 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~121 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[23] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[23]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[23] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram0~4_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~1 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add13~5 ), .combout(\fp_pow_0002:fp_pow_inst|Ram0~4 )); defparam \fp_pow_0002:fp_pow_inst|Ram0~4_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~4_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram0~4_I .lut_mask = "5555AAAA5555AAAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram0~4 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][2]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][2]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~125 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[22] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[22] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add13~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist72|delay_signals[0][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist71|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~177_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][21] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][1] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add15~177 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~178 )); defparam \fp_pow_0002:fp_pow_inst|Add15~177_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~177_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~177_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~173_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][22] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][2] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~178 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~173 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~174 )); defparam \fp_pow_0002:fp_pow_inst|Add15~173_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~173_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~173_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~169_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][23] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][3] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~174 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~169 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~170 )); defparam \fp_pow_0002:fp_pow_inst|Add15~169_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~169_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~169_I .lut_mask = "0000AAAA00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~145_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~170 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~145 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~146 )); defparam \fp_pow_0002:fp_pow_inst|Add15~145_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~145_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~145_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~165_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][25] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~146 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~165 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~166 )); defparam \fp_pow_0002:fp_pow_inst|Add15~165_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~165_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~165_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~161_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][6] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][26] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~166 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~161 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~162 )); defparam \fp_pow_0002:fp_pow_inst|Add15~161_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~161_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~161_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~157_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][7] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][27] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~162 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~157 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~158 )); defparam \fp_pow_0002:fp_pow_inst|Add15~157_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~157_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~157_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~153_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][8] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][28] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~158 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~153 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~154 )); defparam \fp_pow_0002:fp_pow_inst|Add15~153_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~153_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~153_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~149_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][29] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][9] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~154 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~149 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~150 )); defparam \fp_pow_0002:fp_pow_inst|Add15~149_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~149_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~149_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~25_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][10] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][30] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~150 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~26 )); defparam \fp_pow_0002:fp_pow_inst|Add15~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~25_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~21_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][11] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][31] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~22 )); defparam \fp_pow_0002:fp_pow_inst|Add15~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~21_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~17_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][32] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][12] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~18 )); defparam \fp_pow_0002:fp_pow_inst|Add15~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~17_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~13_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][13] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][33] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~14 )); defparam \fp_pow_0002:fp_pow_inst|Add15~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~13_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~9_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][34] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][14] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~10 )); defparam \fp_pow_0002:fp_pow_inst|Add15~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~9_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~5_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][35] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][15] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~6 )); defparam \fp_pow_0002:fp_pow_inst|Add15~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~5_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~49_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][36] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][16] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~50 )); defparam \fp_pow_0002:fp_pow_inst|Add15~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~49_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~45_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][17] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][37] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~46 )); defparam \fp_pow_0002:fp_pow_inst|Add15~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~45_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~41_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][38] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][18] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~42 )); defparam \fp_pow_0002:fp_pow_inst|Add15~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~41_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~37_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][39] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][19] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~38 )); defparam \fp_pow_0002:fp_pow_inst|Add15~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~37_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~33_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][20] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][40] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~34 )); defparam \fp_pow_0002:fp_pow_inst|Add15~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~33_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~29_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][21] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][41] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~30 )); defparam \fp_pow_0002:fp_pow_inst|Add15~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~29_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~57_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][22] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][42]~DUPLICATE ), .cin(\fp_pow_0002:fp_pow_inst|Add15~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~57 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~58 )); defparam \fp_pow_0002:fp_pow_inst|Add15~57_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~57_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~57_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~77_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][43] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][23] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~58 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~78 )); defparam \fp_pow_0002:fp_pow_inst|Add15~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~77_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~73_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][44] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~73 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~74 )); defparam \fp_pow_0002:fp_pow_inst|Add15~73_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~73_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~73_I .lut_mask = "0000FF0000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~69_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][45] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][25] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~74 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~69 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~70 )); defparam \fp_pow_0002:fp_pow_inst|Add15~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~69_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~65_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][26] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][46] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~70 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~65 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~66 )); defparam \fp_pow_0002:fp_pow_inst|Add15~65_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~65_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~65_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~61_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][47] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][27] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~66 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~62 )); defparam \fp_pow_0002:fp_pow_inst|Add15~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~61_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~53_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][28] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][48] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~54 )); defparam \fp_pow_0002:fp_pow_inst|Add15~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~53_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~97_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][49]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][29] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~97 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~98 )); defparam \fp_pow_0002:fp_pow_inst|Add15~97_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~97_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~97_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~93_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][50] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][30] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~98 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~93 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~94 )); defparam \fp_pow_0002:fp_pow_inst|Add15~93_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~93_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~93_I .lut_mask = "0000FF0000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~89_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][31] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|__ALT_INV__delay_signals[0][51] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~94 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~89 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~90 )); defparam \fp_pow_0002:fp_pow_inst|Add15~89_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~89_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~89_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~85_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][32] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[1] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~90 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~85 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~86 )); defparam \fp_pow_0002:fp_pow_inst|Add15~85_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~85_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~85_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~81_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][33] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[2] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~86 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~81 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~82 )); defparam \fp_pow_0002:fp_pow_inst|Add15~81_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~81_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~81_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~109_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][34] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[3] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~82 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~109 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~110 )); defparam \fp_pow_0002:fp_pow_inst|Add15~109_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~109_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~109_I .lut_mask = "0000FF0000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~105_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][35] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[4] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~110 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~105 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~106 )); defparam \fp_pow_0002:fp_pow_inst|Add15~105_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~105_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~105_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~141_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][36] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[5] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~106 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~141 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~142 )); defparam \fp_pow_0002:fp_pow_inst|Add15~141_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~141_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~141_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~137_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][37] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~142 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~137 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~138 )); defparam \fp_pow_0002:fp_pow_inst|Add15~137_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~137_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~137_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~133_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[7] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][38] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~138 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~133 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~134 )); defparam \fp_pow_0002:fp_pow_inst|Add15~133_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~133_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~133_I .lut_mask = "0000FF0000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~129_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][39] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[8] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~134 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~129 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~130 )); defparam \fp_pow_0002:fp_pow_inst|Add15~129_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~129_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~129_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~101_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][40] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[8] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~130 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~101 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~102 )); defparam \fp_pow_0002:fp_pow_inst|Add15~101_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~101_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~101_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~125_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][41] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[8] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~102 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~125 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~126 )); defparam \fp_pow_0002:fp_pow_inst|Add15~125_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~125_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~125_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~121_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][42] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[8] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~126 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~121 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~122 )); defparam \fp_pow_0002:fp_pow_inst|Add15~121_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~121_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~121_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~117_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][43] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[8] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~122 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~117 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~118 )); defparam \fp_pow_0002:fp_pow_inst|Add15~117_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~117_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~117_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~113_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][44] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[8] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~118 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~113 ), .cout(\fp_pow_0002:fp_pow_inst|Add15~114 )); defparam \fp_pow_0002:fp_pow_inst|Add15~113_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~113_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~113_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add15~1_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist71|__ALT_INV__delay_signals[0][44] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[8] ), .cin(\fp_pow_0002:fp_pow_inst|Add15~114 ), .sumout(\fp_pow_0002:fp_pow_inst|Add15~1 )); defparam \fp_pow_0002:fp_pow_inst|Add15~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add15~1_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[4][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist114|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[4][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[4][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[4][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[3][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[4][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[3][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[3][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[3][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[3][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[45]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~1 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[45] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[45]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[45]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[19]~feeder_I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~37 ), .combout(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[19]~feeder )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[19]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[19]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[19]~feeder_I .lut_mask = "00FF00FF00FF00FF"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[19]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][39] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[19] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[39]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[19] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[39] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[39]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[39]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[39]~I .lut_mask = "5A5A5A5A5A5A5A5A"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][39]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[39] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][39] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][39]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[18]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~41 ), .combout(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[18]~feeder )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[18]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[18]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[18]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[18]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][38] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[18] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[38]~I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[18] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[38] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[38]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[38]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[38]~I .lut_mask = "0F0FF0F00F0FF0F0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][38]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[38] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][38] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][38]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[17]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~45 ), .combout(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[17]~feeder )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[17]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[17]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[17]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[17]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][37] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[17] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[37]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[17] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[37] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[37]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[37]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[37]~I .lut_mask = "55555555AAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[37] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][37] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][37]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[16]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~49 ), .combout(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[16]~feeder )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[16]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[16]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[16]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[16]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][36] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[16] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[36]~I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[16] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[36] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[36]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[36]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[36]~I .lut_mask = "0F0FF0F00F0FF0F0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][36]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[36] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][36] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][36]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[15]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~5 ), .combout(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[15]~feeder )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[15]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[15]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[15]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[15]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][35] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[15] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[35]~I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[15] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[35] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[35]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[35]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[35]~I .lut_mask = "0F0F0F0FF0F0F0F0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[35] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][35]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[14]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~9 ), .combout(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[14]~feeder )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[14]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[14]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[14]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[14]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][34] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[14] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[34]~I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[14] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[34] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[34]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[34]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[34]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[34] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[13]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~13 ), .combout(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[13]~feeder )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[13]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[13]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[13]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[13]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][33] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[13] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[33]~I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[13] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[33] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[33]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[33]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[33]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[33] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[12]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~17 ), .combout(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[12]~feeder )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[12]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[12]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[12]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[12]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][32] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[12] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[32]~I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[12] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[32] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[32]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[32]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[32]~I .lut_mask = "0F0F0F0FF0F0F0F0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[32] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[11]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~21 ), .combout(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[11]~feeder )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[11]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[11]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[11]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[11]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][31] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[11] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[31]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[11] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[31] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[31]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[31]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[31]~I .lut_mask = "55555555AAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[31] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][31]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~25 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][30] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[10] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[30]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[10] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[30] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[30]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[30]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[30]~I .lut_mask = "55555555AAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[30] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][30]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~149 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][29] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[9] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[29]~I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[9] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[29] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[29]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[29]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[29]~I .lut_mask = "0F0FF0F00F0FF0F0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[29] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][29]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~153 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][28] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[8] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[28]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[8] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[28] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[28]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[28]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[28]~I .lut_mask = "55555555AAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[28] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][28]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~157 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][27] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[7] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[27]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[7] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[27] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[27]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[27]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[27]~I .lut_mask = "55555555AAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[27] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][27]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~161 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][26] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[6] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[26]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[6] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[26] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[26]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[26]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[26]~I .lut_mask = "5A5A5A5A5A5A5A5A"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[26] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][26]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~165 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][25] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[5] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[25]~I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[5] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[25] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[25]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[25]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[25]~I .lut_mask = "0F0F0F0FF0F0F0F0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[25] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~145 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][24] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[4] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[24]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[4] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[24] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[24]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[24]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[24]~I .lut_mask = "55555555AAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[24] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][24]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~169 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][23] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[3] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[23]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[3] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[23] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[23]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[23]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[23]~I .lut_mask = "55555555AAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[23] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][23]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~173 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][22] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[2] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[22]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[2] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[22] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[22]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[22]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[22]~I .lut_mask = "55555555AAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[22] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~177 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[1] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[21]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[1] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[21] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[21]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[21]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[21]~I .lut_mask = "55555555AAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~129 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[21] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][20] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[0] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[20]~I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[0] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[20] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[20]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[20]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[20]~I .lut_mask = "0F0FF0F00F0FF0F0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[20] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~133 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[20] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[20] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[19]~I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][19] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[19] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[19]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[19]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[19]~I .lut_mask = "0F0F0F0FF0F0F0F0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add9~93 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[19] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[18]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][18] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[18] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[18]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[18]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[18]~I .lut_mask = "55555555AAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[18] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[17]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][17] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[17] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[17]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[17]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[17]~I .lut_mask = "55555555AAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[17]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[17] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[16]~I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][16] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[16] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[16]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[16]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[16]~I .lut_mask = "00FF00FFFF00FF00"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][15]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][15] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][15]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][15]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][15]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][15]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][15]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[16]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[16] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[15]~I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][15] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[15] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[15]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[15]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[15]~I .lut_mask = "0F0F0F0FF0F0F0F0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][14] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[15]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][14] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[15] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][14] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[14]~I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][14] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[14] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[14]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[14]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[14]~I .lut_mask = "55555555AAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[14] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][13]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][13] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][13]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][13]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][13]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][13]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][13]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[14]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|__ALT_INV__delay_signals[0][13] ), .combout(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[14]~feeder )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[14]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[14]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[14]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[14]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[14] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[14] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[13]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][13] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[13] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[13]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[13]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[13]~I .lut_mask = "55555555AAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[13]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[13] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[12]~I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][12] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[12] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[12]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[12]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[12]~I .lut_mask = "0F0F0F0FF0F0F0F0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[12] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[11]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][11] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[11] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[11]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[11]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[11]~I .lut_mask = "5555AAAA5555AAAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][10]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][10] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][10]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][10]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][10]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][10]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][10]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[11] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][10]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[11] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][10]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][10]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][10]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][10]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][10]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[10]~I ( .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][10] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[10] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[10]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[10]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[10]~I .lut_mask = "0000FFFFFFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[10] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[9]~I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][9] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[9] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[9]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[9]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[9]~I .lut_mask = "55555555AAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[9] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[8]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][8] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[8] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[8]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[8]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[8]~I .lut_mask = "55555555AAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][7]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][7] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][7]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[8] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[7]~I ( .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][7] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[7] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[7]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[7]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[7]~I .lut_mask = "0000FFFFFFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[7] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[6]~I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[6] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[6]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[6]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[6]~I .lut_mask = "0F0F0F0FF0F0F0F0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][5]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][5]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[6] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[5]~I ( .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[5] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[5]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[5]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[5]~I .lut_mask = "0000FFFFFFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[5] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[4]~I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[4] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[4]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[4]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[4]~I .lut_mask = "0F0F0F0FF0F0F0F0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[4] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[3]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[3] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[3]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[3]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[3]~I .lut_mask = "55555555AAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[3] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[2]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[2] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[2]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[2]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[2]~I .lut_mask = "55555555AAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[2] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[1]~I ( .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[1] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[1]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[1]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[1]~I .lut_mask = "0000FFFFFFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_im0_cma_s[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist22|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[1] )); defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist108|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[0]~I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist108|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[0] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[0]~I .lut_mask = "0F0F0F0FF0F0F0F0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist107|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist107|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist107|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist107|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~205_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist107|__ALT_INV__delay_signals[0][0] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add18~205 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~206 )); defparam \fp_pow_0002:fp_pow_inst|Add18~205_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~205_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~205_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~201_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][1] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~206 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~201 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~202 )); defparam \fp_pow_0002:fp_pow_inst|Add18~201_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~201_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~201_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~197_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][2] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~202 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~197 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~198 )); defparam \fp_pow_0002:fp_pow_inst|Add18~197_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~197_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~197_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~101_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][3] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~198 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~101 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~102 )); defparam \fp_pow_0002:fp_pow_inst|Add18~101_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~101_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~101_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~97_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][4] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~102 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~97 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~98 )); defparam \fp_pow_0002:fp_pow_inst|Add18~97_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~97_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~97_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~93_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~98 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~93 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~94 )); defparam \fp_pow_0002:fp_pow_inst|Add18~93_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~93_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~93_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~89_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][6] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~94 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~89 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~90 )); defparam \fp_pow_0002:fp_pow_inst|Add18~89_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~89_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~89_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~121_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~90 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~121 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~122 )); defparam \fp_pow_0002:fp_pow_inst|Add18~121_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~121_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~121_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~117_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][8] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~122 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~117 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~118 )); defparam \fp_pow_0002:fp_pow_inst|Add18~117_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~117_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~117_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~113_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][9] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~118 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~113 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~114 )); defparam \fp_pow_0002:fp_pow_inst|Add18~113_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~113_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~113_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~109_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][10] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~114 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~109 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~110 )); defparam \fp_pow_0002:fp_pow_inst|Add18~109_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~109_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~109_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~105_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][11] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~110 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~105 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~106 )); defparam \fp_pow_0002:fp_pow_inst|Add18~105_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~105_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~105_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~133_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][12] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~106 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~133 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~134 )); defparam \fp_pow_0002:fp_pow_inst|Add18~133_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~133_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~133_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~153_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][13] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~134 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~153 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~154 )); defparam \fp_pow_0002:fp_pow_inst|Add18~153_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~153_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~153_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~149_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][14] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~154 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~149 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~150 )); defparam \fp_pow_0002:fp_pow_inst|Add18~149_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~149_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~149_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~145_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][15] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~150 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~145 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~146 )); defparam \fp_pow_0002:fp_pow_inst|Add18~145_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~145_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~145_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~141_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][16] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~146 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~141 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~142 )); defparam \fp_pow_0002:fp_pow_inst|Add18~141_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~141_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~141_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~137_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][17] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~142 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~137 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~138 )); defparam \fp_pow_0002:fp_pow_inst|Add18~137_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~137_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~137_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~129_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][18] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~138 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~129 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~130 )); defparam \fp_pow_0002:fp_pow_inst|Add18~129_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~129_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~129_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~193_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][19] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~130 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~193 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~194 )); defparam \fp_pow_0002:fp_pow_inst|Add18~193_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~193_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~193_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~189_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][20] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~194 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~189 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~190 )); defparam \fp_pow_0002:fp_pow_inst|Add18~189_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~189_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~189_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~185_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][21] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~190 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~185 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~186 )); defparam \fp_pow_0002:fp_pow_inst|Add18~185_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~185_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~185_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~181_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][22] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~186 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~181 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~182 )); defparam \fp_pow_0002:fp_pow_inst|Add18~181_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~181_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~181_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~177_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][23] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~182 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~177 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~178 )); defparam \fp_pow_0002:fp_pow_inst|Add18~177_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~177_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~177_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~125_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~178 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~125 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~126 )); defparam \fp_pow_0002:fp_pow_inst|Add18~125_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~125_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~125_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~173_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][25] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~126 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~173 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~174 )); defparam \fp_pow_0002:fp_pow_inst|Add18~173_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~173_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~173_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~169_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][26] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~174 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~169 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~170 )); defparam \fp_pow_0002:fp_pow_inst|Add18~169_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~169_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~169_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~165_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][27] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~170 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~165 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~166 )); defparam \fp_pow_0002:fp_pow_inst|Add18~165_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~165_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~165_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~161_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][28] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~166 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~161 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~162 )); defparam \fp_pow_0002:fp_pow_inst|Add18~161_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~161_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~161_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~157_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][29] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~162 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~157 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~158 )); defparam \fp_pow_0002:fp_pow_inst|Add18~157_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~157_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~157_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~21_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][30] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~158 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~22 )); defparam \fp_pow_0002:fp_pow_inst|Add18~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~21_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~17_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][31] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~18 )); defparam \fp_pow_0002:fp_pow_inst|Add18~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~17_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~13_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][32] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~14 )); defparam \fp_pow_0002:fp_pow_inst|Add18~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~13_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~9_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][33] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~10 )); defparam \fp_pow_0002:fp_pow_inst|Add18~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~9_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~5_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][34] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~6 )); defparam \fp_pow_0002:fp_pow_inst|Add18~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~5_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~1_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][35] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~1 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~2 )); defparam \fp_pow_0002:fp_pow_inst|Add18~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~1_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~45_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][36] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~2 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~46 )); defparam \fp_pow_0002:fp_pow_inst|Add18~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~45_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~41_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][37] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~42 )); defparam \fp_pow_0002:fp_pow_inst|Add18~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~41_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~37_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][38] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~38 )); defparam \fp_pow_0002:fp_pow_inst|Add18~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~37_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~33_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][39] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~34 )); defparam \fp_pow_0002:fp_pow_inst|Add18~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~33_I .lut_mask = "0000FFFF00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[40]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[40] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[40]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][39]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[40] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][39]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][39]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][39]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][39]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][39]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][39]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][39] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][39]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[38]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[38] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[38]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][37]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[38] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][37] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][37]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[39]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[39] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[39]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][38]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[39] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][38]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][38]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][38]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][38]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][38]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][38]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][38]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][38]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][38]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][38]~DUPLICATE_I .created_from = "Q(delay_signals[0][38])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[20]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~33 ), .combout(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[20]~feeder )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[20]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[20]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[20]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[20]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][40] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[20] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[40]~I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[20] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[40] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[40]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[40]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[40]~I .lut_mask = "0FF00FF00FF00FF0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][40]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[40] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][40] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][40]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~29_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][40] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~30 )); defparam \fp_pow_0002:fp_pow_inst|Add18~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~29_I .lut_mask = "0000FFFF00003333"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[41]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[41] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[41]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][40]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[41] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][40] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][40]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[37] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[37]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][36]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[37] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][36] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][36]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[21]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~29 ), .combout(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[21]~feeder )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[21]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[21]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[21]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[21]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][41] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[21] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[41]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[21] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[41] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[41]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[41]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[41]~I .lut_mask = "55555555AAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][41]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[41] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][41] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][41]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~25_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][41] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~26 )); defparam \fp_pow_0002:fp_pow_inst|Add18~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~25_I .lut_mask = "0000FFFF00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[42]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[42] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[42]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][41]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[42] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][41]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][41]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][41]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][41]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][41]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][41]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][41] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][41]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal9~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][39] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][37] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][38]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][40] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][36] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][41] ), .combout(\fp_pow_0002:fp_pow_inst|Equal9~1 )); defparam \fp_pow_0002:fp_pow_inst|Equal9~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~1_I .lut_mask = "8000000000000000"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~149 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[15] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][14]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[15] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][14]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][14]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][14]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][14]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][14]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~153 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[14] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][13]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[14] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][13]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][13]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][13]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][13]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][13]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~137 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[18] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][17]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[18] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][17]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][17]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][17]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][17]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][17]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][17]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][17]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][17]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][17]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][17]~DUPLICATE_I .created_from = "Q(delay_signals[0][17])"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~141 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[17] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~145 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[16] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][15]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[16] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][15]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][15]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][15]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][15]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][15]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal9~9_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][14] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][13] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][17]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][16] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][15] ), .combout(\fp_pow_0002:fp_pow_inst|Equal9~9 )); defparam \fp_pow_0002:fp_pow_inst|Equal9~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~9_I .lut_mask = "8080000000000000"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~185 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[22] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[22] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~193 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[20] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][19]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[20] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][19]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][19]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][19]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][19]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][19]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~177 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[24] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[24]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[24] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][23]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~181 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[23] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[23]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[23] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~189 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[21] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal9~11_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][21] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][19] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][23] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][22] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][20] ), .combout(\fp_pow_0002:fp_pow_inst|Equal9~11 )); defparam \fp_pow_0002:fp_pow_inst|Equal9~11_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~11_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~11_I .lut_mask = "8080000000000000"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~133 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[13] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~125 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[25] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[25] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][24]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~129 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[19] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~169 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[27] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][26]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[27] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][26]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][26]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][26]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][26]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][26]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][26]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~157 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[30] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][29]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[30] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][29]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][29]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][29]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][29]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][29]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][29]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~165 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[28] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][27]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[28] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][27]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][27]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][27]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][27]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][27]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][27]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~161 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[29] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[29]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[29] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][28]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~173 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[26] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[26]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[26] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal9~10_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][26] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][29] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][27] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][28] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][25] ), .combout(\fp_pow_0002:fp_pow_inst|Equal9~10 )); defparam \fp_pow_0002:fp_pow_inst|Equal9~10_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~10_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~10_I .lut_mask = "8080000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal9~12_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~9 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~11 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][12] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][24] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][18] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~10 ), .combout(\fp_pow_0002:fp_pow_inst|Equal9~12 )); defparam \fp_pow_0002:fp_pow_inst|Equal9~12_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~12_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~12_I .lut_mask = "0000000010000000"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~101 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[4] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[4] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~97 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[5] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~121 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[8] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][7]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[8] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][7]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~113 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[10] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~117 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[9] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~109 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[11] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~105 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[12] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal9~8_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][7] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][9] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][8] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][10] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][11] ), .combout(\fp_pow_0002:fp_pow_inst|Equal9~8 )); defparam \fp_pow_0002:fp_pow_inst|Equal9~8_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~8_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~8_I .lut_mask = "8080000000000000"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~93 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[6] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~89 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[7] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal9~13_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~12 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~8 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Equal9~13 )); defparam \fp_pow_0002:fp_pow_inst|Equal9~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~13_I .lut_mask = "0040000000000000"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[31] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][30]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[31] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][30]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][30]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][30]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][30]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][30]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][30]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[34] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[34]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[34] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][33]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[32] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[32]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[32] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][31]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[33] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][32]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[33] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][32]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][32]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][32]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][32]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][32]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][32]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[35] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[35]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[35] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][34]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[36]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[36] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[36]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[36] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][35]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal9~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][30] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][33] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][31] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][32] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][34] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][35] ), .combout(\fp_pow_0002:fp_pow_inst|Equal9~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal9~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~0_I .lut_mask = "8000000000000000"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~105 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[35] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[35]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[55]~I ( .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[35] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[55] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[55]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[55]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[55]~I .lut_mask = "0000FFFFFFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][55]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[55] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][55] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][55]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][55]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][55] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~109 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[34] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[54]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[34] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[54] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[54]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[54]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[54]~I .lut_mask = "5A5A5A5A5A5A5A5A"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][54]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[54] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][54] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][54]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][54]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][54] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~81 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[33] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[53]~I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[33] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[53] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[53]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[53]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[53]~I .lut_mask = "0F0FF0F00F0FF0F0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][53]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[53] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][53] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][53]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][53]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][53] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~85 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[32] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[52]~I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[32] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[52] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[52]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[52]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[52]~I .lut_mask = "0F0F0F0FF0F0F0F0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][52]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[52] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][52] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][52]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][52]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][52] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~89 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][51] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[31] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[51]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[31] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[51] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[51]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[51]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[51]~I .lut_mask = "5A5A5A5A5A5A5A5A"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][51]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[51] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][51] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][51]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][51]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[30]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~93 ), .combout(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[30]~feeder )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[30]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[30]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[30]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[30]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][50] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[30] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[50]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[30] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[50] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[50]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[50]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[50]~I .lut_mask = "5A5A5A5A5A5A5A5A"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][50]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[50] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][50] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][50]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][50]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[29]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~97 ), .combout(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[29]~feeder )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[29]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[29]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[29]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][49]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][49]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][49] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][49]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][49]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[29]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][49] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[29] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[49]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[29] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[49] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[49]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[49]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[49]~I .lut_mask = "5A5A5A5A5A5A5A5A"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][49]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[49] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][49] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][49]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][49]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[28]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~53 ), .combout(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[28]~feeder )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[28]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[28]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[28]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[28]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][48] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[28] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[48]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[28] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[48] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[48]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[48]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[48]~I .lut_mask = "55AA55AA55AA55AA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][48]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[48] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][48] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][48]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][48]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[27]~feeder_I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~61 ), .combout(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[27]~feeder )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[27]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[27]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[27]~feeder_I .lut_mask = "00FF00FF00FF00FF"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[27]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][47] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[27] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[47]~I ( .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[27] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[47] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[47]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[47]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[47]~I .lut_mask = "0000FFFFFFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][47]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[47] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][47] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][47]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][47]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[26]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~65 ), .combout(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[26]~feeder )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[26]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[26]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[26]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[26]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][46] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[26] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[46]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[26] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[46] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[46]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[46]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[46]~I .lut_mask = "5A5A5A5A5A5A5A5A"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][46]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[46] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][46] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][46]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][46]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[25]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~69 ), .combout(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[25]~feeder )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[25]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[25]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[25]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[25]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][45] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[25] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[45]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[25] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[45] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[45]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[45]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[45]~I .lut_mask = "5A5A5A5A5A5A5A5A"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][45]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[45] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][45] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][45]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][45]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[24]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~73 ), .combout(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[24]~feeder )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[24]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[24]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[24]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[24]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][44] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[24] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[44]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[24] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[44] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[44]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[44]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[44]~I .lut_mask = "55AA55AA55AA55AA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][44]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[44] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][44] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][44]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][44]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[23]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~77 ), .combout(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[23]~feeder )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[23]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[23]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[23]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[23]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][43] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[23] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[43]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[23] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[43] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[43]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[43]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[43]~I .lut_mask = "55AA55AA55AA55AA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][43]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[43] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][43] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][43]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][43]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[22]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add15~57 ), .combout(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[22]~feeder )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[22]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[22]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[22]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][42]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p1_of_2_o[43] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][42] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][42]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[22]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist6|delay_signals[0][42] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[22] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[42]~I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[22] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[42] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[42]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[42]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[42]~I .lut_mask = "3C3C3C3C3C3C3C3C"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][42]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[42] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][42] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][42]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~53_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][42] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~54 )); defparam \fp_pow_0002:fp_pow_inst|Add18~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~53_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~73_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][43] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~73 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~74 )); defparam \fp_pow_0002:fp_pow_inst|Add18~73_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~73_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~73_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~69_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][44] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~74 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~69 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~70 )); defparam \fp_pow_0002:fp_pow_inst|Add18~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~69_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~65_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][45] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~70 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~65 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~66 )); defparam \fp_pow_0002:fp_pow_inst|Add18~65_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~65_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~65_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~61_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][46] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~66 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~62 )); defparam \fp_pow_0002:fp_pow_inst|Add18~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~61_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~57_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][47] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~57 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~58 )); defparam \fp_pow_0002:fp_pow_inst|Add18~57_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~57_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~57_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~49_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][48] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~58 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~50 )); defparam \fp_pow_0002:fp_pow_inst|Add18~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~49_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~85_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][49] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~85 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~86 )); defparam \fp_pow_0002:fp_pow_inst|Add18~85_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~85_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~85_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~81_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][50] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~86 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~81 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~82 )); defparam \fp_pow_0002:fp_pow_inst|Add18~81_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~81_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~81_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~77_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|__ALT_INV__delay_signals[0][51] ), .cin(\fp_pow_0002:fp_pow_inst|Add18~82 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add18~78 )); defparam \fp_pow_0002:fp_pow_inst|Add18~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~77_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add18~209_I ( .cin(\fp_pow_0002:fp_pow_inst|Add18~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add18~209 )); defparam \fp_pow_0002:fp_pow_inst|Add18~209_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~209_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add18~209_I .lut_mask = "0000FFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[53]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~209 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[53] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[53]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[53]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add19~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[53] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add19~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add19~6 )); defparam \fp_pow_0002:fp_pow_inst|Add19~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~5_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add19~1_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][1] ), .cin(\fp_pow_0002:fp_pow_inst|Add19~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add19~1 ), .cout(\fp_pow_0002:fp_pow_inst|Add19~2 )); defparam \fp_pow_0002:fp_pow_inst|Add19~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~1_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add19~17_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][2] ), .cin(\fp_pow_0002:fp_pow_inst|Add19~2 ), .sumout(\fp_pow_0002:fp_pow_inst|Add19~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add19~18 )); defparam \fp_pow_0002:fp_pow_inst|Add19~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~17_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add19~13_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][3] ), .cin(\fp_pow_0002:fp_pow_inst|Add19~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add19~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add19~14 )); defparam \fp_pow_0002:fp_pow_inst|Add19~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~13_I .lut_mask = "0000FFFF00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add19~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[4] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[40]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~101 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[40] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[40]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[60]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[40] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[60] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[60]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[60]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[60]~I .lut_mask = "55AA55AA55AA55AA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][60]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[60] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][60] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][60]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][60]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][60] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[39]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~129 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[39] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[39]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[59]~I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[39] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[59] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[59]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[59]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[59]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][59]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[59] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][59] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][59]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][59]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][59] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[38]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~133 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[38] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[38]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[58]~I ( .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[38] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[58] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[58]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[58]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[58]~I .lut_mask = "0000FFFFFFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][58]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[58] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][58] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][58]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][58]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][58] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~137 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[37] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[37]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[57]~I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[37] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[57] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[57]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[57]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[57]~I .lut_mask = "0F0FF0F00F0FF0F0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][57]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[57] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][57] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][57]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][57]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][57] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[36]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~141 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[36] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[36]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[56]~I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[36] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[56] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[56]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[56]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[56]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][56]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[56] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][56] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][56]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][56]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][56] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add19~53_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][4] ), .cin(\fp_pow_0002:fp_pow_inst|Add19~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add19~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add19~54 )); defparam \fp_pow_0002:fp_pow_inst|Add19~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~53_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add19~49_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add19~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add19~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add19~50 )); defparam \fp_pow_0002:fp_pow_inst|Add19~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~49_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add19~45_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][6] ), .cin(\fp_pow_0002:fp_pow_inst|Add19~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add19~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add19~46 )); defparam \fp_pow_0002:fp_pow_inst|Add19~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~45_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add19~41_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add19~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add19~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add19~42 )); defparam \fp_pow_0002:fp_pow_inst|Add19~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~41_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add19~9_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][8] ), .cin(\fp_pow_0002:fp_pow_inst|Add19~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add19~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add19~10 )); defparam \fp_pow_0002:fp_pow_inst|Add19~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~9_I .lut_mask = "0000FFFF00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add19~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[9] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[43]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~117 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[43] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[43]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[43]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[63]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[43] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[63] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[63]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[63]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[63]~I .lut_mask = "55555555AAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][63]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[63] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][63] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][63]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][63]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][63] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[42]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~121 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[42] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[42]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[62]~I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[42] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[62] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[62]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[62]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[62]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][62]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[62] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][62] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][62]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][62]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][62] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[41]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~125 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[41] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[41]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[61]~I ( .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[41] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[61] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[61]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[61]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[61]~I .lut_mask = "0000FFFFFFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][61]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[61] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][61] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][61]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][61]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][61] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add19~37_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][9] ), .cin(\fp_pow_0002:fp_pow_inst|Add19~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add19~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add19~38 )); defparam \fp_pow_0002:fp_pow_inst|Add19~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~37_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add19~33_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][10] ), .cin(\fp_pow_0002:fp_pow_inst|Add19~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add19~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add19~34 )); defparam \fp_pow_0002:fp_pow_inst|Add19~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~33_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add19~29_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][11] ), .cin(\fp_pow_0002:fp_pow_inst|Add19~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add19~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add19~30 )); defparam \fp_pow_0002:fp_pow_inst|Add19~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~29_I .lut_mask = "0000FFFF00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add19~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[12] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add19~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[11] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add19~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[10] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[44]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add15~113 ), .asdata(\fp_pow_0002:fp_pow_inst|postPEMulLog_uid67_fpPowrTest_result_add_0_0_p2_of_2_o[8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[44] )); defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[44]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumLogsumAHighB_uid72_fpPowrTest_o[44]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[64]~I ( .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[44] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .combout(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[64] )); defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[64]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[64]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[64]~I .lut_mask = "0000FFFFFFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][64]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|finalSumOneCompLog_uid76_fpPowrTest_q_i[64] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][64] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][64]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][64]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:finalSumOneCompLog_uid76_fpPowrTest_delay|delay_signals[0][64] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist12|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add19~25_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist12|__ALT_INV__delay_signals[0][12] ), .cin(\fp_pow_0002:fp_pow_inst|Add19~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add19~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add19~26 )); defparam \fp_pow_0002:fp_pow_inst|Add19~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~25_I .lut_mask = "0000FFFF00003333"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add19~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[13] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add19~21_I ( .cin(\fp_pow_0002:fp_pow_inst|Add19~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add19~21 )); defparam \fp_pow_0002:fp_pow_inst|Add19~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add19~21_I .lut_mask = "0000FFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[14]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add19~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[14]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[14]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[14]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[14]~DUPLICATE_I .created_from = "Q(finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[14])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal9~4_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[12] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[11] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[10] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[13] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[14]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Equal9~4 )); defparam \fp_pow_0002:fp_pow_inst|Equal9~4_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~4_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~4_I .lut_mask = "8080000000000000"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add19~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[3] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add19~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[7] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add19~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[8] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[5]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add19~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[5]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[5]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[5]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[5]~DUPLICATE_I .created_from = "Q(finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[5])"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add19~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[6] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal9~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[7] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[8] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[5]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[6] ), .combout(\fp_pow_0002:fp_pow_inst|Equal9~5 )); defparam \fp_pow_0002:fp_pow_inst|Equal9~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~5_I .lut_mask = "A000A00000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal9~6_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[9] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[4] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~4 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[3] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~5 ), .combout(\fp_pow_0002:fp_pow_inst|Equal9~6 )); defparam \fp_pow_0002:fp_pow_inst|Equal9~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~6_I .lut_mask = "0000000008000800"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[45]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~69 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[45] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[45]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[45]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][44]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[45] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][44] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][44]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][44]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[48]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~57 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[48] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[48]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[48]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][47]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[48] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][47] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][47]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][47]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[44]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~73 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[44] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[44]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[44]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][43]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[44] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][43]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][43]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][43]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][43]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][43]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][43]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][43] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][43]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][43]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[46]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~65 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[46] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[46]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[46]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][45]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[46] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][45]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][45]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][45]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][45]~DUPLICATE_I .created_from = "Q(delay_signals[0][45])"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[47]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~61 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[47] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[47]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[47]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][46]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[47] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][46] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][46]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][46]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal9~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][44] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][47] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][43] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][45]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][46] ), .combout(\fp_pow_0002:fp_pow_inst|Equal9~2 )); defparam \fp_pow_0002:fp_pow_inst|Equal9~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~2_I .lut_mask = "8000000080000000"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add19~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[1] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add19~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[2] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[52]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~77 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[52] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[52]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[52]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][51]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[52] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][51] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][51]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][51]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[51]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~81 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[51] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[51]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[51]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][50]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[51] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][50]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][50]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][50]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][50]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][50]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][50]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][50] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][50]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][50]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[50]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~85 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[50] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[50]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[50]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][49]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[50] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][49] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][49]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][49]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal9~3_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[1] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[2] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][51] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][50] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][49] ), .combout(\fp_pow_0002:fp_pow_inst|Equal9~3 )); defparam \fp_pow_0002:fp_pow_inst|Equal9~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~3_I .lut_mask = "8000800000000000"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[43]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[43] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[43]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[43]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][42]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[43] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][42] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][42]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[49]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[49] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[49]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[49]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][48]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[49] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][48]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][48]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][48]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][48]~DUPLICATE_I .created_from = "Q(delay_signals[0][48])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal9~7_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~6 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~2 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~3 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][42] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][48]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Equal9~7 )); defparam \fp_pow_0002:fp_pow_inst|Equal9~7_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~7_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~7_I .lut_mask = "0101000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[20]~21_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[4] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[20]~21 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[20]~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[20]~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[20]~21_I .lut_mask = "0000FFFF0101FFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[20]~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[27]~26_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[11] ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[27]~26 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[27]~26_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[27]~26_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[27]~26_I .lut_mask = "00000101FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[27]~26 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][27]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add19~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[14] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~201 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[2] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[2] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[30]~23_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[14] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[30]~23 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[30]~23_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[30]~23_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[30]~23_I .lut_mask = "0000FFFF0001FFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[30]~23 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][30]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add18~197 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[3] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][2]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][2]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[31]~22_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[31]~22 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[31]~22_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[31]~22_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[31]~22_I .lut_mask = "0000000000010001"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[31]~22 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][31]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|Add18~205 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[1] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][0]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][0]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][0]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][0]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][0]~DUPLICATE_I .created_from = "Q(delay_signals[0][0])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[29]~24_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[13] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[29]~24 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[29]~24_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[29]~24_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[29]~24_I .lut_mask = "0000FFFF0001FFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[29]~24 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[28]~25_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[12] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[28]~25 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[28]~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[28]~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[28]~25_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[28]~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal10~3_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][27] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][30] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][31] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][29] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][28] ), .combout(\fp_pow_0002:fp_pow_inst|Equal10~3 )); defparam \fp_pow_0002:fp_pow_inst|Equal10~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal10~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal10~3_I .lut_mask = "8000000080000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[24]~28_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[8] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[24]~28 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[24]~28_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[24]~28_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[24]~28_I .lut_mask = "00FF00FF01FF01FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][24]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[24]~28 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][24]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][24]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][24]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][24]~DUPLICATE_I .created_from = "Q(delay_signals[0][24])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[22]~30_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[6] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[22]~30 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[22]~30_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[22]~30_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[22]~30_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[22]~30 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[25]~27_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[9] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[25]~27 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[25]~27_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[25]~27_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[25]~27_I .lut_mask = "0F0F0F0F0F0F0F5F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][25]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[25]~27 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][25]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][25]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][25]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][25]~DUPLICATE_I .created_from = "Q(delay_signals[0][25])"; dffeas \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add19~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[5] )); defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[21]~31_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[5] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[21]~31 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[21]~31_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[21]~31_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[21]~31_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[21]~31 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[23]~29_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[7] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[23]~29 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[23]~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[23]~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[23]~29_I .lut_mask = "5555555555575557"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[23]~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal10~4_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][24]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][22] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][25]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][21] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][23] ), .combout(\fp_pow_0002:fp_pow_inst|Equal10~4 )); defparam \fp_pow_0002:fp_pow_inst|Equal10~4_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal10~4_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal10~4_I .lut_mask = "8000000080000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[26]~20_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[10] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[26]~20 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[26]~20_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[26]~20_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[26]~20_I .lut_mask = "00FF00FF00FF05FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[26]~20 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal10~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][20] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal10~3 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal10~4 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][26] ), .combout(\fp_pow_0002:fp_pow_inst|Equal10~5 )); defparam \fp_pow_0002:fp_pow_inst|Equal10~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal10~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal10~5_I .lut_mask = "0202000002020000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[12]~16_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][47] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[12]~16 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[12]~16_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[12]~16_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[12]~16_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[12]~16 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[13]~15_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][48]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[13]~15 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[13]~15_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[13]~15_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[13]~15_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[13]~15 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[9]~19_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][44] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[9]~19 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[9]~19_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[9]~19_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[9]~19_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][9]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[9]~19 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][9]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][9]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][9]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][9]~DUPLICATE_I .created_from = "Q(delay_signals[0][9])"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][45]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[46] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][45] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][45]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][45]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[10]~18_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][45] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[10]~18 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[10]~18_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[10]~18_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[10]~18_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[10]~18 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[11]~17_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][46] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[11]~17 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[11]~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[11]~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[11]~17_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[11]~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal10~2_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][12] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][13] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][9]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][10] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][11] ), .combout(\fp_pow_0002:fp_pow_inst|Equal10~2 )); defparam \fp_pow_0002:fp_pow_inst|Equal10~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal10~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal10~2_I .lut_mask = "C000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[8]~9_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][43] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[8]~9 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[8]~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[8]~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[8]~9_I .lut_mask = "0000FFFF0101FFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[8]~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[14]~8_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][49] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[14]~8 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[14]~8_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[14]~8_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[14]~8_I .lut_mask = "00FF00FF00FF05FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[14]~8 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[15]~14_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][50] ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[15]~14 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[15]~14_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[15]~14_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[15]~14_I .lut_mask = "00010001FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[15]~14 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[16]~13_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][51] ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[16]~13 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[16]~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[16]~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[16]~13_I .lut_mask = "00010001FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][16]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[16]~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][16]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][16]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][16]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][16]~DUPLICATE_I .created_from = "Q(delay_signals[0][16])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[19]~10_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[3] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[19]~10 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[19]~10_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[19]~10_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[19]~10_I .lut_mask = "00FF00FF01FF01FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[19]~10 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[18]~11_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[2] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[18]~11 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[18]~11_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[18]~11_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[18]~11_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[18]~11 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[17]~12_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[1] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[17]~12 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[17]~12_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[17]~12_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[17]~12_I .lut_mask = "00FF00FF01FF01FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[17]~12 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal10~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][15] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][16]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][19] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][18] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][17] ), .combout(\fp_pow_0002:fp_pow_inst|Equal10~1 )); defparam \fp_pow_0002:fp_pow_inst|Equal10~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal10~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal10~1_I .lut_mask = "8000000080000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal10~6_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal10~5 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal10~2 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][8] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][14] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal10~1 ), .combout(\fp_pow_0002:fp_pow_inst|Equal10~6 )); defparam \fp_pow_0002:fp_pow_inst|Equal10~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal10~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal10~6_I .lut_mask = "0000000010001000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[1]~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][36] ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[1]~1 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[1]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[1]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[1]~1_I .lut_mask = "00010001FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[1]~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][40]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[41] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][40]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][40]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][40]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][40]~DUPLICATE_I .created_from = "Q(delay_signals[0][40])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[5]~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][40]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[5]~5 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[5]~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[5]~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[5]~5_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[5]~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[7]~3_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][42] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[7]~3 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[7]~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[7]~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[7]~3_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[7]~3 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[4]~6_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][39] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[4]~6 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[4]~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[4]~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[4]~6_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[4]~6 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][41]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][41]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][41]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][41]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][41]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][41]~DUPLICATE_I .created_from = "Q(delay_signals[0][41])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[6]~4_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][41]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[6]~4 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[6]~4_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[6]~4_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[6]~4_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[6]~4 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[3]~7_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][38]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[3]~7 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[3]~7_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[3]~7_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[3]~7_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[3]~7 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal10~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][7] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][4] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][6] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Equal10~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal10~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal10~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal10~0_I .lut_mask = "8080000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[0]~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][35] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[0]~2 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[0]~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[0]~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[0]~2_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[0]~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[2]~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][37] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[2]~0 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[2]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[2]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[2]~0_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[2]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal10~7_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal10~6 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal10~0 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Equal10~7 )); defparam \fp_pow_0002:fp_pow_inst|Equal10~7_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal10~7_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal10~7_I .lut_mask = "0050000000000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal10~7 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[31]~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][34] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[31]~2 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[31]~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[31]~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[31]~2_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[31]~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][31]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][31] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][31]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][31]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][31]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][31]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][31]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][31]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][31] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[15]~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][31] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][31] ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[15]~2 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[15]~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[15]~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[15]~2_I .lut_mask = "00550055AAFFAAFF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[17]~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][20] ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[17]~0 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[17]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[17]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[17]~0_I .lut_mask = "00010001FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[17]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[1]~0_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][17] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][17] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[1]~0 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[1]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[1]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[1]~0_I .lut_mask = "0F0F0F0F33333333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[27]~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][30] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[27]~1 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[27]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[27]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[27]~1_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[27]~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][27]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][27] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][27]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][27]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][27]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][27]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][27]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][27]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][27] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][27]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][27]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][27]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][27]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][27]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[11]~1_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][27] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][27] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[11]~1 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[11]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[11]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[11]~1_I .lut_mask = "00FF00FF0F0F0F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][29]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][29] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][29]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][29]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][29]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][29]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][29]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[29]~3_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][32] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[29]~3 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[29]~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[29]~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[29]~3_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[29]~3 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][29]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][29] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][29]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][29]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][29]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][29]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][29]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[13]~3_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][29] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][29] ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[13]~3 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[13]~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[13]~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[13]~3_I .lut_mask = "2727272727272727"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[30]~15_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][33] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[30]~15 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[30]~15_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[30]~15_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[30]~15_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[30]~15 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][30]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][30] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][30]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][30] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[14]~14_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][30] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][30] ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[14]~14 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[14]~14_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[14]~14_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[14]~14_I .lut_mask = "05AF05AF05AF05AF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][21]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][21] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][21]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][21]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][21]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][21]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][21]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[21]~13_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][24] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[21]~13 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[21]~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[21]~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[21]~13_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[21]~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[5]~12_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][21] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][21] ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[5]~12 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[5]~12_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[5]~12_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[5]~12_I .lut_mask = "00F000F00FFF0FFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[16]~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][28] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[28]~14_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][31] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[28]~14 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[28]~14_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[28]~14_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[28]~14_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[28]~14 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][28]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][28] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[12]~13_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][28] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][28] ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[12]~13 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[12]~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[12]~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[12]~13_I .lut_mask = "00AA00AA55FF55FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal11~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[14]~14 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[5]~12 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][16] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[12]~13 ), .combout(\fp_pow_0002:fp_pow_inst|Equal11~2 )); defparam \fp_pow_0002:fp_pow_inst|Equal11~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal11~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal11~2_I .lut_mask = "C040C04000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[18]~7_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][21] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[18]~7 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[18]~7_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[18]~7_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[18]~7_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[18]~7 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[2]~7_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][18] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][18] ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[2]~7 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[2]~7_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[2]~7_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[2]~7_I .lut_mask = "11BB11BB11BB11BB"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[24]~28 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][24]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][24] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][24]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][24]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][24]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][24]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][24]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[24]~4_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][27] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[24]~4 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[24]~4_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[24]~4_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[24]~4_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[24]~4 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][24]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][24] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][24]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][24]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][24]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][24]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][24]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[8]~4_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][24] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][24] ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[8]~4 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[8]~4_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[8]~4_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[8]~4_I .lut_mask = "0F000F000FFF0FFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[19]~6_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][22] ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[19]~6 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[19]~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[19]~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[19]~6_I .lut_mask = "00010001FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[19]~6 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[3]~6_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][19] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][19] ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[3]~6 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[3]~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[3]~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[3]~6_I .lut_mask = "0000F0F00F0FFFFF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][20]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][20] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][20]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][20]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][20]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][20]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][20]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[20]~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][23] ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[20]~5 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[20]~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[20]~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[20]~5_I .lut_mask = "00010001FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[20]~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][20]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][20] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][20]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][20]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][20]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][20]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][20]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[4]~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][20] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][20] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[4]~5 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[4]~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[4]~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[4]~5_I .lut_mask = "555555550000FFFF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[26]~10_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][29] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[26]~10 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[26]~10_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[26]~10_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[26]~10_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[26]~10 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][26]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][26] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][26]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][26] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[10]~10_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][26] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][26] ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[10]~10 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[10]~10_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[10]~10_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[10]~10_I .lut_mask = "05050505AFAFAFAF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[23]~8_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][26] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[23]~8 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[23]~8_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[23]~8_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[23]~8_I .lut_mask = "0F0F0F0F0F0F1F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[23]~8 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][23]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][23] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][23]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][23] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[7]~8_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][23] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][23] ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[7]~8 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[7]~8_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[7]~8_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[7]~8_I .lut_mask = "00330033CCFFCCFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[25]~27 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][25] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[25]~11_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][28] ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[25]~11 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[25]~11_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[25]~11_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[25]~11_I .lut_mask = "00010001FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[25]~11 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][25] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[9]~11_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][25] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][25] ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[9]~11 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[9]~11_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[9]~11_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[9]~11_I .lut_mask = "00FF000000FFFFFF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[16]~12_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][19] ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[16]~12 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[16]~12_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[16]~12_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[16]~12_I .lut_mask = "00010001FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[16]~12 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][22] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[22]~9_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][25] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[22]~9 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[22]~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[22]~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[22]~9_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[22]~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][22] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[6]~9_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][22] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][22] ), .combout(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[6]~9 )); defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[6]~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[6]~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[6]~9_I .lut_mask = "0A0A0A0A5F5F5F5F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal11~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[10]~10 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[7]~8 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[9]~11 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[0][16] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[6]~9 ), .combout(\fp_pow_0002:fp_pow_inst|Equal11~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal11~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal11~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal11~0_I .lut_mask = "C000800000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal11~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[2]~7 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[8]~4 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[3]~6 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[4]~5 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal11~0 ), .combout(\fp_pow_0002:fp_pow_inst|Equal11~1 )); defparam \fp_pow_0002:fp_pow_inst|Equal11~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal11~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal11~1_I .lut_mask = "0000000080008000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal11~3_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[15]~2 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[1]~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[11]~1 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__rVStage_uid299_countZLog_uid78_fpPowrTest_b[13]~3 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal11~2 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal11~1 ), .combout(\fp_pow_0002:fp_pow_inst|Equal11~3 )); defparam \fp_pow_0002:fp_pow_inst|Equal11~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal11~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal11~3_I .lut_mask = "0000000000008000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid300_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal11~3 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid300_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid300_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid300_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[15]~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][7]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][7] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][7]~feeder_I .lut_mask = "00000000FFFFFFFF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[7]~26_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][10] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[7]~26 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[7]~26_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[7]~26_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[7]~26_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[7]~26 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][7]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[7]~8 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][15]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][15] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][15]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][15]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][15]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][15]~feeder_I .lut_mask = "00000000FFFFFFFF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[15]~20_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][18] ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[15]~20 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[15]~20_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[15]~20_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[15]~20_I .lut_mask = "00010001FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[15]~20 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][15]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][10]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][10] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][10]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][10]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][10]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][10]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][10]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][10]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][10] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][10]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][10]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][10]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][10]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[10]~17_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][13] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[10]~17 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[10]~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[10]~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[10]~17_I .lut_mask = "00FF00FF01FF01FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[10]~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][10]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][14]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|__ALT_INV__delay_signals[0][14] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][14]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][14]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][14]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][14]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][14]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][14]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][14] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][14]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][14]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][14]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][14]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][17]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[14]~21_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][17] ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[14]~21 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[14]~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[14]~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[14]~21_I .lut_mask = "00000101FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[14]~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][14] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][14]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][14] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][12]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][12] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][12]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][12]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][12]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][12]~feeder_I .lut_mask = "5555555555555555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[12]~23_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][15] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[12]~23 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[12]~23_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[12]~23_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[12]~23_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[12]~23 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][12]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][12] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][12]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][12]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][12]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][12]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][12]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][12]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][13]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][13] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][13]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][13]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][13]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][13]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[13]~22_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][16] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[13]~22 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[13]~22_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[13]~22_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[13]~22_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[13]~22 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][13]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][13]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][13]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][13]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][13]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][13]~DUPLICATE_I .created_from = "Q(delay_signals[0][13])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal12~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][14] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][12] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid300_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][15] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][13]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Equal12~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal12~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal12~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal12~0_I .lut_mask = "0800080000000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][8]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][8] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][8]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][8]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][8]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][8]~feeder_I .lut_mask = "5555555555555555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[8]~19_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][11] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[8]~19 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[8]~19_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[8]~19_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[8]~19_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[8]~19 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][8]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[9]~19 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][9]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][9] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][9]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][9]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][9]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][9]~feeder_I .lut_mask = "00000000FFFFFFFF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[9]~18_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][12] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[9]~18 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[9]~18_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[9]~18_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[9]~18_I .lut_mask = "0000FFFF0005FFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[9]~18 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][9]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[11]~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[8]~4 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[10]~10 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[9]~11 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[14]~14 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[13]~3 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[12]~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal12~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][14] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][15] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid300_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][13] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][12] ), .combout(\fp_pow_0002:fp_pow_inst|Equal12~1 )); defparam \fp_pow_0002:fp_pow_inst|Equal12~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal12~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal12~1_I .lut_mask = "8000800000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal12~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][11] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][8] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][10] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][9] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal12~1 ), .combout(\fp_pow_0002:fp_pow_inst|Equal12~2 )); defparam \fp_pow_0002:fp_pow_inst|Equal12~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal12~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal12~2_I .lut_mask = "0000000080008000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][11]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][11] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][11]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][11]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][11]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][11]~feeder_I .lut_mask = "00000000FFFFFFFF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[11]~16_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][14] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[11]~16 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[11]~16_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[11]~16_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[11]~16_I .lut_mask = "3333333333373337"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[11]~16 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][11]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal12~3_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][10] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal12~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][8] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][9] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal12~2 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][11] ), .combout(\fp_pow_0002:fp_pow_inst|Equal12~3 )); defparam \fp_pow_0002:fp_pow_inst|Equal12~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal12~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal12~3_I .lut_mask = "2000FFFF0000FFFF"; cyclonev_lcell_comb \rtl~140_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid300_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][15] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][7] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][7] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][15] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal12~3 ), .combout(\rtl~140 )); defparam \rtl~140_I .shared_arith = "off"; defparam \rtl~140_I .extended_lut = "off"; defparam \rtl~140_I .lut_mask = "2222777705AF05AF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~140 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[6]~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][6]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][6]~feeder_I .lut_mask = "5555555555555555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[6]~27_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][9] ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[6]~27 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[6]~27_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[6]~27_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[6]~27_I .lut_mask = "00010001FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[6]~27 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][6]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][6]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][6]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~141_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal12~3 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][14] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid300_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][14] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][6] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][6] ), .combout(\rtl~141 )); defparam \rtl~141_I .shared_arith = "off"; defparam \rtl~141_I .extended_lut = "off"; defparam \rtl~141_I .lut_mask = "02A252F207A757F7"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~141 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[4]~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][4]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[4]~6 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][4]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][4]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][4]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][4]~DUPLICATE_I .created_from = "Q(delay_signals[0][4])"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][4]~DUPLICATE ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][4]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][4]~feeder_I .lut_mask = "3333333333333333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[4]~25_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][7] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[4]~25 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[4]~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[4]~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[4]~25_I .lut_mask = "00FF00FF01FF01FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[4]~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][4]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|__ALT_INV__delay_signals[1][4] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][4]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][4]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][4]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~143_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid300_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][12] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][12] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal12~3 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][4] ), .combout(\rtl~143 )); defparam \rtl~143_I .shared_arith = "off"; defparam \rtl~143_I .extended_lut = "off"; defparam \rtl~143_I .lut_mask = "11BB0A0A11BB5F5F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~143 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][13]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][5]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][5]~feeder_I .lut_mask = "00000000FFFFFFFF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[5]~24_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][8] ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[5]~24 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[5]~24_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[5]~24_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[5]~24_I .lut_mask = "00010001FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[5]~24 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][5]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[5]~12 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~142_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid300_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal12~3 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][13] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][13] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][5] ), .combout(\rtl~142 )); defparam \rtl~142_I .shared_arith = "off"; defparam \rtl~142_I .extended_lut = "off"; defparam \rtl~142_I .lut_mask = "084C195D2A6E3B7F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~142 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist55|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal13~0_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist55|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist55|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist55|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist55|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Equal13~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal13~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal13~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal13~0_I .lut_mask = "C000C00000000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][2]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][2]~feeder_I .lut_mask = "5555555555555555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[2]~29_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[2]~29 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[2]~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[2]~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[2]~29_I .lut_mask = "00FF00FF01FF01FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[2]~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][2]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[2]~7 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~145_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal12~3 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid300_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][10] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][10] ), .combout(\rtl~145 )); defparam \rtl~145_I .shared_arith = "off"; defparam \rtl~145_I .extended_lut = "off"; defparam \rtl~145_I .lut_mask = "08194C5D2A3B6E7F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~145 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[3]~6 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][3]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid293_countZLog_uid78_fpPowrTest_b[3]~7 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][3]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][3]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][3]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][3]~DUPLICATE_I .created_from = "Q(delay_signals[0][3])"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][3]~DUPLICATE ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][3]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][3]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[3]~28_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][6] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[3]~28 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[3]~28_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[3]~28_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[3]~28_I .lut_mask = "0F0F0F0F0F1F0F1F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[3]~28 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][3]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~144_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][11] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal12~3 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid300_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][11] ), .combout(\rtl~144 )); defparam \rtl~144_I .shared_arith = "off"; defparam \rtl~144_I .extended_lut = "off"; defparam \rtl~144_I .lut_mask = "0033550FFF33550F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][3]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\rtl~144 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][3]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][3]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][3]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][3]~DUPLICATE_I .created_from = "Q(delay_signals[0][3])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal14~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal13~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist53|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist55|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist55|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist53|__ALT_INV__delay_signals[0][3]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Equal14~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal14~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal14~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal14~0_I .lut_mask = "FA000000AA000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist52|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal14~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist52|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist52|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist52|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][1]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist52|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][1]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][1]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][1]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][1]~DUPLICATE_I .created_from = "Q(delay_signals[0][1])"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist54|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|Equal13~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist54|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist54|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist54|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][2]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist54|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][2]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][2]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][2]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][2]~DUPLICATE_I .created_from = "Q(delay_signals[0][2])"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist56|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|Equal12~3 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist56|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist56|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist56|delay_signals[0][0]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|delay_signals[0][0]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist56|delay_signals[0][0]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist56|delay_signals[0][0]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist56|delay_signals[0][0]~DUPLICATE_I .created_from = "Q(delay_signals[0][0])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist58|delay_signals[1][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid300_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|delay_signals[1][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist58|delay_signals[1][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist58|delay_signals[1][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist58|delay_signals[1][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist58|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|delay_signals[1][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist58|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist58|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist58|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist58|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist58|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add20~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Add20~0 )); defparam \fp_pow_0002:fp_pow_inst|Add20~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add20~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add20~0_I .lut_mask = "F800F800F800F800"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist61|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist61|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist61|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist61|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist61|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist61|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist61|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist61|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist61|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal9~14_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .combout(\fp_pow_0002:fp_pow_inst|Equal9~14 )); defparam \fp_pow_0002:fp_pow_inst|Equal9~14_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~14_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal9~14_I .lut_mask = "0000000000001111"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[4][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal9~14 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[4][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[4][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[4][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[3][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[4][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[3][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[3][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[3][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[3][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add20~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add20~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Add20~1 )); defparam \fp_pow_0002:fp_pow_inst|Add20~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add20~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add20~1_I .lut_mask = "5050505000000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][41]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add20~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][41] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][41]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add20~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add20~0 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Add20~2 )); defparam \fp_pow_0002:fp_pow_inst|Add20~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add20~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add20~2_I .lut_mask = "AAFFAAFF55005500"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][40]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add20~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][40] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][40]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add20~3_I ( .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add20~0 ), .combout(\fp_pow_0002:fp_pow_inst|Add20~3 )); defparam \fp_pow_0002:fp_pow_inst|Add20~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add20~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add20~3_I .lut_mask = "FFFF00000000FFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][39]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add20~3 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][39] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][39]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add20~4_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Add20~4 )); defparam \fp_pow_0002:fp_pow_inst|Add20~4_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add20~4_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add20~4_I .lut_mask = "0F780F780F780F78"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][38]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add20~4 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][38] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][38]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add20~5_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Add20~5 )); defparam \fp_pow_0002:fp_pow_inst|Add20~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add20~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add20~5_I .lut_mask = "C0C03F3FC0C03F3F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add20~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][37] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][37]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add20~6_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Add20~6 )); defparam \fp_pow_0002:fp_pow_inst|Add20~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add20~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add20~6_I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][36]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add20~6 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][36] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][36]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][1]~DUPLICATE ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][35]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~144 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rVStage_uid299_countZLog_uid78_fpPowrTest_b[1]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist59|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist62|delay_signals[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist63|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][1]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist63|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][1]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[1]~30_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~7 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~1 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~13 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal9~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[1]~30 )); defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[1]~30_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[1]~30_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[1]~30_I .lut_mask = "00010001FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|vStage_uid295_countZLog_uid78_fpPowrTest_b[1]~30 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[1][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][1]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist60|delay_signals[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid294_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist57|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~234_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal12~3 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][9] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist59|__ALT_INV__delay_signals[0][9] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid300_countZLog_uid78_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist57|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~234 )); defparam \rtl~234_I .shared_arith = "off"; defparam \rtl~234_I .extended_lut = "off"; defparam \rtl~234_I .lut_mask = "11DD0C0C11DD3F3F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~234 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist53|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~148_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal13~0 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist53|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist53|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Equal14~0 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist55|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist55|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~148 )); defparam \rtl~148_I .shared_arith = "off"; defparam \rtl~148_I .extended_lut = "off"; defparam \rtl~148_I .lut_mask = "EEFA44FAEE504450"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid324_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~148 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid324_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid324_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid324_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:vCount_uid324_countZLog_uid78_fpPowrTest_delay|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][34]~3_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][34]~3 )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][34]~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][34]~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][34]~3_I .lut_mask = "FFFFFFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][34]~3 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][34]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist56|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist56|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist56|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~1 )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~1_I .lut_mask = "A0F0A0F0A0F0A0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0]~feeder_I ( .combout(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0]~feeder_I .lut_mask = "FFFFFFFFFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|redist9_cmpReg_q[0] ), .q(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0]~0_I ( .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist9_replace_rdcnt_i[0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0]~0_I .lut_mask = "FFFF0000FFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE_I .created_from = "Q(redist9_replace_rdreg_q[1])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0]~0_I ( .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist9_replace_rdcnt_i[0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "FFFF0000FFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[1] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2117,portadatain_unconnected_wire_2118,portadatain_unconnected_wire_2119,portadatain_unconnected_wire_2120,portadatain_unconnected_wire_2121,portadatain_unconnected_wire_2122,portadatain_unconnected_wire_2123, portadatain_unconnected_wire_2124,portadatain_unconnected_wire_2125,portadatain_unconnected_wire_2126,portadatain_unconnected_wire_2127,portadatain_unconnected_wire_2128,portadatain_unconnected_wire_2129,portadatain_unconnected_wire_2130, portadatain_unconnected_wire_2131,portadatain_unconnected_wire_2132,portadatain_unconnected_wire_2133,portadatain_unconnected_wire_2134,portadatain_unconnected_wire_2135,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][10] }), .portaaddr({portaaddr_unconnected_wire_2136,portaaddr_unconnected_wire_2137,portaaddr_unconnected_wire_2138,portaaddr_unconnected_wire_2139,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2140,portbaddr_unconnected_wire_2141,portbaddr_unconnected_wire_2142,portbaddr_unconnected_wire_2143, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[10] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10 .first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama10 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2144,portadatain_unconnected_wire_2145,portadatain_unconnected_wire_2146,portadatain_unconnected_wire_2147,portadatain_unconnected_wire_2148,portadatain_unconnected_wire_2149,portadatain_unconnected_wire_2150, portadatain_unconnected_wire_2151,portadatain_unconnected_wire_2152,portadatain_unconnected_wire_2153,portadatain_unconnected_wire_2154,portadatain_unconnected_wire_2155,portadatain_unconnected_wire_2156,portadatain_unconnected_wire_2157, portadatain_unconnected_wire_2158,portadatain_unconnected_wire_2159,portadatain_unconnected_wire_2160,portadatain_unconnected_wire_2161,portadatain_unconnected_wire_2162,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][42] }), .portaaddr({portaaddr_unconnected_wire_2163,portaaddr_unconnected_wire_2164,portaaddr_unconnected_wire_2165,portaaddr_unconnected_wire_2166,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2167,portbaddr_unconnected_wire_2168,portbaddr_unconnected_wire_2169,portbaddr_unconnected_wire_2170, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[42] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42 .first_bit_number = 42; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama42 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][42]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[42] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][42] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][42]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux34~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][10] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][42] ), .combout(\fp_pow_0002:fp_pow_inst|Mux34~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux34~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux34~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux34~0_I .lut_mask = "028A028A028A028A"; cyclonev_lcell_comb \rtl~288_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .combout(\rtl~288 )); defparam \rtl~288_I .shared_arith = "off"; defparam \rtl~288_I .extended_lut = "off"; defparam \rtl~288_I .lut_mask = "AAAAAAAA00000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~0_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~288 ), .combout(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~0 )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~0_I .lut_mask = "FF00FF0000000000"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2171,portadatain_unconnected_wire_2172,portadatain_unconnected_wire_2173,portadatain_unconnected_wire_2174,portadatain_unconnected_wire_2175,portadatain_unconnected_wire_2176,portadatain_unconnected_wire_2177, portadatain_unconnected_wire_2178,portadatain_unconnected_wire_2179,portadatain_unconnected_wire_2180,portadatain_unconnected_wire_2181,portadatain_unconnected_wire_2182,portadatain_unconnected_wire_2183,portadatain_unconnected_wire_2184, portadatain_unconnected_wire_2185,portadatain_unconnected_wire_2186,portadatain_unconnected_wire_2187,portadatain_unconnected_wire_2188,portadatain_unconnected_wire_2189,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][26] }), .portaaddr({portaaddr_unconnected_wire_2190,portaaddr_unconnected_wire_2191,portaaddr_unconnected_wire_2192,portaaddr_unconnected_wire_2193,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2194,portbaddr_unconnected_wire_2195,portbaddr_unconnected_wire_2196,portbaddr_unconnected_wire_2197, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[26] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26 .first_bit_number = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama26 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[26] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][26]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2198,portadatain_unconnected_wire_2199,portadatain_unconnected_wire_2200,portadatain_unconnected_wire_2201,portadatain_unconnected_wire_2202,portadatain_unconnected_wire_2203,portadatain_unconnected_wire_2204, portadatain_unconnected_wire_2205,portadatain_unconnected_wire_2206,portadatain_unconnected_wire_2207,portadatain_unconnected_wire_2208,portadatain_unconnected_wire_2209,portadatain_unconnected_wire_2210,portadatain_unconnected_wire_2211, portadatain_unconnected_wire_2212,portadatain_unconnected_wire_2213,portadatain_unconnected_wire_2214,portadatain_unconnected_wire_2215,portadatain_unconnected_wire_2216,\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[7] }), .portaaddr({portaaddr_unconnected_wire_2217,portaaddr_unconnected_wire_2218,portaaddr_unconnected_wire_2219,portaaddr_unconnected_wire_2220,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2221,portbaddr_unconnected_wire_2222,portbaddr_unconnected_wire_2223,portbaddr_unconnected_wire_2224, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[58] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58 .first_bit_number = 58; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama58 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][58]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[58] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][58] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][58]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][58]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~295_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux34~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~0 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][26] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][58] ), .combout(\rtl~295 )); defparam \rtl~295_I .shared_arith = "off"; defparam \rtl~295_I .extended_lut = "off"; defparam \rtl~295_I .lut_mask = "202A707A202A707A"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2225,portadatain_unconnected_wire_2226,portadatain_unconnected_wire_2227,portadatain_unconnected_wire_2228,portadatain_unconnected_wire_2229,portadatain_unconnected_wire_2230,portadatain_unconnected_wire_2231, portadatain_unconnected_wire_2232,portadatain_unconnected_wire_2233,portadatain_unconnected_wire_2234,portadatain_unconnected_wire_2235,portadatain_unconnected_wire_2236,portadatain_unconnected_wire_2237,portadatain_unconnected_wire_2238, portadatain_unconnected_wire_2239,portadatain_unconnected_wire_2240,portadatain_unconnected_wire_2241,portadatain_unconnected_wire_2242,portadatain_unconnected_wire_2243,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][18] }), .portaaddr({portaaddr_unconnected_wire_2244,portaaddr_unconnected_wire_2245,portaaddr_unconnected_wire_2246,portaaddr_unconnected_wire_2247,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2248,portbaddr_unconnected_wire_2249,portbaddr_unconnected_wire_2250,portbaddr_unconnected_wire_2251, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[18] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18 .first_bit_number = 18; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama18 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][18]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][18]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][18]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][18]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][18]~DUPLICATE_I .created_from = "Q(delay_signals[0][18])"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2252,portadatain_unconnected_wire_2253,portadatain_unconnected_wire_2254,portadatain_unconnected_wire_2255,portadatain_unconnected_wire_2256,portadatain_unconnected_wire_2257,portadatain_unconnected_wire_2258, portadatain_unconnected_wire_2259,portadatain_unconnected_wire_2260,portadatain_unconnected_wire_2261,portadatain_unconnected_wire_2262,portadatain_unconnected_wire_2263,portadatain_unconnected_wire_2264,portadatain_unconnected_wire_2265, portadatain_unconnected_wire_2266,portadatain_unconnected_wire_2267,portadatain_unconnected_wire_2268,portadatain_unconnected_wire_2269,portadatain_unconnected_wire_2270,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][34] }), .portaaddr({portaaddr_unconnected_wire_2271,portaaddr_unconnected_wire_2272,portaaddr_unconnected_wire_2273,portaaddr_unconnected_wire_2274,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2275,portbaddr_unconnected_wire_2276,portbaddr_unconnected_wire_2277,portbaddr_unconnected_wire_2278, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[34] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34 .first_bit_number = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama34 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[34] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][34]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2279,portadatain_unconnected_wire_2280,portadatain_unconnected_wire_2281,portadatain_unconnected_wire_2282,portadatain_unconnected_wire_2283,portadatain_unconnected_wire_2284,portadatain_unconnected_wire_2285, portadatain_unconnected_wire_2286,portadatain_unconnected_wire_2287,portadatain_unconnected_wire_2288,portadatain_unconnected_wire_2289,portadatain_unconnected_wire_2290,portadatain_unconnected_wire_2291,portadatain_unconnected_wire_2292, portadatain_unconnected_wire_2293,portadatain_unconnected_wire_2294,portadatain_unconnected_wire_2295,portadatain_unconnected_wire_2296,portadatain_unconnected_wire_2297,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][2] }), .portaaddr({portaaddr_unconnected_wire_2298,portaaddr_unconnected_wire_2299,portaaddr_unconnected_wire_2300,portaaddr_unconnected_wire_2301,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2302,portbaddr_unconnected_wire_2303,portbaddr_unconnected_wire_2304,portbaddr_unconnected_wire_2305, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[2] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2 .first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama2 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2306,portadatain_unconnected_wire_2307,portadatain_unconnected_wire_2308,portadatain_unconnected_wire_2309,portadatain_unconnected_wire_2310,portadatain_unconnected_wire_2311,portadatain_unconnected_wire_2312, portadatain_unconnected_wire_2313,portadatain_unconnected_wire_2314,portadatain_unconnected_wire_2315,portadatain_unconnected_wire_2316,portadatain_unconnected_wire_2317,portadatain_unconnected_wire_2318,portadatain_unconnected_wire_2319, portadatain_unconnected_wire_2320,portadatain_unconnected_wire_2321,portadatain_unconnected_wire_2322,portadatain_unconnected_wire_2323,portadatain_unconnected_wire_2324,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][50] }), .portaaddr({portaaddr_unconnected_wire_2325,portaaddr_unconnected_wire_2326,portaaddr_unconnected_wire_2327,portaaddr_unconnected_wire_2328,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2329,portbaddr_unconnected_wire_2330,portbaddr_unconnected_wire_2331,portbaddr_unconnected_wire_2332, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[50] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50 .first_bit_number = 50; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama50 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][50]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[50] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][50] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][50]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][50]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~294_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][18]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][34] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][50] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .combout(\rtl~294 )); defparam \rtl~294_I .shared_arith = "off"; defparam \rtl~294_I .extended_lut = "off"; defparam \rtl~294_I .lut_mask = "00FF333355550F0F"; cyclonev_lcell_comb \rtl~296_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0] ), .datac(\__ALT_INV__rtl~295 ), .datad(\__ALT_INV__rtl~294 ), .combout(\rtl~296 )); defparam \rtl~296_I .shared_arith = "off"; defparam \rtl~296_I .extended_lut = "off"; defparam \rtl~296_I .lut_mask = "0C2E0C2E0C2E0C2E"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[58]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~296 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[58] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[58]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[58]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2333,portadatain_unconnected_wire_2334,portadatain_unconnected_wire_2335,portadatain_unconnected_wire_2336,portadatain_unconnected_wire_2337,portadatain_unconnected_wire_2338,portadatain_unconnected_wire_2339, portadatain_unconnected_wire_2340,portadatain_unconnected_wire_2341,portadatain_unconnected_wire_2342,portadatain_unconnected_wire_2343,portadatain_unconnected_wire_2344,portadatain_unconnected_wire_2345,portadatain_unconnected_wire_2346, portadatain_unconnected_wire_2347,portadatain_unconnected_wire_2348,portadatain_unconnected_wire_2349,portadatain_unconnected_wire_2350,portadatain_unconnected_wire_2351,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][24] }), .portaaddr({portaaddr_unconnected_wire_2352,portaaddr_unconnected_wire_2353,portaaddr_unconnected_wire_2354,portaaddr_unconnected_wire_2355,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2356,portbaddr_unconnected_wire_2357,portbaddr_unconnected_wire_2358,portbaddr_unconnected_wire_2359, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[24] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24 .first_bit_number = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama24 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[24] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2360,portadatain_unconnected_wire_2361,portadatain_unconnected_wire_2362,portadatain_unconnected_wire_2363,portadatain_unconnected_wire_2364,portadatain_unconnected_wire_2365,portadatain_unconnected_wire_2366, portadatain_unconnected_wire_2367,portadatain_unconnected_wire_2368,portadatain_unconnected_wire_2369,portadatain_unconnected_wire_2370,portadatain_unconnected_wire_2371,portadatain_unconnected_wire_2372,portadatain_unconnected_wire_2373, portadatain_unconnected_wire_2374,portadatain_unconnected_wire_2375,portadatain_unconnected_wire_2376,portadatain_unconnected_wire_2377,portadatain_unconnected_wire_2378,\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[5]~DUPLICATE }), .portaaddr({portaaddr_unconnected_wire_2379,portaaddr_unconnected_wire_2380,portaaddr_unconnected_wire_2381,portaaddr_unconnected_wire_2382,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2383,portbaddr_unconnected_wire_2384,portbaddr_unconnected_wire_2385,portbaddr_unconnected_wire_2386, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[56] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56 .first_bit_number = 56; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama56 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][56]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[56] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][56] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][56]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][56]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux20~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][24] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][56] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Mux20~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux20~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux20~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux20~0_I .lut_mask = "00AA00AA0A0A0A0A"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][48]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[49] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][48] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][48]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][48]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2387,portadatain_unconnected_wire_2388,portadatain_unconnected_wire_2389,portadatain_unconnected_wire_2390,portadatain_unconnected_wire_2391,portadatain_unconnected_wire_2392,portadatain_unconnected_wire_2393, portadatain_unconnected_wire_2394,portadatain_unconnected_wire_2395,portadatain_unconnected_wire_2396,portadatain_unconnected_wire_2397,portadatain_unconnected_wire_2398,portadatain_unconnected_wire_2399,portadatain_unconnected_wire_2400, portadatain_unconnected_wire_2401,portadatain_unconnected_wire_2402,portadatain_unconnected_wire_2403,portadatain_unconnected_wire_2404,portadatain_unconnected_wire_2405,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][48] }), .portaaddr({portaaddr_unconnected_wire_2406,portaaddr_unconnected_wire_2407,portaaddr_unconnected_wire_2408,portaaddr_unconnected_wire_2409,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2410,portbaddr_unconnected_wire_2411,portbaddr_unconnected_wire_2412,portbaddr_unconnected_wire_2413, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[48] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48 .first_bit_number = 48; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama48 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][48]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[48] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][48] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][48]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][48]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2414,portadatain_unconnected_wire_2415,portadatain_unconnected_wire_2416,portadatain_unconnected_wire_2417,portadatain_unconnected_wire_2418,portadatain_unconnected_wire_2419,portadatain_unconnected_wire_2420, portadatain_unconnected_wire_2421,portadatain_unconnected_wire_2422,portadatain_unconnected_wire_2423,portadatain_unconnected_wire_2424,portadatain_unconnected_wire_2425,portadatain_unconnected_wire_2426,portadatain_unconnected_wire_2427, portadatain_unconnected_wire_2428,portadatain_unconnected_wire_2429,portadatain_unconnected_wire_2430,portadatain_unconnected_wire_2431,portadatain_unconnected_wire_2432,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][16] }), .portaaddr({portaaddr_unconnected_wire_2433,portaaddr_unconnected_wire_2434,portaaddr_unconnected_wire_2435,portaaddr_unconnected_wire_2436,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2437,portbaddr_unconnected_wire_2438,portbaddr_unconnected_wire_2439,portbaddr_unconnected_wire_2440, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[16] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16 .first_bit_number = 16; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama16 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux28~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][48] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][16] ), .combout(\fp_pow_0002:fp_pow_inst|Mux28~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux28~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux28~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux28~0_I .lut_mask = "0088008822AA22AA"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2441,portadatain_unconnected_wire_2442,portadatain_unconnected_wire_2443,portadatain_unconnected_wire_2444,portadatain_unconnected_wire_2445,portadatain_unconnected_wire_2446,portadatain_unconnected_wire_2447, portadatain_unconnected_wire_2448,portadatain_unconnected_wire_2449,portadatain_unconnected_wire_2450,portadatain_unconnected_wire_2451,portadatain_unconnected_wire_2452,portadatain_unconnected_wire_2453,portadatain_unconnected_wire_2454, portadatain_unconnected_wire_2455,portadatain_unconnected_wire_2456,portadatain_unconnected_wire_2457,portadatain_unconnected_wire_2458,portadatain_unconnected_wire_2459,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][40] }), .portaaddr({portaaddr_unconnected_wire_2460,portaaddr_unconnected_wire_2461,portaaddr_unconnected_wire_2462,portaaddr_unconnected_wire_2463,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2464,portbaddr_unconnected_wire_2465,portbaddr_unconnected_wire_2466,portbaddr_unconnected_wire_2467, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[40] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40 .first_bit_number = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama40 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][40]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[40] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][40] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][40]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2468,portadatain_unconnected_wire_2469,portadatain_unconnected_wire_2470,portadatain_unconnected_wire_2471,portadatain_unconnected_wire_2472,portadatain_unconnected_wire_2473,portadatain_unconnected_wire_2474, portadatain_unconnected_wire_2475,portadatain_unconnected_wire_2476,portadatain_unconnected_wire_2477,portadatain_unconnected_wire_2478,portadatain_unconnected_wire_2479,portadatain_unconnected_wire_2480,portadatain_unconnected_wire_2481, portadatain_unconnected_wire_2482,portadatain_unconnected_wire_2483,portadatain_unconnected_wire_2484,portadatain_unconnected_wire_2485,portadatain_unconnected_wire_2486,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][8] }), .portaaddr({portaaddr_unconnected_wire_2487,portaaddr_unconnected_wire_2488,portaaddr_unconnected_wire_2489,portaaddr_unconnected_wire_2490,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2491,portbaddr_unconnected_wire_2492,portbaddr_unconnected_wire_2493,portbaddr_unconnected_wire_2494, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[8] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8 .first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama8 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux36~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][40] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][8] ), .combout(\fp_pow_0002:fp_pow_inst|Mux36~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux36~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux36~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux36~0_I .lut_mask = "0088008822AA22AA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p1_of_2_o[1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[4][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[4][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[4][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[4][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[3][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[4][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[3][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[3][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[3][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[3][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2495,portadatain_unconnected_wire_2496,portadatain_unconnected_wire_2497,portadatain_unconnected_wire_2498,portadatain_unconnected_wire_2499,portadatain_unconnected_wire_2500,portadatain_unconnected_wire_2501, portadatain_unconnected_wire_2502,portadatain_unconnected_wire_2503,portadatain_unconnected_wire_2504,portadatain_unconnected_wire_2505,portadatain_unconnected_wire_2506,portadatain_unconnected_wire_2507,portadatain_unconnected_wire_2508, portadatain_unconnected_wire_2509,portadatain_unconnected_wire_2510,portadatain_unconnected_wire_2511,portadatain_unconnected_wire_2512,portadatain_unconnected_wire_2513,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][32] }), .portaaddr({portaaddr_unconnected_wire_2514,portaaddr_unconnected_wire_2515,portaaddr_unconnected_wire_2516,portaaddr_unconnected_wire_2517,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2518,portbaddr_unconnected_wire_2519,portbaddr_unconnected_wire_2520,portbaddr_unconnected_wire_2521, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[32] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32 .first_bit_number = 32; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama32 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[32] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][32]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2522,portadatain_unconnected_wire_2523,portadatain_unconnected_wire_2524,portadatain_unconnected_wire_2525,portadatain_unconnected_wire_2526,portadatain_unconnected_wire_2527,portadatain_unconnected_wire_2528, portadatain_unconnected_wire_2529,portadatain_unconnected_wire_2530,portadatain_unconnected_wire_2531,portadatain_unconnected_wire_2532,portadatain_unconnected_wire_2533,portadatain_unconnected_wire_2534,portadatain_unconnected_wire_2535, portadatain_unconnected_wire_2536,portadatain_unconnected_wire_2537,portadatain_unconnected_wire_2538,portadatain_unconnected_wire_2539,portadatain_unconnected_wire_2540,\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[13] }), .portaaddr({portaaddr_unconnected_wire_2541,portaaddr_unconnected_wire_2542,portaaddr_unconnected_wire_2543,portaaddr_unconnected_wire_2544,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2545,portbaddr_unconnected_wire_2546,portbaddr_unconnected_wire_2547,portbaddr_unconnected_wire_2548, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[64] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64 .first_bit_number = 64; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama64 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][64]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[64] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][64] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][64]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][64]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~286_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist64|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][32] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][64] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .combout(\rtl~286 )); defparam \rtl~286_I .shared_arith = "off"; defparam \rtl~286_I .extended_lut = "off"; defparam \rtl~286_I .lut_mask = "0303F3F300F500F5"; cyclonev_lcell_comb \rtl~179_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux20~0 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux28~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux36~0 ), .dataf(\__ALT_INV__rtl~286 ), .combout(\rtl~179 )); defparam \rtl~179_I .shared_arith = "off"; defparam \rtl~179_I .extended_lut = "off"; defparam \rtl~179_I .lut_mask = "101C131FD0DCD3DF"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[64]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~179 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[64] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[64]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[64]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2549,portadatain_unconnected_wire_2550,portadatain_unconnected_wire_2551,portadatain_unconnected_wire_2552,portadatain_unconnected_wire_2553,portadatain_unconnected_wire_2554,portadatain_unconnected_wire_2555, portadatain_unconnected_wire_2556,portadatain_unconnected_wire_2557,portadatain_unconnected_wire_2558,portadatain_unconnected_wire_2559,portadatain_unconnected_wire_2560,portadatain_unconnected_wire_2561,portadatain_unconnected_wire_2562, portadatain_unconnected_wire_2563,portadatain_unconnected_wire_2564,portadatain_unconnected_wire_2565,portadatain_unconnected_wire_2566,portadatain_unconnected_wire_2567,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][28] }), .portaaddr({portaaddr_unconnected_wire_2568,portaaddr_unconnected_wire_2569,portaaddr_unconnected_wire_2570,portaaddr_unconnected_wire_2571,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2572,portbaddr_unconnected_wire_2573,portbaddr_unconnected_wire_2574,portbaddr_unconnected_wire_2575, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[28] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28 .first_bit_number = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama28 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[28] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][28]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2576,portadatain_unconnected_wire_2577,portadatain_unconnected_wire_2578,portadatain_unconnected_wire_2579,portadatain_unconnected_wire_2580,portadatain_unconnected_wire_2581,portadatain_unconnected_wire_2582, portadatain_unconnected_wire_2583,portadatain_unconnected_wire_2584,portadatain_unconnected_wire_2585,portadatain_unconnected_wire_2586,portadatain_unconnected_wire_2587,portadatain_unconnected_wire_2588,portadatain_unconnected_wire_2589, portadatain_unconnected_wire_2590,portadatain_unconnected_wire_2591,portadatain_unconnected_wire_2592,portadatain_unconnected_wire_2593,portadatain_unconnected_wire_2594,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][44] }), .portaaddr({portaaddr_unconnected_wire_2595,portaaddr_unconnected_wire_2596,portaaddr_unconnected_wire_2597,portaaddr_unconnected_wire_2598,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2599,portbaddr_unconnected_wire_2600,portbaddr_unconnected_wire_2601,portbaddr_unconnected_wire_2602, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[44] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44 .first_bit_number = 44; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama44 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][44]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[44] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][44] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][44]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][44]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2603,portadatain_unconnected_wire_2604,portadatain_unconnected_wire_2605,portadatain_unconnected_wire_2606,portadatain_unconnected_wire_2607,portadatain_unconnected_wire_2608,portadatain_unconnected_wire_2609, portadatain_unconnected_wire_2610,portadatain_unconnected_wire_2611,portadatain_unconnected_wire_2612,portadatain_unconnected_wire_2613,portadatain_unconnected_wire_2614,portadatain_unconnected_wire_2615,portadatain_unconnected_wire_2616, portadatain_unconnected_wire_2617,portadatain_unconnected_wire_2618,portadatain_unconnected_wire_2619,portadatain_unconnected_wire_2620,portadatain_unconnected_wire_2621,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][12] }), .portaaddr({portaaddr_unconnected_wire_2622,portaaddr_unconnected_wire_2623,portaaddr_unconnected_wire_2624,portaaddr_unconnected_wire_2625,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2626,portbaddr_unconnected_wire_2627,portbaddr_unconnected_wire_2628,portbaddr_unconnected_wire_2629, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[12] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12 .first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama12 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux32~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][44] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][12] ), .combout(\fp_pow_0002:fp_pow_inst|Mux32~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux32~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux32~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux32~0_I .lut_mask = "0088008844CC44CC"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2630,portadatain_unconnected_wire_2631,portadatain_unconnected_wire_2632,portadatain_unconnected_wire_2633,portadatain_unconnected_wire_2634,portadatain_unconnected_wire_2635,portadatain_unconnected_wire_2636, portadatain_unconnected_wire_2637,portadatain_unconnected_wire_2638,portadatain_unconnected_wire_2639,portadatain_unconnected_wire_2640,portadatain_unconnected_wire_2641,portadatain_unconnected_wire_2642,portadatain_unconnected_wire_2643, portadatain_unconnected_wire_2644,portadatain_unconnected_wire_2645,portadatain_unconnected_wire_2646,portadatain_unconnected_wire_2647,portadatain_unconnected_wire_2648,\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[9] }), .portaaddr({portaaddr_unconnected_wire_2649,portaaddr_unconnected_wire_2650,portaaddr_unconnected_wire_2651,portaaddr_unconnected_wire_2652,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2653,portbaddr_unconnected_wire_2654,portbaddr_unconnected_wire_2655,portbaddr_unconnected_wire_2656, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[60] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60 .first_bit_number = 60; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama60 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][60]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[60] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][60] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][60]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][60]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~289_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][28] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~1 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux32~0 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][60] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~0 ), .combout(\rtl~289 )); defparam \rtl~289_I .shared_arith = "off"; defparam \rtl~289_I .extended_lut = "off"; defparam \rtl~289_I .lut_mask = "0C3F0C3F44444444"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2657,portadatain_unconnected_wire_2658,portadatain_unconnected_wire_2659,portadatain_unconnected_wire_2660,portadatain_unconnected_wire_2661,portadatain_unconnected_wire_2662,portadatain_unconnected_wire_2663, portadatain_unconnected_wire_2664,portadatain_unconnected_wire_2665,portadatain_unconnected_wire_2666,portadatain_unconnected_wire_2667,portadatain_unconnected_wire_2668,portadatain_unconnected_wire_2669,portadatain_unconnected_wire_2670, portadatain_unconnected_wire_2671,portadatain_unconnected_wire_2672,portadatain_unconnected_wire_2673,portadatain_unconnected_wire_2674,portadatain_unconnected_wire_2675,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][20] }), .portaaddr({portaaddr_unconnected_wire_2676,portaaddr_unconnected_wire_2677,portaaddr_unconnected_wire_2678,portaaddr_unconnected_wire_2679,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2680,portbaddr_unconnected_wire_2681,portbaddr_unconnected_wire_2682,portbaddr_unconnected_wire_2683, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[20] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20 .first_bit_number = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama20 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][20]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|__ALT_INV__dataout_reg[20] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][20]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][20]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][20]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][20]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][20]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2684,portadatain_unconnected_wire_2685,portadatain_unconnected_wire_2686,portadatain_unconnected_wire_2687,portadatain_unconnected_wire_2688,portadatain_unconnected_wire_2689,portadatain_unconnected_wire_2690, portadatain_unconnected_wire_2691,portadatain_unconnected_wire_2692,portadatain_unconnected_wire_2693,portadatain_unconnected_wire_2694,portadatain_unconnected_wire_2695,portadatain_unconnected_wire_2696,portadatain_unconnected_wire_2697, portadatain_unconnected_wire_2698,portadatain_unconnected_wire_2699,portadatain_unconnected_wire_2700,portadatain_unconnected_wire_2701,portadatain_unconnected_wire_2702,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][36] }), .portaaddr({portaaddr_unconnected_wire_2703,portaaddr_unconnected_wire_2704,portaaddr_unconnected_wire_2705,portaaddr_unconnected_wire_2706,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2707,portbaddr_unconnected_wire_2708,portbaddr_unconnected_wire_2709,portbaddr_unconnected_wire_2710, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[36] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36 .first_bit_number = 36; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama36 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][36]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[36] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][36] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][36]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2711,portadatain_unconnected_wire_2712,portadatain_unconnected_wire_2713,portadatain_unconnected_wire_2714,portadatain_unconnected_wire_2715,portadatain_unconnected_wire_2716,portadatain_unconnected_wire_2717, portadatain_unconnected_wire_2718,portadatain_unconnected_wire_2719,portadatain_unconnected_wire_2720,portadatain_unconnected_wire_2721,portadatain_unconnected_wire_2722,portadatain_unconnected_wire_2723,portadatain_unconnected_wire_2724, portadatain_unconnected_wire_2725,portadatain_unconnected_wire_2726,portadatain_unconnected_wire_2727,portadatain_unconnected_wire_2728,portadatain_unconnected_wire_2729,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][4] }), .portaaddr({portaaddr_unconnected_wire_2730,portaaddr_unconnected_wire_2731,portaaddr_unconnected_wire_2732,portaaddr_unconnected_wire_2733,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2734,portbaddr_unconnected_wire_2735,portbaddr_unconnected_wire_2736,portbaddr_unconnected_wire_2737, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[4] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4 .first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama4 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2738,portadatain_unconnected_wire_2739,portadatain_unconnected_wire_2740,portadatain_unconnected_wire_2741,portadatain_unconnected_wire_2742,portadatain_unconnected_wire_2743,portadatain_unconnected_wire_2744, portadatain_unconnected_wire_2745,portadatain_unconnected_wire_2746,portadatain_unconnected_wire_2747,portadatain_unconnected_wire_2748,portadatain_unconnected_wire_2749,portadatain_unconnected_wire_2750,portadatain_unconnected_wire_2751, portadatain_unconnected_wire_2752,portadatain_unconnected_wire_2753,portadatain_unconnected_wire_2754,portadatain_unconnected_wire_2755,portadatain_unconnected_wire_2756,\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[1] }), .portaaddr({portaaddr_unconnected_wire_2757,portaaddr_unconnected_wire_2758,portaaddr_unconnected_wire_2759,portaaddr_unconnected_wire_2760,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2761,portbaddr_unconnected_wire_2762,portbaddr_unconnected_wire_2763,portbaddr_unconnected_wire_2764, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[52] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52 .first_bit_number = 52; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama52 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][52]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[52] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][52] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][52]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][52]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~287_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][20] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][36] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][52] ), .combout(\rtl~287 )); defparam \rtl~287_I .shared_arith = "off"; defparam \rtl~287_I .extended_lut = "off"; defparam \rtl~287_I .lut_mask = "101A151FB0BAB5BF"; cyclonev_lcell_comb \rtl~290_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\__ALT_INV__rtl~289 ), .datad(\__ALT_INV__rtl~287 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .combout(\rtl~290 )); defparam \rtl~290_I .shared_arith = "off"; defparam \rtl~290_I .extended_lut = "off"; defparam \rtl~290_I .lut_mask = "0A5F0A5F0A0A0A0A"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~290 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2765,portadatain_unconnected_wire_2766,portadatain_unconnected_wire_2767,portadatain_unconnected_wire_2768,portadatain_unconnected_wire_2769,portadatain_unconnected_wire_2770,portadatain_unconnected_wire_2771, portadatain_unconnected_wire_2772,portadatain_unconnected_wire_2773,portadatain_unconnected_wire_2774,portadatain_unconnected_wire_2775,portadatain_unconnected_wire_2776,portadatain_unconnected_wire_2777,portadatain_unconnected_wire_2778, portadatain_unconnected_wire_2779,portadatain_unconnected_wire_2780,portadatain_unconnected_wire_2781,portadatain_unconnected_wire_2782,portadatain_unconnected_wire_2783,\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[3] }), .portaaddr({portaaddr_unconnected_wire_2784,portaaddr_unconnected_wire_2785,portaaddr_unconnected_wire_2786,portaaddr_unconnected_wire_2787,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2788,portbaddr_unconnected_wire_2789,portbaddr_unconnected_wire_2790,portbaddr_unconnected_wire_2791, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[54] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54 .first_bit_number = 54; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama54 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][54]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[54] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][54] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][54]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][54]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][38]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][38]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][38] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][38]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2792,portadatain_unconnected_wire_2793,portadatain_unconnected_wire_2794,portadatain_unconnected_wire_2795,portadatain_unconnected_wire_2796,portadatain_unconnected_wire_2797,portadatain_unconnected_wire_2798, portadatain_unconnected_wire_2799,portadatain_unconnected_wire_2800,portadatain_unconnected_wire_2801,portadatain_unconnected_wire_2802,portadatain_unconnected_wire_2803,portadatain_unconnected_wire_2804,portadatain_unconnected_wire_2805, portadatain_unconnected_wire_2806,portadatain_unconnected_wire_2807,portadatain_unconnected_wire_2808,portadatain_unconnected_wire_2809,portadatain_unconnected_wire_2810,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][38] }), .portaaddr({portaaddr_unconnected_wire_2811,portaaddr_unconnected_wire_2812,portaaddr_unconnected_wire_2813,portaaddr_unconnected_wire_2814,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2815,portbaddr_unconnected_wire_2816,portbaddr_unconnected_wire_2817,portbaddr_unconnected_wire_2818, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[38] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38 .first_bit_number = 38; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama38 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][38]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[38] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][38] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][38]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2819,portadatain_unconnected_wire_2820,portadatain_unconnected_wire_2821,portadatain_unconnected_wire_2822,portadatain_unconnected_wire_2823,portadatain_unconnected_wire_2824,portadatain_unconnected_wire_2825, portadatain_unconnected_wire_2826,portadatain_unconnected_wire_2827,portadatain_unconnected_wire_2828,portadatain_unconnected_wire_2829,portadatain_unconnected_wire_2830,portadatain_unconnected_wire_2831,portadatain_unconnected_wire_2832, portadatain_unconnected_wire_2833,portadatain_unconnected_wire_2834,portadatain_unconnected_wire_2835,portadatain_unconnected_wire_2836,portadatain_unconnected_wire_2837,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][22] }), .portaaddr({portaaddr_unconnected_wire_2838,portaaddr_unconnected_wire_2839,portaaddr_unconnected_wire_2840,portaaddr_unconnected_wire_2841,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2842,portbaddr_unconnected_wire_2843,portbaddr_unconnected_wire_2844,portbaddr_unconnected_wire_2845, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[22] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22 .first_bit_number = 22; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama22 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[22] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2846,portadatain_unconnected_wire_2847,portadatain_unconnected_wire_2848,portadatain_unconnected_wire_2849,portadatain_unconnected_wire_2850,portadatain_unconnected_wire_2851,portadatain_unconnected_wire_2852, portadatain_unconnected_wire_2853,portadatain_unconnected_wire_2854,portadatain_unconnected_wire_2855,portadatain_unconnected_wire_2856,portadatain_unconnected_wire_2857,portadatain_unconnected_wire_2858,portadatain_unconnected_wire_2859, portadatain_unconnected_wire_2860,portadatain_unconnected_wire_2861,portadatain_unconnected_wire_2862,portadatain_unconnected_wire_2863,portadatain_unconnected_wire_2864,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][6] }), .portaaddr({portaaddr_unconnected_wire_2865,portaaddr_unconnected_wire_2866,portaaddr_unconnected_wire_2867,portaaddr_unconnected_wire_2868,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2869,portbaddr_unconnected_wire_2870,portbaddr_unconnected_wire_2871,portbaddr_unconnected_wire_2872, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[6] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6 .first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama6 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~291_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][54] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][38] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][22] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][6] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .combout(\rtl~291 )); defparam \rtl~291_I .shared_arith = "off"; defparam \rtl~291_I .extended_lut = "off"; defparam \rtl~291_I .lut_mask = "5353535300F00FFF"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2873,portadatain_unconnected_wire_2874,portadatain_unconnected_wire_2875,portadatain_unconnected_wire_2876,portadatain_unconnected_wire_2877,portadatain_unconnected_wire_2878,portadatain_unconnected_wire_2879, portadatain_unconnected_wire_2880,portadatain_unconnected_wire_2881,portadatain_unconnected_wire_2882,portadatain_unconnected_wire_2883,portadatain_unconnected_wire_2884,portadatain_unconnected_wire_2885,portadatain_unconnected_wire_2886, portadatain_unconnected_wire_2887,portadatain_unconnected_wire_2888,portadatain_unconnected_wire_2889,portadatain_unconnected_wire_2890,portadatain_unconnected_wire_2891,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][30] }), .portaaddr({portaaddr_unconnected_wire_2892,portaaddr_unconnected_wire_2893,portaaddr_unconnected_wire_2894,portaaddr_unconnected_wire_2895,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2896,portbaddr_unconnected_wire_2897,portbaddr_unconnected_wire_2898,portbaddr_unconnected_wire_2899, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[30] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30 .first_bit_number = 30; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama30 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[30] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][30]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2900,portadatain_unconnected_wire_2901,portadatain_unconnected_wire_2902,portadatain_unconnected_wire_2903,portadatain_unconnected_wire_2904,portadatain_unconnected_wire_2905,portadatain_unconnected_wire_2906, portadatain_unconnected_wire_2907,portadatain_unconnected_wire_2908,portadatain_unconnected_wire_2909,portadatain_unconnected_wire_2910,portadatain_unconnected_wire_2911,portadatain_unconnected_wire_2912,portadatain_unconnected_wire_2913, portadatain_unconnected_wire_2914,portadatain_unconnected_wire_2915,portadatain_unconnected_wire_2916,portadatain_unconnected_wire_2917,portadatain_unconnected_wire_2918,\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[11] }), .portaaddr({portaaddr_unconnected_wire_2919,portaaddr_unconnected_wire_2920,portaaddr_unconnected_wire_2921,portaaddr_unconnected_wire_2922,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2923,portbaddr_unconnected_wire_2924,portbaddr_unconnected_wire_2925,portbaddr_unconnected_wire_2926, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[62] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62 .first_bit_number = 62; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama62 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][62]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[62] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][62] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][62]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][62]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2927,portadatain_unconnected_wire_2928,portadatain_unconnected_wire_2929,portadatain_unconnected_wire_2930,portadatain_unconnected_wire_2931,portadatain_unconnected_wire_2932,portadatain_unconnected_wire_2933, portadatain_unconnected_wire_2934,portadatain_unconnected_wire_2935,portadatain_unconnected_wire_2936,portadatain_unconnected_wire_2937,portadatain_unconnected_wire_2938,portadatain_unconnected_wire_2939,portadatain_unconnected_wire_2940, portadatain_unconnected_wire_2941,portadatain_unconnected_wire_2942,portadatain_unconnected_wire_2943,portadatain_unconnected_wire_2944,portadatain_unconnected_wire_2945,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][14] }), .portaaddr({portaaddr_unconnected_wire_2946,portaaddr_unconnected_wire_2947,portaaddr_unconnected_wire_2948,portaaddr_unconnected_wire_2949,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2950,portbaddr_unconnected_wire_2951,portbaddr_unconnected_wire_2952,portbaddr_unconnected_wire_2953, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[14] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14 .first_bit_number = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama14 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[14] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2954,portadatain_unconnected_wire_2955,portadatain_unconnected_wire_2956,portadatain_unconnected_wire_2957,portadatain_unconnected_wire_2958,portadatain_unconnected_wire_2959,portadatain_unconnected_wire_2960, portadatain_unconnected_wire_2961,portadatain_unconnected_wire_2962,portadatain_unconnected_wire_2963,portadatain_unconnected_wire_2964,portadatain_unconnected_wire_2965,portadatain_unconnected_wire_2966,portadatain_unconnected_wire_2967, portadatain_unconnected_wire_2968,portadatain_unconnected_wire_2969,portadatain_unconnected_wire_2970,portadatain_unconnected_wire_2971,portadatain_unconnected_wire_2972,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][46] }), .portaaddr({portaaddr_unconnected_wire_2973,portaaddr_unconnected_wire_2974,portaaddr_unconnected_wire_2975,portaaddr_unconnected_wire_2976,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_2977,portbaddr_unconnected_wire_2978,portbaddr_unconnected_wire_2979,portbaddr_unconnected_wire_2980, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[46] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46 .first_bit_number = 46; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama46 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][46]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[46] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][46] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][46]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][46]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux30~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][14] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][46] ), .combout(\fp_pow_0002:fp_pow_inst|Mux30~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux30~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux30~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux30~0_I .lut_mask = "028A028A028A028A"; cyclonev_lcell_comb \rtl~292_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~1 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][30] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~0 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][62] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux30~0 ), .combout(\rtl~292 )); defparam \rtl~292_I .shared_arith = "off"; defparam \rtl~292_I .extended_lut = "off"; defparam \rtl~292_I .lut_mask = "02025252A2A2F2F2"; cyclonev_lcell_comb \rtl~293_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datab(\__ALT_INV__rtl~291 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~292 ), .combout(\rtl~293 )); defparam \rtl~293_I .shared_arith = "off"; defparam \rtl~293_I .extended_lut = "off"; defparam \rtl~293_I .lut_mask = "10101010BABABABA"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[62]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~293 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[62] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[62]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[62]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~147_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[58] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[64] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[62] ), .combout(\rtl~147 )); defparam \rtl~147_I .shared_arith = "off"; defparam \rtl~147_I .extended_lut = "off"; defparam \rtl~147_I .lut_mask = "30053F0530F53FF5"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_2981,portadatain_unconnected_wire_2982,portadatain_unconnected_wire_2983,portadatain_unconnected_wire_2984,portadatain_unconnected_wire_2985,portadatain_unconnected_wire_2986,portadatain_unconnected_wire_2987, portadatain_unconnected_wire_2988,portadatain_unconnected_wire_2989,portadatain_unconnected_wire_2990,portadatain_unconnected_wire_2991,portadatain_unconnected_wire_2992,portadatain_unconnected_wire_2993,portadatain_unconnected_wire_2994, portadatain_unconnected_wire_2995,portadatain_unconnected_wire_2996,portadatain_unconnected_wire_2997,portadatain_unconnected_wire_2998,portadatain_unconnected_wire_2999,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][25] }), .portaaddr({portaaddr_unconnected_wire_3000,portaaddr_unconnected_wire_3001,portaaddr_unconnected_wire_3002,portaaddr_unconnected_wire_3003,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3004,portbaddr_unconnected_wire_3005,portbaddr_unconnected_wire_3006,portbaddr_unconnected_wire_3007, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[25] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25 .first_bit_number = 25; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama25 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[25] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][25]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3008,portadatain_unconnected_wire_3009,portadatain_unconnected_wire_3010,portadatain_unconnected_wire_3011,portadatain_unconnected_wire_3012,portadatain_unconnected_wire_3013,portadatain_unconnected_wire_3014, portadatain_unconnected_wire_3015,portadatain_unconnected_wire_3016,portadatain_unconnected_wire_3017,portadatain_unconnected_wire_3018,portadatain_unconnected_wire_3019,portadatain_unconnected_wire_3020,portadatain_unconnected_wire_3021, portadatain_unconnected_wire_3022,portadatain_unconnected_wire_3023,portadatain_unconnected_wire_3024,portadatain_unconnected_wire_3025,portadatain_unconnected_wire_3026,\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[6] }), .portaaddr({portaaddr_unconnected_wire_3027,portaaddr_unconnected_wire_3028,portaaddr_unconnected_wire_3029,portaaddr_unconnected_wire_3030,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3031,portbaddr_unconnected_wire_3032,portbaddr_unconnected_wire_3033,portbaddr_unconnected_wire_3034, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[57] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57 .first_bit_number = 57; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama57 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][57]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[57] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][57] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][57]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][57]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux19~0_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][25] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][57] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Mux19~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux19~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux19~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux19~0_I .lut_mask = "0000F0F030303030"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3035,portadatain_unconnected_wire_3036,portadatain_unconnected_wire_3037,portadatain_unconnected_wire_3038,portadatain_unconnected_wire_3039,portadatain_unconnected_wire_3040,portadatain_unconnected_wire_3041, portadatain_unconnected_wire_3042,portadatain_unconnected_wire_3043,portadatain_unconnected_wire_3044,portadatain_unconnected_wire_3045,portadatain_unconnected_wire_3046,portadatain_unconnected_wire_3047,portadatain_unconnected_wire_3048, portadatain_unconnected_wire_3049,portadatain_unconnected_wire_3050,portadatain_unconnected_wire_3051,portadatain_unconnected_wire_3052,portadatain_unconnected_wire_3053,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][17]~DUPLICATE }), .portaaddr({portaaddr_unconnected_wire_3054,portaaddr_unconnected_wire_3055,portaaddr_unconnected_wire_3056,portaaddr_unconnected_wire_3057,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3058,portbaddr_unconnected_wire_3059,portbaddr_unconnected_wire_3060,portbaddr_unconnected_wire_3061, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[17] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17 .first_bit_number = 17; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama17 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3062,portadatain_unconnected_wire_3063,portadatain_unconnected_wire_3064,portadatain_unconnected_wire_3065,portadatain_unconnected_wire_3066,portadatain_unconnected_wire_3067,portadatain_unconnected_wire_3068, portadatain_unconnected_wire_3069,portadatain_unconnected_wire_3070,portadatain_unconnected_wire_3071,portadatain_unconnected_wire_3072,portadatain_unconnected_wire_3073,portadatain_unconnected_wire_3074,portadatain_unconnected_wire_3075, portadatain_unconnected_wire_3076,portadatain_unconnected_wire_3077,portadatain_unconnected_wire_3078,portadatain_unconnected_wire_3079,portadatain_unconnected_wire_3080,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][49] }), .portaaddr({portaaddr_unconnected_wire_3081,portaaddr_unconnected_wire_3082,portaaddr_unconnected_wire_3083,portaaddr_unconnected_wire_3084,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3085,portbaddr_unconnected_wire_3086,portbaddr_unconnected_wire_3087,portbaddr_unconnected_wire_3088, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[49] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49 .first_bit_number = 49; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama49 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][49]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[49] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][49] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][49]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][49]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux27~0_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][17] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][49] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Mux27~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux27~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux27~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux27~0_I .lut_mask = "00F000F030303030"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3089,portadatain_unconnected_wire_3090,portadatain_unconnected_wire_3091,portadatain_unconnected_wire_3092,portadatain_unconnected_wire_3093,portadatain_unconnected_wire_3094,portadatain_unconnected_wire_3095, portadatain_unconnected_wire_3096,portadatain_unconnected_wire_3097,portadatain_unconnected_wire_3098,portadatain_unconnected_wire_3099,portadatain_unconnected_wire_3100,portadatain_unconnected_wire_3101,portadatain_unconnected_wire_3102, portadatain_unconnected_wire_3103,portadatain_unconnected_wire_3104,portadatain_unconnected_wire_3105,portadatain_unconnected_wire_3106,portadatain_unconnected_wire_3107,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][33] }), .portaaddr({portaaddr_unconnected_wire_3108,portaaddr_unconnected_wire_3109,portaaddr_unconnected_wire_3110,portaaddr_unconnected_wire_3111,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3112,portbaddr_unconnected_wire_3113,portbaddr_unconnected_wire_3114,portbaddr_unconnected_wire_3115, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[33] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33 .first_bit_number = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama33 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[33] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[4][1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[4][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[4][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[4][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[4][1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[4][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[4][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[4][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[4][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[4][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[3][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[4][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[3][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[3][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[3][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[2][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[3][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[2][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[2][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[2][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[1][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[2][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[1][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[1][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[1][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[1][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist64|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3116,portadatain_unconnected_wire_3117,portadatain_unconnected_wire_3118,portadatain_unconnected_wire_3119,portadatain_unconnected_wire_3120,portadatain_unconnected_wire_3121,portadatain_unconnected_wire_3122, portadatain_unconnected_wire_3123,portadatain_unconnected_wire_3124,portadatain_unconnected_wire_3125,portadatain_unconnected_wire_3126,portadatain_unconnected_wire_3127,portadatain_unconnected_wire_3128,portadatain_unconnected_wire_3129, portadatain_unconnected_wire_3130,portadatain_unconnected_wire_3131,portadatain_unconnected_wire_3132,portadatain_unconnected_wire_3133,portadatain_unconnected_wire_3134,\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[14]~DUPLICATE }), .portaaddr({portaaddr_unconnected_wire_3135,portaaddr_unconnected_wire_3136,portaaddr_unconnected_wire_3137,portaaddr_unconnected_wire_3138,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3139,portbaddr_unconnected_wire_3140,portbaddr_unconnected_wire_3141,portbaddr_unconnected_wire_3142, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[65] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65 .first_bit_number = 65; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama65 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][65]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[65] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][65] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][65]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][65]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~297_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][33] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist64|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][65] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .combout(\rtl~297 )); defparam \rtl~297_I .shared_arith = "off"; defparam \rtl~297_I .extended_lut = "off"; defparam \rtl~297_I .lut_mask = "1111BBBB01AB01AB"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3143,portadatain_unconnected_wire_3144,portadatain_unconnected_wire_3145,portadatain_unconnected_wire_3146,portadatain_unconnected_wire_3147,portadatain_unconnected_wire_3148,portadatain_unconnected_wire_3149, portadatain_unconnected_wire_3150,portadatain_unconnected_wire_3151,portadatain_unconnected_wire_3152,portadatain_unconnected_wire_3153,portadatain_unconnected_wire_3154,portadatain_unconnected_wire_3155,portadatain_unconnected_wire_3156, portadatain_unconnected_wire_3157,portadatain_unconnected_wire_3158,portadatain_unconnected_wire_3159,portadatain_unconnected_wire_3160,portadatain_unconnected_wire_3161,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][9] }), .portaaddr({portaaddr_unconnected_wire_3162,portaaddr_unconnected_wire_3163,portaaddr_unconnected_wire_3164,portaaddr_unconnected_wire_3165,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3166,portbaddr_unconnected_wire_3167,portbaddr_unconnected_wire_3168,portbaddr_unconnected_wire_3169, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[9] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9 .first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama9 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3170,portadatain_unconnected_wire_3171,portadatain_unconnected_wire_3172,portadatain_unconnected_wire_3173,portadatain_unconnected_wire_3174,portadatain_unconnected_wire_3175,portadatain_unconnected_wire_3176, portadatain_unconnected_wire_3177,portadatain_unconnected_wire_3178,portadatain_unconnected_wire_3179,portadatain_unconnected_wire_3180,portadatain_unconnected_wire_3181,portadatain_unconnected_wire_3182,portadatain_unconnected_wire_3183, portadatain_unconnected_wire_3184,portadatain_unconnected_wire_3185,portadatain_unconnected_wire_3186,portadatain_unconnected_wire_3187,portadatain_unconnected_wire_3188,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][41]~DUPLICATE }), .portaaddr({portaaddr_unconnected_wire_3189,portaaddr_unconnected_wire_3190,portaaddr_unconnected_wire_3191,portaaddr_unconnected_wire_3192,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3193,portbaddr_unconnected_wire_3194,portbaddr_unconnected_wire_3195,portbaddr_unconnected_wire_3196, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[41] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41 .first_bit_number = 41; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama41 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][41]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[41] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][41] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][41]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux35~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][9] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][41] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Mux35~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux35~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux35~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux35~0_I .lut_mask = "00AA00AA0A0A0A0A"; cyclonev_lcell_comb \rtl~153_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux19~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux27~0 ), .datae(\__ALT_INV__rtl~297 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux35~0 ), .combout(\rtl~153 )); defparam \rtl~153_I .shared_arith = "off"; defparam \rtl~153_I .extended_lut = "off"; defparam \rtl~153_I .lut_mask = "04268CAE15379DBF"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[65]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~153 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[65] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[65]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[65]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist52|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] )); defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3197,portadatain_unconnected_wire_3198,portadatain_unconnected_wire_3199,portadatain_unconnected_wire_3200,portadatain_unconnected_wire_3201,portadatain_unconnected_wire_3202,portadatain_unconnected_wire_3203, portadatain_unconnected_wire_3204,portadatain_unconnected_wire_3205,portadatain_unconnected_wire_3206,portadatain_unconnected_wire_3207,portadatain_unconnected_wire_3208,portadatain_unconnected_wire_3209,portadatain_unconnected_wire_3210, portadatain_unconnected_wire_3211,portadatain_unconnected_wire_3212,portadatain_unconnected_wire_3213,portadatain_unconnected_wire_3214,portadatain_unconnected_wire_3215,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][13] }), .portaaddr({portaaddr_unconnected_wire_3216,portaaddr_unconnected_wire_3217,portaaddr_unconnected_wire_3218,portaaddr_unconnected_wire_3219,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3220,portbaddr_unconnected_wire_3221,portbaddr_unconnected_wire_3222,portbaddr_unconnected_wire_3223, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[13] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13 .first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama13 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3224,portadatain_unconnected_wire_3225,portadatain_unconnected_wire_3226,portadatain_unconnected_wire_3227,portadatain_unconnected_wire_3228,portadatain_unconnected_wire_3229,portadatain_unconnected_wire_3230, portadatain_unconnected_wire_3231,portadatain_unconnected_wire_3232,portadatain_unconnected_wire_3233,portadatain_unconnected_wire_3234,portadatain_unconnected_wire_3235,portadatain_unconnected_wire_3236,portadatain_unconnected_wire_3237, portadatain_unconnected_wire_3238,portadatain_unconnected_wire_3239,portadatain_unconnected_wire_3240,portadatain_unconnected_wire_3241,portadatain_unconnected_wire_3242,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][45]~DUPLICATE }), .portaaddr({portaaddr_unconnected_wire_3243,portaaddr_unconnected_wire_3244,portaaddr_unconnected_wire_3245,portaaddr_unconnected_wire_3246,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3247,portbaddr_unconnected_wire_3248,portbaddr_unconnected_wire_3249,portbaddr_unconnected_wire_3250, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[45] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45 .first_bit_number = 45; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama45 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][45]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[45] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][45] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][45]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][45]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux31~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][13] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][45] ), .combout(\fp_pow_0002:fp_pow_inst|Mux31~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux31~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux31~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux31~0_I .lut_mask = "048C048C048C048C"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3251,portadatain_unconnected_wire_3252,portadatain_unconnected_wire_3253,portadatain_unconnected_wire_3254,portadatain_unconnected_wire_3255,portadatain_unconnected_wire_3256,portadatain_unconnected_wire_3257, portadatain_unconnected_wire_3258,portadatain_unconnected_wire_3259,portadatain_unconnected_wire_3260,portadatain_unconnected_wire_3261,portadatain_unconnected_wire_3262,portadatain_unconnected_wire_3263,portadatain_unconnected_wire_3264, portadatain_unconnected_wire_3265,portadatain_unconnected_wire_3266,portadatain_unconnected_wire_3267,portadatain_unconnected_wire_3268,portadatain_unconnected_wire_3269,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][29] }), .portaaddr({portaaddr_unconnected_wire_3270,portaaddr_unconnected_wire_3271,portaaddr_unconnected_wire_3272,portaaddr_unconnected_wire_3273,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3274,portbaddr_unconnected_wire_3275,portbaddr_unconnected_wire_3276,portbaddr_unconnected_wire_3277, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[29] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29 .first_bit_number = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama29 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[29] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][29]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3278,portadatain_unconnected_wire_3279,portadatain_unconnected_wire_3280,portadatain_unconnected_wire_3281,portadatain_unconnected_wire_3282,portadatain_unconnected_wire_3283,portadatain_unconnected_wire_3284, portadatain_unconnected_wire_3285,portadatain_unconnected_wire_3286,portadatain_unconnected_wire_3287,portadatain_unconnected_wire_3288,portadatain_unconnected_wire_3289,portadatain_unconnected_wire_3290,portadatain_unconnected_wire_3291, portadatain_unconnected_wire_3292,portadatain_unconnected_wire_3293,portadatain_unconnected_wire_3294,portadatain_unconnected_wire_3295,portadatain_unconnected_wire_3296,\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[10] }), .portaaddr({portaaddr_unconnected_wire_3297,portaaddr_unconnected_wire_3298,portaaddr_unconnected_wire_3299,portaaddr_unconnected_wire_3300,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3301,portbaddr_unconnected_wire_3302,portbaddr_unconnected_wire_3303,portbaddr_unconnected_wire_3304, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[61] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61 .first_bit_number = 61; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama61 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][61]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[61] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][61] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][61]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][61]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~299_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux31~0 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][29] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~1 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][61] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~0 ), .combout(\rtl~299 )); defparam \rtl~299_I .shared_arith = "off"; defparam \rtl~299_I .extended_lut = "off"; defparam \rtl~299_I .lut_mask = "550055FF33003300"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3305,portadatain_unconnected_wire_3306,portadatain_unconnected_wire_3307,portadatain_unconnected_wire_3308,portadatain_unconnected_wire_3309,portadatain_unconnected_wire_3310,portadatain_unconnected_wire_3311, portadatain_unconnected_wire_3312,portadatain_unconnected_wire_3313,portadatain_unconnected_wire_3314,portadatain_unconnected_wire_3315,portadatain_unconnected_wire_3316,portadatain_unconnected_wire_3317,portadatain_unconnected_wire_3318, portadatain_unconnected_wire_3319,portadatain_unconnected_wire_3320,portadatain_unconnected_wire_3321,portadatain_unconnected_wire_3322,portadatain_unconnected_wire_3323,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][5] }), .portaaddr({portaaddr_unconnected_wire_3324,portaaddr_unconnected_wire_3325,portaaddr_unconnected_wire_3326,portaaddr_unconnected_wire_3327,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3328,portbaddr_unconnected_wire_3329,portbaddr_unconnected_wire_3330,portbaddr_unconnected_wire_3331, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[5] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5 .first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama5 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3332,portadatain_unconnected_wire_3333,portadatain_unconnected_wire_3334,portadatain_unconnected_wire_3335,portadatain_unconnected_wire_3336,portadatain_unconnected_wire_3337,portadatain_unconnected_wire_3338, portadatain_unconnected_wire_3339,portadatain_unconnected_wire_3340,portadatain_unconnected_wire_3341,portadatain_unconnected_wire_3342,portadatain_unconnected_wire_3343,portadatain_unconnected_wire_3344,portadatain_unconnected_wire_3345, portadatain_unconnected_wire_3346,portadatain_unconnected_wire_3347,portadatain_unconnected_wire_3348,portadatain_unconnected_wire_3349,portadatain_unconnected_wire_3350,\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[2] }), .portaaddr({portaaddr_unconnected_wire_3351,portaaddr_unconnected_wire_3352,portaaddr_unconnected_wire_3353,portaaddr_unconnected_wire_3354,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3355,portbaddr_unconnected_wire_3356,portbaddr_unconnected_wire_3357,portbaddr_unconnected_wire_3358, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[53] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53 .first_bit_number = 53; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama53 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][53]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[53] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][53] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][53]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][53]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3359,portadatain_unconnected_wire_3360,portadatain_unconnected_wire_3361,portadatain_unconnected_wire_3362,portadatain_unconnected_wire_3363,portadatain_unconnected_wire_3364,portadatain_unconnected_wire_3365, portadatain_unconnected_wire_3366,portadatain_unconnected_wire_3367,portadatain_unconnected_wire_3368,portadatain_unconnected_wire_3369,portadatain_unconnected_wire_3370,portadatain_unconnected_wire_3371,portadatain_unconnected_wire_3372, portadatain_unconnected_wire_3373,portadatain_unconnected_wire_3374,portadatain_unconnected_wire_3375,portadatain_unconnected_wire_3376,portadatain_unconnected_wire_3377,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][37] }), .portaaddr({portaaddr_unconnected_wire_3378,portaaddr_unconnected_wire_3379,portaaddr_unconnected_wire_3380,portaaddr_unconnected_wire_3381,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3382,portbaddr_unconnected_wire_3383,portbaddr_unconnected_wire_3384,portbaddr_unconnected_wire_3385, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[37] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37 .first_bit_number = 37; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama37 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][37]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[37] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][37] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][37]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3386,portadatain_unconnected_wire_3387,portadatain_unconnected_wire_3388,portadatain_unconnected_wire_3389,portadatain_unconnected_wire_3390,portadatain_unconnected_wire_3391,portadatain_unconnected_wire_3392, portadatain_unconnected_wire_3393,portadatain_unconnected_wire_3394,portadatain_unconnected_wire_3395,portadatain_unconnected_wire_3396,portadatain_unconnected_wire_3397,portadatain_unconnected_wire_3398,portadatain_unconnected_wire_3399, portadatain_unconnected_wire_3400,portadatain_unconnected_wire_3401,portadatain_unconnected_wire_3402,portadatain_unconnected_wire_3403,portadatain_unconnected_wire_3404,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][21] }), .portaaddr({portaaddr_unconnected_wire_3405,portaaddr_unconnected_wire_3406,portaaddr_unconnected_wire_3407,portaaddr_unconnected_wire_3408,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3409,portbaddr_unconnected_wire_3410,portbaddr_unconnected_wire_3411,portbaddr_unconnected_wire_3412, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[21] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21 .first_bit_number = 21; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama21 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~298_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][53] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][37] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][21] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .combout(\rtl~298 )); defparam \rtl~298_I .shared_arith = "off"; defparam \rtl~298_I .extended_lut = "off"; defparam \rtl~298_I .lut_mask = "333300FF0F0F5555"; cyclonev_lcell_comb \rtl~300_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datad(\__ALT_INV__rtl~299 ), .dataf(\__ALT_INV__rtl~298 ), .combout(\rtl~300 )); defparam \rtl~300_I .shared_arith = "off"; defparam \rtl~300_I .extended_lut = "off"; defparam \rtl~300_I .lut_mask = "00F000F00AFA0AFA"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[61]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~300 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[61] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[61]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[61]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3413,portadatain_unconnected_wire_3414,portadatain_unconnected_wire_3415,portadatain_unconnected_wire_3416,portadatain_unconnected_wire_3417,portadatain_unconnected_wire_3418,portadatain_unconnected_wire_3419, portadatain_unconnected_wire_3420,portadatain_unconnected_wire_3421,portadatain_unconnected_wire_3422,portadatain_unconnected_wire_3423,portadatain_unconnected_wire_3424,portadatain_unconnected_wire_3425,portadatain_unconnected_wire_3426, portadatain_unconnected_wire_3427,portadatain_unconnected_wire_3428,portadatain_unconnected_wire_3429,portadatain_unconnected_wire_3430,portadatain_unconnected_wire_3431,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][35] }), .portaaddr({portaaddr_unconnected_wire_3432,portaaddr_unconnected_wire_3433,portaaddr_unconnected_wire_3434,portaaddr_unconnected_wire_3435,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3436,portbaddr_unconnected_wire_3437,portbaddr_unconnected_wire_3438,portbaddr_unconnected_wire_3439, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[35] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35 .first_bit_number = 35; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama35 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[35] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][35]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3440,portadatain_unconnected_wire_3441,portadatain_unconnected_wire_3442,portadatain_unconnected_wire_3443,portadatain_unconnected_wire_3444,portadatain_unconnected_wire_3445,portadatain_unconnected_wire_3446, portadatain_unconnected_wire_3447,portadatain_unconnected_wire_3448,portadatain_unconnected_wire_3449,portadatain_unconnected_wire_3450,portadatain_unconnected_wire_3451,portadatain_unconnected_wire_3452,portadatain_unconnected_wire_3453, portadatain_unconnected_wire_3454,portadatain_unconnected_wire_3455,portadatain_unconnected_wire_3456,portadatain_unconnected_wire_3457,portadatain_unconnected_wire_3458,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][51] }), .portaaddr({portaaddr_unconnected_wire_3459,portaaddr_unconnected_wire_3460,portaaddr_unconnected_wire_3461,portaaddr_unconnected_wire_3462,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3463,portbaddr_unconnected_wire_3464,portbaddr_unconnected_wire_3465,portbaddr_unconnected_wire_3466, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[51] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51 .first_bit_number = 51; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama51 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][51]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[51] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][51] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][51]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][51]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3467,portadatain_unconnected_wire_3468,portadatain_unconnected_wire_3469,portadatain_unconnected_wire_3470,portadatain_unconnected_wire_3471,portadatain_unconnected_wire_3472,portadatain_unconnected_wire_3473, portadatain_unconnected_wire_3474,portadatain_unconnected_wire_3475,portadatain_unconnected_wire_3476,portadatain_unconnected_wire_3477,portadatain_unconnected_wire_3478,portadatain_unconnected_wire_3479,portadatain_unconnected_wire_3480, portadatain_unconnected_wire_3481,portadatain_unconnected_wire_3482,portadatain_unconnected_wire_3483,portadatain_unconnected_wire_3484,portadatain_unconnected_wire_3485,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][3] }), .portaaddr({portaaddr_unconnected_wire_3486,portaaddr_unconnected_wire_3487,portaaddr_unconnected_wire_3488,portaaddr_unconnected_wire_3489,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3490,portbaddr_unconnected_wire_3491,portbaddr_unconnected_wire_3492,portbaddr_unconnected_wire_3493, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[3] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3 .first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama3 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3494,portadatain_unconnected_wire_3495,portadatain_unconnected_wire_3496,portadatain_unconnected_wire_3497,portadatain_unconnected_wire_3498,portadatain_unconnected_wire_3499,portadatain_unconnected_wire_3500, portadatain_unconnected_wire_3501,portadatain_unconnected_wire_3502,portadatain_unconnected_wire_3503,portadatain_unconnected_wire_3504,portadatain_unconnected_wire_3505,portadatain_unconnected_wire_3506,portadatain_unconnected_wire_3507, portadatain_unconnected_wire_3508,portadatain_unconnected_wire_3509,portadatain_unconnected_wire_3510,portadatain_unconnected_wire_3511,portadatain_unconnected_wire_3512,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][19] }), .portaaddr({portaaddr_unconnected_wire_3513,portaaddr_unconnected_wire_3514,portaaddr_unconnected_wire_3515,portaaddr_unconnected_wire_3516,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3517,portbaddr_unconnected_wire_3518,portbaddr_unconnected_wire_3519,portbaddr_unconnected_wire_3520, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[19] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19 .first_bit_number = 19; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama19 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~304_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][35] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][51] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][19] ), .combout(\rtl~304 )); defparam \rtl~304_I .shared_arith = "off"; defparam \rtl~304_I .extended_lut = "off"; defparam \rtl~304_I .lut_mask = "3050305F3F503F5F"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3521,portadatain_unconnected_wire_3522,portadatain_unconnected_wire_3523,portadatain_unconnected_wire_3524,portadatain_unconnected_wire_3525,portadatain_unconnected_wire_3526,portadatain_unconnected_wire_3527, portadatain_unconnected_wire_3528,portadatain_unconnected_wire_3529,portadatain_unconnected_wire_3530,portadatain_unconnected_wire_3531,portadatain_unconnected_wire_3532,portadatain_unconnected_wire_3533,portadatain_unconnected_wire_3534, portadatain_unconnected_wire_3535,portadatain_unconnected_wire_3536,portadatain_unconnected_wire_3537,portadatain_unconnected_wire_3538,portadatain_unconnected_wire_3539,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][27] }), .portaaddr({portaaddr_unconnected_wire_3540,portaaddr_unconnected_wire_3541,portaaddr_unconnected_wire_3542,portaaddr_unconnected_wire_3543,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3544,portbaddr_unconnected_wire_3545,portbaddr_unconnected_wire_3546,portbaddr_unconnected_wire_3547, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[27] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27 .first_bit_number = 27; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama27 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[27] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][27]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3548,portadatain_unconnected_wire_3549,portadatain_unconnected_wire_3550,portadatain_unconnected_wire_3551,portadatain_unconnected_wire_3552,portadatain_unconnected_wire_3553,portadatain_unconnected_wire_3554, portadatain_unconnected_wire_3555,portadatain_unconnected_wire_3556,portadatain_unconnected_wire_3557,portadatain_unconnected_wire_3558,portadatain_unconnected_wire_3559,portadatain_unconnected_wire_3560,portadatain_unconnected_wire_3561, portadatain_unconnected_wire_3562,portadatain_unconnected_wire_3563,portadatain_unconnected_wire_3564,portadatain_unconnected_wire_3565,portadatain_unconnected_wire_3566,\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[8] }), .portaaddr({portaaddr_unconnected_wire_3567,portaaddr_unconnected_wire_3568,portaaddr_unconnected_wire_3569,portaaddr_unconnected_wire_3570,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3571,portbaddr_unconnected_wire_3572,portbaddr_unconnected_wire_3573,portbaddr_unconnected_wire_3574, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[59] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59 .first_bit_number = 59; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama59 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][59]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[59] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][59] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][59]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][59]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3575,portadatain_unconnected_wire_3576,portadatain_unconnected_wire_3577,portadatain_unconnected_wire_3578,portadatain_unconnected_wire_3579,portadatain_unconnected_wire_3580,portadatain_unconnected_wire_3581, portadatain_unconnected_wire_3582,portadatain_unconnected_wire_3583,portadatain_unconnected_wire_3584,portadatain_unconnected_wire_3585,portadatain_unconnected_wire_3586,portadatain_unconnected_wire_3587,portadatain_unconnected_wire_3588, portadatain_unconnected_wire_3589,portadatain_unconnected_wire_3590,portadatain_unconnected_wire_3591,portadatain_unconnected_wire_3592,portadatain_unconnected_wire_3593,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][43] }), .portaaddr({portaaddr_unconnected_wire_3594,portaaddr_unconnected_wire_3595,portaaddr_unconnected_wire_3596,portaaddr_unconnected_wire_3597,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3598,portbaddr_unconnected_wire_3599,portbaddr_unconnected_wire_3600,portbaddr_unconnected_wire_3601, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[43] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43 .first_bit_number = 43; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama43 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][43]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[43] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][43] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][43]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][43]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3602,portadatain_unconnected_wire_3603,portadatain_unconnected_wire_3604,portadatain_unconnected_wire_3605,portadatain_unconnected_wire_3606,portadatain_unconnected_wire_3607,portadatain_unconnected_wire_3608, portadatain_unconnected_wire_3609,portadatain_unconnected_wire_3610,portadatain_unconnected_wire_3611,portadatain_unconnected_wire_3612,portadatain_unconnected_wire_3613,portadatain_unconnected_wire_3614,portadatain_unconnected_wire_3615, portadatain_unconnected_wire_3616,portadatain_unconnected_wire_3617,portadatain_unconnected_wire_3618,portadatain_unconnected_wire_3619,portadatain_unconnected_wire_3620,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][11] }), .portaaddr({portaaddr_unconnected_wire_3621,portaaddr_unconnected_wire_3622,portaaddr_unconnected_wire_3623,portaaddr_unconnected_wire_3624,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3625,portbaddr_unconnected_wire_3626,portbaddr_unconnected_wire_3627,portbaddr_unconnected_wire_3628, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[11] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11 .first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama11 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux33~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][43] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][11] ), .combout(\fp_pow_0002:fp_pow_inst|Mux33~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux33~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux33~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux33~0_I .lut_mask = "00A000A00AAA0AAA"; cyclonev_lcell_comb \rtl~305_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][27] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][59] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux33~0 ), .combout(\rtl~305 )); defparam \rtl~305_I .shared_arith = "off"; defparam \rtl~305_I .extended_lut = "off"; defparam \rtl~305_I .lut_mask = "024602468ACE8ACE"; cyclonev_lcell_comb \rtl~306_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datad(\__ALT_INV__rtl~304 ), .dataf(\__ALT_INV__rtl~305 ), .combout(\rtl~306 )); defparam \rtl~306_I .shared_arith = "off"; defparam \rtl~306_I .extended_lut = "off"; defparam \rtl~306_I .lut_mask = "000A000AF0FAF0FA"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[59]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~306 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[59] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[59]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[59]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3629,portadatain_unconnected_wire_3630,portadatain_unconnected_wire_3631,portadatain_unconnected_wire_3632,portadatain_unconnected_wire_3633,portadatain_unconnected_wire_3634,portadatain_unconnected_wire_3635, portadatain_unconnected_wire_3636,portadatain_unconnected_wire_3637,portadatain_unconnected_wire_3638,portadatain_unconnected_wire_3639,portadatain_unconnected_wire_3640,portadatain_unconnected_wire_3641,portadatain_unconnected_wire_3642, portadatain_unconnected_wire_3643,portadatain_unconnected_wire_3644,portadatain_unconnected_wire_3645,portadatain_unconnected_wire_3646,portadatain_unconnected_wire_3647,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][47] }), .portaaddr({portaaddr_unconnected_wire_3648,portaaddr_unconnected_wire_3649,portaaddr_unconnected_wire_3650,portaaddr_unconnected_wire_3651,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3652,portbaddr_unconnected_wire_3653,portbaddr_unconnected_wire_3654,portbaddr_unconnected_wire_3655, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[47] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47 .first_bit_number = 47; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama47 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][47]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[47] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][47] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][47]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][47]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3656,portadatain_unconnected_wire_3657,portadatain_unconnected_wire_3658,portadatain_unconnected_wire_3659,portadatain_unconnected_wire_3660,portadatain_unconnected_wire_3661,portadatain_unconnected_wire_3662, portadatain_unconnected_wire_3663,portadatain_unconnected_wire_3664,portadatain_unconnected_wire_3665,portadatain_unconnected_wire_3666,portadatain_unconnected_wire_3667,portadatain_unconnected_wire_3668,portadatain_unconnected_wire_3669, portadatain_unconnected_wire_3670,portadatain_unconnected_wire_3671,portadatain_unconnected_wire_3672,portadatain_unconnected_wire_3673,portadatain_unconnected_wire_3674,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][15] }), .portaaddr({portaaddr_unconnected_wire_3675,portaaddr_unconnected_wire_3676,portaaddr_unconnected_wire_3677,portaaddr_unconnected_wire_3678,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3679,portbaddr_unconnected_wire_3680,portbaddr_unconnected_wire_3681,portbaddr_unconnected_wire_3682, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[15] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15 .first_bit_number = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama15 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux29~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][47] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][15] ), .combout(\fp_pow_0002:fp_pow_inst|Mux29~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux29~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux29~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux29~0_I .lut_mask = "00A000A00AAA0AAA"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3683,portadatain_unconnected_wire_3684,portadatain_unconnected_wire_3685,portadatain_unconnected_wire_3686,portadatain_unconnected_wire_3687,portadatain_unconnected_wire_3688,portadatain_unconnected_wire_3689, portadatain_unconnected_wire_3690,portadatain_unconnected_wire_3691,portadatain_unconnected_wire_3692,portadatain_unconnected_wire_3693,portadatain_unconnected_wire_3694,portadatain_unconnected_wire_3695,portadatain_unconnected_wire_3696, portadatain_unconnected_wire_3697,portadatain_unconnected_wire_3698,portadatain_unconnected_wire_3699,portadatain_unconnected_wire_3700,portadatain_unconnected_wire_3701,\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[12] }), .portaaddr({portaaddr_unconnected_wire_3702,portaaddr_unconnected_wire_3703,portaaddr_unconnected_wire_3704,portaaddr_unconnected_wire_3705,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3706,portbaddr_unconnected_wire_3707,portbaddr_unconnected_wire_3708,portbaddr_unconnected_wire_3709, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[63] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63 .first_bit_number = 63; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama63 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][63]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[63] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][63] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][63]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][63]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3710,portadatain_unconnected_wire_3711,portadatain_unconnected_wire_3712,portadatain_unconnected_wire_3713,portadatain_unconnected_wire_3714,portadatain_unconnected_wire_3715,portadatain_unconnected_wire_3716, portadatain_unconnected_wire_3717,portadatain_unconnected_wire_3718,portadatain_unconnected_wire_3719,portadatain_unconnected_wire_3720,portadatain_unconnected_wire_3721,portadatain_unconnected_wire_3722,portadatain_unconnected_wire_3723, portadatain_unconnected_wire_3724,portadatain_unconnected_wire_3725,portadatain_unconnected_wire_3726,portadatain_unconnected_wire_3727,portadatain_unconnected_wire_3728,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][31] }), .portaaddr({portaaddr_unconnected_wire_3729,portaaddr_unconnected_wire_3730,portaaddr_unconnected_wire_3731,portaaddr_unconnected_wire_3732,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3733,portbaddr_unconnected_wire_3734,portbaddr_unconnected_wire_3735,portbaddr_unconnected_wire_3736, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[31] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31 .first_bit_number = 31; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama31 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[31] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~302_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60]~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux29~0 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][63] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][31] ), .combout(\rtl~302 )); defparam \rtl~302_I .shared_arith = "off"; defparam \rtl~302_I .extended_lut = "off"; defparam \rtl~302_I .lut_mask = "084C084C2A6E2A6E"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3737,portadatain_unconnected_wire_3738,portadatain_unconnected_wire_3739,portadatain_unconnected_wire_3740,portadatain_unconnected_wire_3741,portadatain_unconnected_wire_3742,portadatain_unconnected_wire_3743, portadatain_unconnected_wire_3744,portadatain_unconnected_wire_3745,portadatain_unconnected_wire_3746,portadatain_unconnected_wire_3747,portadatain_unconnected_wire_3748,portadatain_unconnected_wire_3749,portadatain_unconnected_wire_3750, portadatain_unconnected_wire_3751,portadatain_unconnected_wire_3752,portadatain_unconnected_wire_3753,portadatain_unconnected_wire_3754,portadatain_unconnected_wire_3755,\fp_pow_0002:fp_pow_inst|finalSumAbsLog_uid77_fpPowrTest_p2_of_2_o[4] }), .portaaddr({portaaddr_unconnected_wire_3756,portaaddr_unconnected_wire_3757,portaaddr_unconnected_wire_3758,portaaddr_unconnected_wire_3759,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3760,portbaddr_unconnected_wire_3761,portbaddr_unconnected_wire_3762,portbaddr_unconnected_wire_3763, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[55] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55 .first_bit_number = 55; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama55 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][55]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[55] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][55] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][55]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][55]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3764,portadatain_unconnected_wire_3765,portadatain_unconnected_wire_3766,portadatain_unconnected_wire_3767,portadatain_unconnected_wire_3768,portadatain_unconnected_wire_3769,portadatain_unconnected_wire_3770, portadatain_unconnected_wire_3771,portadatain_unconnected_wire_3772,portadatain_unconnected_wire_3773,portadatain_unconnected_wire_3774,portadatain_unconnected_wire_3775,portadatain_unconnected_wire_3776,portadatain_unconnected_wire_3777, portadatain_unconnected_wire_3778,portadatain_unconnected_wire_3779,portadatain_unconnected_wire_3780,portadatain_unconnected_wire_3781,portadatain_unconnected_wire_3782,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][39] }), .portaaddr({portaaddr_unconnected_wire_3783,portaaddr_unconnected_wire_3784,portaaddr_unconnected_wire_3785,portaaddr_unconnected_wire_3786,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3787,portbaddr_unconnected_wire_3788,portbaddr_unconnected_wire_3789,portbaddr_unconnected_wire_3790, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[39] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39 .first_bit_number = 39; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama39 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][39]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[39] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][39] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][39]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3791,portadatain_unconnected_wire_3792,portadatain_unconnected_wire_3793,portadatain_unconnected_wire_3794,portadatain_unconnected_wire_3795,portadatain_unconnected_wire_3796,portadatain_unconnected_wire_3797, portadatain_unconnected_wire_3798,portadatain_unconnected_wire_3799,portadatain_unconnected_wire_3800,portadatain_unconnected_wire_3801,portadatain_unconnected_wire_3802,portadatain_unconnected_wire_3803,portadatain_unconnected_wire_3804, portadatain_unconnected_wire_3805,portadatain_unconnected_wire_3806,portadatain_unconnected_wire_3807,portadatain_unconnected_wire_3808,portadatain_unconnected_wire_3809,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][7] }), .portaaddr({portaaddr_unconnected_wire_3810,portaaddr_unconnected_wire_3811,portaaddr_unconnected_wire_3812,portaaddr_unconnected_wire_3813,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3814,portbaddr_unconnected_wire_3815,portbaddr_unconnected_wire_3816,portbaddr_unconnected_wire_3817, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[7] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7 .first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama7 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3818,portadatain_unconnected_wire_3819,portadatain_unconnected_wire_3820,portadatain_unconnected_wire_3821,portadatain_unconnected_wire_3822,portadatain_unconnected_wire_3823,portadatain_unconnected_wire_3824, portadatain_unconnected_wire_3825,portadatain_unconnected_wire_3826,portadatain_unconnected_wire_3827,portadatain_unconnected_wire_3828,portadatain_unconnected_wire_3829,portadatain_unconnected_wire_3830,portadatain_unconnected_wire_3831, portadatain_unconnected_wire_3832,portadatain_unconnected_wire_3833,portadatain_unconnected_wire_3834,portadatain_unconnected_wire_3835,portadatain_unconnected_wire_3836,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][23] }), .portaaddr({portaaddr_unconnected_wire_3837,portaaddr_unconnected_wire_3838,portaaddr_unconnected_wire_3839,portaaddr_unconnected_wire_3840,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3841,portbaddr_unconnected_wire_3842,portbaddr_unconnected_wire_3843,portbaddr_unconnected_wire_3844, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[23] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23 .first_bit_number = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama23 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[23] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~301_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][55] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][39] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][7] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][23] ), .combout(\rtl~301 )); defparam \rtl~301_I .shared_arith = "off"; defparam \rtl~301_I .extended_lut = "off"; defparam \rtl~301_I .lut_mask = "082A193B4C6E5D7F"; cyclonev_lcell_comb \rtl~303_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datad(\__ALT_INV__rtl~302 ), .dataf(\__ALT_INV__rtl~301 ), .combout(\rtl~303 )); defparam \rtl~303_I .shared_arith = "off"; defparam \rtl~303_I .extended_lut = "off"; defparam \rtl~303_I .lut_mask = "00AA00AA50FA50FA"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[63]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~303 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[63] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[63]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[63]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~146_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[65] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[61] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[59] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[63] ), .combout(\rtl~146 )); defparam \rtl~146_I .shared_arith = "off"; defparam \rtl~146_I .extended_lut = "off"; defparam \rtl~146_I .lut_mask = "207025752A7A2F7F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|expFracConc_uid87_fpPowrTest_q[33]~0_I ( .datab(\__ALT_INV__rtl~147 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~146 ), .combout(\fp_pow_0002:fp_pow_inst|expFracConc_uid87_fpPowrTest_q[33]~0 )); defparam \fp_pow_0002:fp_pow_inst|expFracConc_uid87_fpPowrTest_q[33]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|expFracConc_uid87_fpPowrTest_q[33]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|expFracConc_uid87_fpPowrTest_q[33]~0_I .lut_mask = "03030303F3F3F3F3"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|expFracConc_uid87_fpPowrTest_q[33]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][33]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3845,portadatain_unconnected_wire_3846,portadatain_unconnected_wire_3847,portadatain_unconnected_wire_3848,portadatain_unconnected_wire_3849,portadatain_unconnected_wire_3850,portadatain_unconnected_wire_3851, portadatain_unconnected_wire_3852,portadatain_unconnected_wire_3853,portadatain_unconnected_wire_3854,portadatain_unconnected_wire_3855,portadatain_unconnected_wire_3856,portadatain_unconnected_wire_3857,portadatain_unconnected_wire_3858, portadatain_unconnected_wire_3859,portadatain_unconnected_wire_3860,portadatain_unconnected_wire_3861,portadatain_unconnected_wire_3862,portadatain_unconnected_wire_3863,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][1] }), .portaaddr({portaaddr_unconnected_wire_3864,portaaddr_unconnected_wire_3865,portaaddr_unconnected_wire_3866,portaaddr_unconnected_wire_3867,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3868,portbaddr_unconnected_wire_3869,portbaddr_unconnected_wire_3870,portbaddr_unconnected_wire_3871, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[1] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1 .first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama1 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~307_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][33] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~307 )); defparam \rtl~307_I .shared_arith = "off"; defparam \rtl~307_I .extended_lut = "off"; defparam \rtl~307_I .lut_mask = "082A082A082A082A"; cyclonev_lcell_comb \rtl~237_I ( .dataa(\__ALT_INV__rtl~307 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux35~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux27~0 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux19~0 ), .combout(\rtl~237 )); defparam \rtl~237_I .shared_arith = "off"; defparam \rtl~237_I .extended_lut = "off"; defparam \rtl~237_I .lut_mask = "030311DDCFCF11DD"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[57]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~237 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[57] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[57]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[57]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~201_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[57] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[61] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[59] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[63] ), .combout(\rtl~201 )); defparam \rtl~201_I .shared_arith = "off"; defparam \rtl~201_I .extended_lut = "off"; defparam \rtl~201_I .lut_mask = "00330F55FF330F55"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~147 ), .asdata(\rtl~201 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][32]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist9_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3872,portadatain_unconnected_wire_3873,portadatain_unconnected_wire_3874,portadatain_unconnected_wire_3875,portadatain_unconnected_wire_3876,portadatain_unconnected_wire_3877,portadatain_unconnected_wire_3878, portadatain_unconnected_wire_3879,portadatain_unconnected_wire_3880,portadatain_unconnected_wire_3881,portadatain_unconnected_wire_3882,portadatain_unconnected_wire_3883,portadatain_unconnected_wire_3884,portadatain_unconnected_wire_3885, portadatain_unconnected_wire_3886,portadatain_unconnected_wire_3887,portadatain_unconnected_wire_3888,portadatain_unconnected_wire_3889,portadatain_unconnected_wire_3890,\fp_pow_0002:fp_pow_inst|dspba_delay:redist10|delay_signals[0][0]~DUPLICATE }), .portaaddr({portaaddr_unconnected_wire_3891,portaaddr_unconnected_wire_3892,portaaddr_unconnected_wire_3893,portaaddr_unconnected_wire_3894,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3895,portbaddr_unconnected_wire_3896,portbaddr_unconnected_wire_3897,portbaddr_unconnected_wire_3898, \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0 .logical_ram_width = 67; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~308_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][32] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .combout(\rtl~308 )); defparam \rtl~308_I .shared_arith = "off"; defparam \rtl~308_I .extended_lut = "off"; defparam \rtl~308_I .lut_mask = "0A0A0A0A00AA00AA"; cyclonev_lcell_comb \rtl~252_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux20~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux28~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux36~0 ), .dataf(\__ALT_INV__rtl~308 ), .combout(\rtl~252 )); defparam \rtl~252_I .shared_arith = "off"; defparam \rtl~252_I .extended_lut = "off"; defparam \rtl~252_I .lut_mask = "082A4C6E193B5D7F"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[56]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~252 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[56] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[56]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[56]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~214_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[58] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[56] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[62] ), .combout(\rtl~214 )); defparam \rtl~214_I .shared_arith = "off"; defparam \rtl~214_I .extended_lut = "off"; defparam \rtl~214_I .lut_mask = "0350035FF350F35F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~201 ), .asdata(\rtl~214 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux37~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][7] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][39] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Mux37~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux37~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux37~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux37~0_I .lut_mask = "05F505F500000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux45~0_I ( .dataa(\__ALT_INV__rtl~288 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][31] ), .combout(\fp_pow_0002:fp_pow_inst|Mux45~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux45~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux45~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux45~0_I .lut_mask = "1111111111111111"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux21~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][23] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][55] ), .combout(\fp_pow_0002:fp_pow_inst|Mux21~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux21~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux21~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux21~0_I .lut_mask = "028A028A028A028A"; cyclonev_lcell_comb \rtl~251_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux37~0 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux45~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux21~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux29~0 ), .combout(\rtl~251 )); defparam \rtl~251_I .shared_arith = "off"; defparam \rtl~251_I .extended_lut = "off"; defparam \rtl~251_I .lut_mask = "0407C4C73437F4F7"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[55]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~251 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[55] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[55]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[55]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~213_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[61] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[57] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[55] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[59] ), .combout(\rtl~213 )); defparam \rtl~213_I .shared_arith = "off"; defparam \rtl~213_I .extended_lut = "off"; defparam \rtl~213_I .lut_mask = "2700275527AA27FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~214 ), .asdata(\rtl~213 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux46~0_I ( .dataa(\__ALT_INV__rtl~288 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][30] ), .combout(\fp_pow_0002:fp_pow_inst|Mux46~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux46~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux46~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux46~0_I .lut_mask = "0000555500005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux38~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][6] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][38] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Mux38~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux38~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux38~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux38~0_I .lut_mask = "0000AAAA0A0A0A0A"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux22~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][22] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][54] ), .combout(\fp_pow_0002:fp_pow_inst|Mux22~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux22~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux22~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux22~0_I .lut_mask = "028A028A028A028A"; cyclonev_lcell_comb \rtl~250_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux46~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux38~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux22~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux30~0 ), .combout(\rtl~250 )); defparam \rtl~250_I .shared_arith = "off"; defparam \rtl~250_I .extended_lut = "off"; defparam \rtl~250_I .lut_mask = "012389AB4567CDEF"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[54]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~250 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[54] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[54]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[54]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~212_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[54] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[56] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[60] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[58] ), .combout(\rtl~212 )); defparam \rtl~212_I .shared_arith = "off"; defparam \rtl~212_I .extended_lut = "off"; defparam \rtl~212_I .lut_mask = "010DC1CD313DF1FD"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~213 ), .asdata(\rtl~212 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux23~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][21] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][53] ), .combout(\fp_pow_0002:fp_pow_inst|Mux23~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux23~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux23~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux23~0_I .lut_mask = "048C048C048C048C"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux47~0_I ( .datac(\__ALT_INV__rtl~288 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][29] ), .combout(\fp_pow_0002:fp_pow_inst|Mux47~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux47~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux47~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux47~0_I .lut_mask = "000000000F0F0F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux39~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][37] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Mux39~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux39~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux39~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux39~0_I .lut_mask = "05F505F500000000"; cyclonev_lcell_comb \rtl~249_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux23~0 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux47~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux39~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux31~0 ), .combout(\rtl~249 )); defparam \rtl~249_I .shared_arith = "off"; defparam \rtl~249_I .extended_lut = "off"; defparam \rtl~249_I .lut_mask = "40434C4F70737C7F"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[53]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~249 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[53] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[53]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[53]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~211_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[59] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[55] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[53] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[57] ), .combout(\rtl~211 )); defparam \rtl~211_I .shared_arith = "off"; defparam \rtl~211_I .extended_lut = "off"; defparam \rtl~211_I .lut_mask = "44440C3F77770C3F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~212 ), .asdata(\rtl~211 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux48~0_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][28] ), .dataf(\__ALT_INV__rtl~288 ), .combout(\fp_pow_0002:fp_pow_inst|Mux48~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux48~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux48~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux48~0_I .lut_mask = "0000000000FF00FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux24~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][20] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][52] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Mux24~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux24~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux24~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux24~0_I .lut_mask = "05AF05AF00000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux40~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][36] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Mux40~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux40~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux40~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux40~0_I .lut_mask = "05F505F500000000"; cyclonev_lcell_comb \rtl~248_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux32~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux48~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux24~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux40~0 ), .combout(\rtl~248 )); defparam \rtl~248_I .shared_arith = "off"; defparam \rtl~248_I .extended_lut = "off"; defparam \rtl~248_I .lut_mask = "1015B0B51A1FBABF"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[52]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~248 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[52] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[52]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[52]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~210_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[52] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[54] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[56] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[58] ), .combout(\rtl~210 )); defparam \rtl~210_I .shared_arith = "off"; defparam \rtl~210_I .extended_lut = "off"; defparam \rtl~210_I .lut_mask = "051105BBAF11AFBB"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~211 ), .asdata(\rtl~210 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux25~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][51] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][19] ), .combout(\fp_pow_0002:fp_pow_inst|Mux25~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux25~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux25~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux25~0_I .lut_mask = "0088008822AA22AA"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux41~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][35] ), .combout(\fp_pow_0002:fp_pow_inst|Mux41~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux41~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux41~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux41~0_I .lut_mask = "10B010B010B010B0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux49~0_I ( .datac(\__ALT_INV__rtl~288 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][27] ), .combout(\fp_pow_0002:fp_pow_inst|Mux49~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux49~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux49~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux49~0_I .lut_mask = "000000000F0F0F0F"; cyclonev_lcell_comb \rtl~238_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux25~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux41~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux49~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux33~0 ), .combout(\rtl~238 )); defparam \rtl~238_I .shared_arith = "off"; defparam \rtl~238_I .extended_lut = "off"; defparam \rtl~238_I .lut_mask = "084C195D2A6E3B7F"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[51]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~238 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[51] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[51]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[51]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~209_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[53] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[55] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[51] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[57] ), .combout(\rtl~209 )); defparam \rtl~209_I .shared_arith = "off"; defparam \rtl~209_I .extended_lut = "off"; defparam \rtl~209_I .lut_mask = "03034477CFCF4477"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~210 ), .asdata(\rtl~209 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux42~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][34] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Mux42~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux42~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux42~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux42~0_I .lut_mask = "00AA00AA0A0A0A0A"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux26~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist65|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist61|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][50] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][18]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Mux26~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux26~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux26~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux26~0_I .lut_mask = "0088008822AA22AA"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux50~0_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][26] ), .datad(\__ALT_INV__rtl~288 ), .combout(\fp_pow_0002:fp_pow_inst|Mux50~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux50~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux50~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux50~0_I .lut_mask = "000F000F000F000F"; cyclonev_lcell_comb \rtl~242_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux34~0 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux42~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux26~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux50~0 ), .combout(\rtl~242 )); defparam \rtl~242_I .shared_arith = "off"; defparam \rtl~242_I .extended_lut = "off"; defparam \rtl~242_I .lut_mask = "101CD0DC131FD3DF"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[50]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~242 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[50] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[50]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[50]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~208_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[54] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[50] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[56] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[52] ), .combout(\rtl~208 )); defparam \rtl~208_I .shared_arith = "off"; defparam \rtl~208_I .extended_lut = "off"; defparam \rtl~208_I .lut_mask = "02138A9B4657CEDF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~209 ), .asdata(\rtl~208 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux51~0_I ( .datac(\__ALT_INV__rtl~288 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][25] ), .combout(\fp_pow_0002:fp_pow_inst|Mux51~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux51~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux51~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux51~0_I .lut_mask = "000000000F0F0F0F"; cyclonev_lcell_comb \rtl~240_I ( .dataa(\__ALT_INV__rtl~307 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux35~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux27~0 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux51~0 ), .combout(\rtl~240 )); defparam \rtl~240_I .shared_arith = "off"; defparam \rtl~240_I .extended_lut = "off"; defparam \rtl~240_I .lut_mask = "11DD0C0C11DD3F3F"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[49]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~240 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[49] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[49]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[49]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~207_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[49] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[51] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[55] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[53] ), .combout(\rtl~207 )); defparam \rtl~207_I .shared_arith = "off"; defparam \rtl~207_I .extended_lut = "off"; defparam \rtl~207_I .lut_mask = "010DC1CD313DF1FD"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~208 ), .asdata(\rtl~207 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux52~0_I ( .dataa(\__ALT_INV__rtl~288 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][24] ), .combout(\fp_pow_0002:fp_pow_inst|Mux52~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux52~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux52~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux52~0_I .lut_mask = "0000555500005555"; cyclonev_lcell_comb \rtl~246_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux52~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux28~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux36~0 ), .dataf(\__ALT_INV__rtl~308 ), .combout(\rtl~246 )); defparam \rtl~246_I .shared_arith = "off"; defparam \rtl~246_I .extended_lut = "off"; defparam \rtl~246_I .lut_mask = "01A151F10BAB5BFB"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[48]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~246 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[48] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[48]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[48]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~206_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[54] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[52] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[48] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[50] ), .combout(\rtl~206 )); defparam \rtl~206_I .shared_arith = "off"; defparam \rtl~206_I .extended_lut = "off"; defparam \rtl~206_I .lut_mask = "220A225F770A775F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~207 ), .asdata(\rtl~206 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux53~0_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][23] ), .dataf(\__ALT_INV__rtl~288 ), .combout(\fp_pow_0002:fp_pow_inst|Mux53~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux53~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux53~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux53~0_I .lut_mask = "0000000000FF00FF"; cyclonev_lcell_comb \rtl~239_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux37~0 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux53~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux45~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux29~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .combout(\rtl~239 )); defparam \rtl~239_I .shared_arith = "off"; defparam \rtl~239_I .extended_lut = "off"; defparam \rtl~239_I .lut_mask = "1111DDDD03CF03CF"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[47]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~239 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[47] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[47]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[47]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~205_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[51] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[53] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[49] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[47] ), .combout(\rtl~205 )); defparam \rtl~205_I .shared_arith = "off"; defparam \rtl~205_I .extended_lut = "off"; defparam \rtl~205_I .lut_mask = "10D01CDC13D31FDF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~206 ), .asdata(\rtl~205 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux54~0_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][22] ), .datad(\__ALT_INV__rtl~288 ), .combout(\fp_pow_0002:fp_pow_inst|Mux54~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux54~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux54~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux54~0_I .lut_mask = "000F000F000F000F"; cyclonev_lcell_comb \rtl~243_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux46~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux38~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux54~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux30~0 ), .combout(\rtl~243 )); defparam \rtl~243_I .shared_arith = "off"; defparam \rtl~243_I .extended_lut = "off"; defparam \rtl~243_I .lut_mask = "024613578ACE9BDF"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[46]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~243 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[46] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[46]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[46]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~204_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[46] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[50] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[48] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[52] ), .combout(\rtl~204 )); defparam \rtl~204_I .shared_arith = "off"; defparam \rtl~204_I .extended_lut = "off"; defparam \rtl~204_I .lut_mask = "001B551BAA1BFF1B"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~205 ), .asdata(\rtl~204 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux55~0_I ( .datac(\__ALT_INV__rtl~288 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][21] ), .combout(\fp_pow_0002:fp_pow_inst|Mux55~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux55~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux55~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux55~0_I .lut_mask = "000000000F0F0F0F"; cyclonev_lcell_comb \rtl~241_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux47~0 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux39~0 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux55~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux31~0 ), .combout(\rtl~241 )); defparam \rtl~241_I .shared_arith = "off"; defparam \rtl~241_I .extended_lut = "off"; defparam \rtl~241_I .lut_mask = "03440377CF44CF77"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[45]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~241 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[45] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[45]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[45]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~202_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[51] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[45] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[49] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[47] ), .combout(\rtl~202 )); defparam \rtl~202_I .shared_arith = "off"; defparam \rtl~202_I .extended_lut = "off"; defparam \rtl~202_I .lut_mask = "08192A3B4C5D6E7F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~204 ), .asdata(\rtl~202 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux56~0_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][20] ), .dataf(\__ALT_INV__rtl~288 ), .combout(\fp_pow_0002:fp_pow_inst|Mux56~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux56~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux56~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux56~0_I .lut_mask = "0000000033333333"; cyclonev_lcell_comb \rtl~247_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux48~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux40~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux56~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux32~0 ), .combout(\rtl~247 )); defparam \rtl~247_I .shared_arith = "off"; defparam \rtl~247_I .extended_lut = "off"; defparam \rtl~247_I .lut_mask = "02520757A2F2A7F7"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[44]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~247 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[44] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[44]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[44]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~203_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[46] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[44] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[48] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[50] ), .combout(\rtl~203 )); defparam \rtl~203_I .shared_arith = "off"; defparam \rtl~203_I .extended_lut = "off"; defparam \rtl~203_I .lut_mask = "110511AFBB05BBAF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~202 ), .asdata(\rtl~203 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux57~0_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][19] ), .dataf(\__ALT_INV__rtl~288 ), .combout(\fp_pow_0002:fp_pow_inst|Mux57~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux57~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux57~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux57~0_I .lut_mask = "0000000000FF00FF"; cyclonev_lcell_comb \rtl~272_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux33~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux57~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux49~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux41~0 ), .combout(\rtl~272 )); defparam \rtl~272_I .shared_arith = "off"; defparam \rtl~272_I .extended_lut = "off"; defparam \rtl~272_I .lut_mask = "08194C5D2A3B6E7F"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[43]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~272 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[43] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[43]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[43]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~233_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[43] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[45] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[49] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[47] ), .combout(\rtl~233 )); defparam \rtl~233_I .shared_arith = "off"; defparam \rtl~233_I .extended_lut = "off"; defparam \rtl~233_I .lut_mask = "010DC1CD313DF1FD"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~203 ), .asdata(\rtl~233 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux58~0_I ( .datab(\__ALT_INV__rtl~288 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][18] ), .combout(\fp_pow_0002:fp_pow_inst|Mux58~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux58~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux58~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux58~0_I .lut_mask = "0000000033333333"; cyclonev_lcell_comb \rtl~271_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux58~0 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux50~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux34~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux42~0 ), .combout(\rtl~271 )); defparam \rtl~271_I .shared_arith = "off"; defparam \rtl~271_I .extended_lut = "off"; defparam \rtl~271_I .lut_mask = "010DC1CD313DF1FD"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[42]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~271 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[42] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[42]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~232_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[46] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[44] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[48] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[42] ), .combout(\rtl~232 )); defparam \rtl~232_I .shared_arith = "off"; defparam \rtl~232_I .extended_lut = "off"; defparam \rtl~232_I .lut_mask = "0522AF220577AF77"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~233 ), .asdata(\rtl~232 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux59~0_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][17] ), .datad(\__ALT_INV__rtl~288 ), .combout(\fp_pow_0002:fp_pow_inst|Mux59~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux59~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux59~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux59~0_I .lut_mask = "000F000F000F000F"; cyclonev_lcell_comb \rtl~270_I ( .dataa(\__ALT_INV__rtl~307 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux59~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux35~0 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux51~0 ), .combout(\rtl~270 )); defparam \rtl~270_I .shared_arith = "off"; defparam \rtl~270_I .extended_lut = "off"; defparam \rtl~270_I .lut_mask = "0F0055330FFF5533"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[41]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~270 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[41] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[41]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~231_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[43] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[45] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[47] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[41] ), .combout(\rtl~231 )); defparam \rtl~231_I .shared_arith = "off"; defparam \rtl~231_I .extended_lut = "off"; defparam \rtl~231_I .lut_mask = "0F5533000F5533FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~232 ), .asdata(\rtl~231 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][16]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][16]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][16]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][16]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][16]~DUPLICATE_I .created_from = "Q(delay_signals[0][16])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux60~0_I ( .datae(\__ALT_INV__rtl~288 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][16]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Mux60~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux60~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux60~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux60~0_I .lut_mask = "000000000000FFFF"; cyclonev_lcell_comb \rtl~269_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux52~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux60~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux36~0 ), .dataf(\__ALT_INV__rtl~308 ), .combout(\rtl~269 )); defparam \rtl~269_I .shared_arith = "off"; defparam \rtl~269_I .extended_lut = "off"; defparam \rtl~269_I .lut_mask = "0207A2A75257F2F7"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[40]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~269 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[40] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[40]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~230_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[46] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[44] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[40] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[42] ), .combout(\rtl~230 )); defparam \rtl~230_I .shared_arith = "off"; defparam \rtl~230_I .extended_lut = "off"; defparam \rtl~230_I .lut_mask = "220A225F770A775F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~231 ), .asdata(\rtl~230 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~311_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datac(\__ALT_INV__rtl~288 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][15] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][31] ), .combout(\rtl~311 )); defparam \rtl~311_I .shared_arith = "off"; defparam \rtl~311_I .extended_lut = "off"; defparam \rtl~311_I .lut_mask = "000300030C0F0C0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux102~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux53~0 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datac(\__ALT_INV__rtl~311 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux37~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Mux102~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux102~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux102~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux102~0_I .lut_mask = "11DD11DD0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[39]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux102~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[39] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[39]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~229_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[45] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[39] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[41] ), .combout(\rtl~229 )); defparam \rtl~229_I .shared_arith = "off"; defparam \rtl~229_I .extended_lut = "off"; defparam \rtl~229_I .lut_mask = "5030503F5F305F3F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~230 ), .asdata(\rtl~229 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~314_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][30] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][14] ), .dataf(\__ALT_INV__rtl~288 ), .combout(\rtl~314 )); defparam \rtl~314_I .shared_arith = "off"; defparam \rtl~314_I .extended_lut = "off"; defparam \rtl~314_I .lut_mask = "000000000A5F0A5F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux103~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datab(\__ALT_INV__rtl~314 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux54~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux38~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux103~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux103~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux103~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux103~0_I .lut_mask = "03530353A3F3A3F3"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[38]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux103~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[38] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[38]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~228_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[40] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[38] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[44] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[42] ), .combout(\rtl~228 )); defparam \rtl~228_I .shared_arith = "off"; defparam \rtl~228_I .extended_lut = "off"; defparam \rtl~228_I .lut_mask = "1105BB0511AFBBAF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~229 ), .asdata(\rtl~228 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~310_I ( .datab(\__ALT_INV__rtl~288 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][29] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][13] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .combout(\rtl~310 )); defparam \rtl~310_I .shared_arith = "off"; defparam \rtl~310_I .extended_lut = "off"; defparam \rtl~310_I .lut_mask = "0303030300330033"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux104~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux39~0 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux55~0 ), .dataf(\__ALT_INV__rtl~310 ), .combout(\fp_pow_0002:fp_pow_inst|Mux104~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux104~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux104~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux104~0_I .lut_mask = "40404C4C73737F7F"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux104~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[37] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[37]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~227_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[37] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[39] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[41] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[43] ), .combout(\rtl~227 )); defparam \rtl~227_I .shared_arith = "off"; defparam \rtl~227_I .extended_lut = "off"; defparam \rtl~227_I .lut_mask = "000F3355FF0F3355"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~228 ), .asdata(\rtl~227 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~313_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][28] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][12] ), .dataf(\__ALT_INV__rtl~288 ), .combout(\rtl~313 )); defparam \rtl~313_I .shared_arith = "off"; defparam \rtl~313_I .extended_lut = "off"; defparam \rtl~313_I .lut_mask = "00000000505F505F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux105~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux40~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux56~0 ), .dataf(\__ALT_INV__rtl~313 ), .combout(\fp_pow_0002:fp_pow_inst|Mux105~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux105~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux105~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux105~0_I .lut_mask = "084C084C3B7F3B7F"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[36]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux105~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[36] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[36]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~226_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[38] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[42] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[40] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[36] ), .combout(\rtl~226 )); defparam \rtl~226_I .shared_arith = "off"; defparam \rtl~226_I .extended_lut = "off"; defparam \rtl~226_I .lut_mask = "048C26AE159D37BF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~227 ), .asdata(\rtl~226 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~312_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datac(\__ALT_INV__rtl~288 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][11] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][27] ), .combout(\rtl~312 )); defparam \rtl~312_I .shared_arith = "off"; defparam \rtl~312_I .extended_lut = "off"; defparam \rtl~312_I .lut_mask = "000500050A0F0A0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux106~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux57~0 ), .datac(\__ALT_INV__rtl~312 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux41~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux106~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux106~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux106~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux106~0_I .lut_mask = "110F110FBB0FBB0F"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux106~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[35] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[35]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~225_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[37] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[35] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[39] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[41] ), .combout(\rtl~225 )); defparam \rtl~225_I .shared_arith = "off"; defparam \rtl~225_I .extended_lut = "off"; defparam \rtl~225_I .lut_mask = "050305F3F503F5F3"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~226 ), .asdata(\rtl~225 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~315_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][26] ), .datab(\__ALT_INV__rtl~288 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][10] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .combout(\rtl~315 )); defparam \rtl~315_I .shared_arith = "off"; defparam \rtl~315_I .extended_lut = "off"; defparam \rtl~315_I .lut_mask = "1111111100003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux107~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux58~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0] ), .datad(\__ALT_INV__rtl~315 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux42~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux107~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux107~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux107~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux107~0_I .lut_mask = "101F101FB0BFB0BF"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux107~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[34] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~224_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[36] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[38] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[34] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[40] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .combout(\rtl~224 )); defparam \rtl~224_I .shared_arith = "off"; defparam \rtl~224_I .extended_lut = "off"; defparam \rtl~224_I .lut_mask = "1111BBBB0A5F0A5F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~225 ), .asdata(\rtl~224 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~309_I ( .datab(\__ALT_INV__rtl~288 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][9] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][25] ), .combout(\rtl~309 )); defparam \rtl~309_I .shared_arith = "off"; defparam \rtl~309_I .extended_lut = "off"; defparam \rtl~309_I .lut_mask = "0003000330333033"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux108~0_I ( .dataa(\__ALT_INV__rtl~309 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux59~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~307 ), .combout(\fp_pow_0002:fp_pow_inst|Mux108~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux108~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux108~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux108~0_I .lut_mask = "05350535F535F535"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux108~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[33] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~223_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[33] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[37] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[39] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[35] ), .combout(\rtl~223 )); defparam \rtl~223_I .shared_arith = "off"; defparam \rtl~223_I .extended_lut = "off"; defparam \rtl~223_I .lut_mask = "001BAA1B551BFF1B"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~224 ), .asdata(\rtl~223 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux109~0_I ( .dataa(\__ALT_INV__rtl~288 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][24] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][16] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][8] ), .datag(\__ALT_INV__rtl~308 ), .combout(\fp_pow_0002:fp_pow_inst|Mux109~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux109~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux109~0_I .extended_lut = "on"; defparam \fp_pow_0002:fp_pow_inst|Mux109~0_I .lut_mask = "0C1D04040C1D1515"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux109~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[32] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~222_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[34] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[38] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[32] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[36] ), .combout(\rtl~222 )); defparam \rtl~222_I .shared_arith = "off"; defparam \rtl~222_I .extended_lut = "off"; defparam \rtl~222_I .lut_mask = "1B001B551BAA1BFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~223 ), .asdata(\rtl~222 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~3_I ( .datab(\__ALT_INV__rtl~288 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~3 )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~3_I .lut_mask = "00000000FCFCFCFC"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist56|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist58|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~288 ), .combout(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~2 )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~2_I .lut_mask = "5555555500550055"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux110~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][7] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~3 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~2 ), .datad(\__ALT_INV__rtl~311 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][23] ), .combout(\fp_pow_0002:fp_pow_inst|Mux110~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux110~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux110~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux110~0_I .lut_mask = "04C404C434F434F4"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux110~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[31] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~221_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[31] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[35] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[33] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[37] ), .combout(\rtl~221 )); defparam \rtl~221_I .shared_arith = "off"; defparam \rtl~221_I .extended_lut = "off"; defparam \rtl~221_I .lut_mask = "00350F35F035FF35"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~222 ), .asdata(\rtl~221 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux111~0_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~3 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~2 ), .datad(\__ALT_INV__rtl~314 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][22] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Mux111~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux111~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux111~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux111~0_I .lut_mask = "00C030F00CCC3CFC"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux111~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[30] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~220_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[34] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[30] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[32] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[36] ), .combout(\rtl~220 )); defparam \rtl~220_I .shared_arith = "off"; defparam \rtl~220_I .extended_lut = "off"; defparam \rtl~220_I .lut_mask = "00275527AA27FF27"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~221 ), .asdata(\rtl~220 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux112~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][5] ), .datab(\__ALT_INV__rtl~310 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~2 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~3 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][21] ), .combout(\fp_pow_0002:fp_pow_inst|Mux112~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux112~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux112~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux112~0_I .lut_mask = "3500350035F035F0"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux112~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~219_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[31] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[33] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[35] ), .combout(\rtl~219 )); defparam \rtl~219_I .shared_arith = "off"; defparam \rtl~219_I .extended_lut = "off"; defparam \rtl~219_I .lut_mask = "051105BBAF11AFBB"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~220 ), .asdata(\rtl~219 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux113~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~2 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][20] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~3 ), .dataf(\__ALT_INV__rtl~313 ), .combout(\fp_pow_0002:fp_pow_inst|Mux113~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux113~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux113~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux113~0_I .lut_mask = "110C110CDD0CDD0C"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux113~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[28] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[28]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist54|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~218_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[30] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[28] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[32] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[34] ), .combout(\rtl~218 )); defparam \rtl~218_I .shared_arith = "off"; defparam \rtl~218_I .extended_lut = "off"; defparam \rtl~218_I .lut_mask = "00275527AA27FF27"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~219 ), .asdata(\rtl~218 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux114~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][19] ), .datab(\__ALT_INV__rtl~312 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~2 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~3 ), .combout(\fp_pow_0002:fp_pow_inst|Mux114~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux114~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux114~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux114~0_I .lut_mask = "303F303F50505050"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux114~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[27] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~215_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[31] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[33] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[27] ), .combout(\rtl~215 )); defparam \rtl~215_I .shared_arith = "off"; defparam \rtl~215_I .extended_lut = "off"; defparam \rtl~215_I .lut_mask = "0C443F440C773F77"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~218 ), .asdata(\rtl~215 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][17]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist9_replace_mem_dmem|altera_syncram_beg3:auto_generated|altsyncram_6nb4:altsyncram1|dataout_reg[17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][17]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][17]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][17]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|delay_signals[0][17]~DUPLICATE_I .created_from = "Q(delay_signals[0][17])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux116~0_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][17]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~2 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~3 ), .datae(\__ALT_INV__rtl~309 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Mux116~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux116~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux116~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux116~0_I .lut_mask = "0030F0300F30FF30"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux116~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[25] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~217_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[31] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[25] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[27] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2] ), .combout(\rtl~217 )); defparam \rtl~217_I .shared_arith = "off"; defparam \rtl~217_I .extended_lut = "off"; defparam \rtl~217_I .lut_mask = "5555333300FF0F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux115~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~2 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[29]~3 ), .datac(\__ALT_INV__rtl~315 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist9_outputreg|__ALT_INV__delay_signals[0][18]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Mux115~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux115~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux115~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux115~0_I .lut_mask = "08084C4C2A2A6E6E"; dffeas \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux115~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[26] )); defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~216_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[26] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][2] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[30] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[32] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__leftShiftStage1_uid574_normValLog_uid79_fpPowrTest_q[28] ), .combout(\rtl~216 )); defparam \rtl~216_I .shared_arith = "off"; defparam \rtl~216_I .extended_lut = "off"; defparam \rtl~216_I .lut_mask = "001DCC1D331DFF1D"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|expFracConc_uid87_fpPowrTest_q[0]~1_I ( .datac(\__ALT_INV__rtl~217 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~216 ), .combout(\fp_pow_0002:fp_pow_inst|expFracConc_uid87_fpPowrTest_q[0]~1 )); defparam \fp_pow_0002:fp_pow_inst|expFracConc_uid87_fpPowrTest_q[0]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|expFracConc_uid87_fpPowrTest_q[0]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|expFracConc_uid87_fpPowrTest_q[0]~1_I .lut_mask = "000F000FFF0FFF0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|expFracConc_uid87_fpPowrTest_q[0]~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~215 ), .asdata(\rtl~216 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist51|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist105|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~97_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][1] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add23~97 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~98 )); defparam \fp_pow_0002:fp_pow_inst|Add23~97_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~97_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~97_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~101_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][2] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~98 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~101 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~102 )); defparam \fp_pow_0002:fp_pow_inst|Add23~101_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~101_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~101_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~105_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][3] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~102 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~105 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~106 )); defparam \fp_pow_0002:fp_pow_inst|Add23~105_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~105_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~105_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~109_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][4] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~106 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~109 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~110 )); defparam \fp_pow_0002:fp_pow_inst|Add23~109_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~109_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~109_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~113_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~110 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~113 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~114 )); defparam \fp_pow_0002:fp_pow_inst|Add23~113_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~113_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~113_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~117_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][6] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~114 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~117 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~118 )); defparam \fp_pow_0002:fp_pow_inst|Add23~117_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~117_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~117_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~121_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~118 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~121 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~122 )); defparam \fp_pow_0002:fp_pow_inst|Add23~121_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~121_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~121_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~125_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][8] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~122 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~125 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~126 )); defparam \fp_pow_0002:fp_pow_inst|Add23~125_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~125_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~125_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~129_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][9] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~126 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~129 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~130 )); defparam \fp_pow_0002:fp_pow_inst|Add23~129_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~129_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~129_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~133_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][10] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~130 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~133 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~134 )); defparam \fp_pow_0002:fp_pow_inst|Add23~133_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~133_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~133_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~137_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][11] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~134 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~137 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~138 )); defparam \fp_pow_0002:fp_pow_inst|Add23~137_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~137_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~137_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~141_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][12] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~138 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~141 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~142 )); defparam \fp_pow_0002:fp_pow_inst|Add23~141_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~141_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~141_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~145_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][13] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~142 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~145 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~146 )); defparam \fp_pow_0002:fp_pow_inst|Add23~145_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~145_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~145_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~149_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][14] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~146 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~149 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~150 )); defparam \fp_pow_0002:fp_pow_inst|Add23~149_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~149_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~149_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~153_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][15] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~150 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~153 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~154 )); defparam \fp_pow_0002:fp_pow_inst|Add23~153_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~153_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~153_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~157_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][16] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~154 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~157 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~158 )); defparam \fp_pow_0002:fp_pow_inst|Add23~157_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~157_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~157_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~161_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][17] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~158 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~161 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~162 )); defparam \fp_pow_0002:fp_pow_inst|Add23~161_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~161_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~161_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~165_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][18] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~162 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~165 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~166 )); defparam \fp_pow_0002:fp_pow_inst|Add23~165_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~165_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~165_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~45_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][19] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~166 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~46 )); defparam \fp_pow_0002:fp_pow_inst|Add23~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~45_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~49_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][20] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~50 )); defparam \fp_pow_0002:fp_pow_inst|Add23~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~49_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~53_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][21] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~54 )); defparam \fp_pow_0002:fp_pow_inst|Add23~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~53_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~57_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][22] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~57 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~58 )); defparam \fp_pow_0002:fp_pow_inst|Add23~57_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~57_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~57_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~61_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][23] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~58 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~62 )); defparam \fp_pow_0002:fp_pow_inst|Add23~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~61_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~65_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~65 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~66 )); defparam \fp_pow_0002:fp_pow_inst|Add23~65_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~65_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~65_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~69_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][25] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~66 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~69 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~70 )); defparam \fp_pow_0002:fp_pow_inst|Add23~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~69_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~73_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][26] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~70 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~73 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~74 )); defparam \fp_pow_0002:fp_pow_inst|Add23~73_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~73_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~73_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~77_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][27] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~74 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~78 )); defparam \fp_pow_0002:fp_pow_inst|Add23~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~77_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~81_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][28] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~81 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~82 )); defparam \fp_pow_0002:fp_pow_inst|Add23~81_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~81_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~81_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~85_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][29] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~82 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~85 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~86 )); defparam \fp_pow_0002:fp_pow_inst|Add23~85_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~85_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~85_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~89_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][30] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~86 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~89 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~90 )); defparam \fp_pow_0002:fp_pow_inst|Add23~89_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~89_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~89_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~93_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][31] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~90 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~93 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~94 )); defparam \fp_pow_0002:fp_pow_inst|Add23~93_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~93_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~93_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~41_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][32] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~94 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~42 )); defparam \fp_pow_0002:fp_pow_inst|Add23~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~41_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~29_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][33] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~30 )); defparam \fp_pow_0002:fp_pow_inst|Add23~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~29_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~21_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][34] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~22 )); defparam \fp_pow_0002:fp_pow_inst|Add23~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~21_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~37_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][35] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~38 )); defparam \fp_pow_0002:fp_pow_inst|Add23~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~37_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~33_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][36] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~34 )); defparam \fp_pow_0002:fp_pow_inst|Add23~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~33_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~25_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][37] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~26 )); defparam \fp_pow_0002:fp_pow_inst|Add23~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~25_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~17_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][38] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~18 )); defparam \fp_pow_0002:fp_pow_inst|Add23~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~17_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~13_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][39] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~14 )); defparam \fp_pow_0002:fp_pow_inst|Add23~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~13_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~9_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][40] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~10 )); defparam \fp_pow_0002:fp_pow_inst|Add23~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~9_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~5_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist105|__ALT_INV__delay_signals[0][41] ), .cin(\fp_pow_0002:fp_pow_inst|Add23~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add23~6 )); defparam \fp_pow_0002:fp_pow_inst|Add23~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~5_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add23~1_I ( .cin(\fp_pow_0002:fp_pow_inst|Add23~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add23~1 )); defparam \fp_pow_0002:fp_pow_inst|Add23~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add23~1_I .lut_mask = "0000FFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][1]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][1]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][1]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][1]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|delay_signals[0][1]~DUPLICATE_I .created_from = "Q(delay_signals[0][1])"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist103|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add33~21_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][0] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add33~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add33~22 )); defparam \fp_pow_0002:fp_pow_inst|Add33~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add33~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add33~21_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add33~37_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .cin(\fp_pow_0002:fp_pow_inst|Add33~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add33~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add33~38 )); defparam \fp_pow_0002:fp_pow_inst|Add33~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add33~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add33~37_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add33~29_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][2] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][2] ), .cin(\fp_pow_0002:fp_pow_inst|Add33~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add33~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add33~30 )); defparam \fp_pow_0002:fp_pow_inst|Add33~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add33~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add33~29_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add33~33_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][3] ), .cin(\fp_pow_0002:fp_pow_inst|Add33~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add33~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add33~34 )); defparam \fp_pow_0002:fp_pow_inst|Add33~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add33~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add33~33_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add33~25_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][4] ), .cin(\fp_pow_0002:fp_pow_inst|Add33~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add33~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add33~26 )); defparam \fp_pow_0002:fp_pow_inst|Add33~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add33~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add33~25_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add33~17_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add33~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add33~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add33~18 )); defparam \fp_pow_0002:fp_pow_inst|Add33~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add33~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add33~17_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add33~13_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][6] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][6] ), .cin(\fp_pow_0002:fp_pow_inst|Add33~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add33~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add33~14 )); defparam \fp_pow_0002:fp_pow_inst|Add33~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add33~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add33~13_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add33~9_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][7] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist131_outputreg|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add33~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add33~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add33~10 )); defparam \fp_pow_0002:fp_pow_inst|Add33~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add33~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add33~9_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add33~5_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][8] ), .cin(\fp_pow_0002:fp_pow_inst|Add33~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add33~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add33~6 )); defparam \fp_pow_0002:fp_pow_inst|Add33~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add33~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add33~5_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add33~1_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist103|__ALT_INV__delay_signals[0][8] ), .cin(\fp_pow_0002:fp_pow_inst|Add33~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add33~1 )); defparam \fp_pow_0002:fp_pow_inst|Add33~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add33~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add33~1_I .lut_mask = "0000FFFF00003333"; dffeas \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add33~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[9] )); defparam \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[0]~0_I ( .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist9_replace_rdcnt_i[0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "FFFF0000FFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist9_replace_rdcnt_i[1] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[1] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[1]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3899,portadatain_unconnected_wire_3900,portadatain_unconnected_wire_3901,portadatain_unconnected_wire_3902,portadatain_unconnected_wire_3903,portadatain_unconnected_wire_3904,portadatain_unconnected_wire_3905, portadatain_unconnected_wire_3906,portadatain_unconnected_wire_3907,portadatain_unconnected_wire_3908,portadatain_unconnected_wire_3909,portadatain_unconnected_wire_3910,portadatain_unconnected_wire_3911,portadatain_unconnected_wire_3912, portadatain_unconnected_wire_3913,portadatain_unconnected_wire_3914,portadatain_unconnected_wire_3915,portadatain_unconnected_wire_3916,portadatain_unconnected_wire_3917,\fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[9] }), .portaaddr({portaaddr_unconnected_wire_3918,portaaddr_unconnected_wire_3919,portaaddr_unconnected_wire_3920,portaaddr_unconnected_wire_3921,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3922,portbaddr_unconnected_wire_3923,portbaddr_unconnected_wire_3924,portbaddr_unconnected_wire_3925, \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[9] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9 .logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9 .first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama9 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add33~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[8] )); defparam \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[8]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3926,portadatain_unconnected_wire_3927,portadatain_unconnected_wire_3928,portadatain_unconnected_wire_3929,portadatain_unconnected_wire_3930,portadatain_unconnected_wire_3931,portadatain_unconnected_wire_3932, portadatain_unconnected_wire_3933,portadatain_unconnected_wire_3934,portadatain_unconnected_wire_3935,portadatain_unconnected_wire_3936,portadatain_unconnected_wire_3937,portadatain_unconnected_wire_3938,portadatain_unconnected_wire_3939, portadatain_unconnected_wire_3940,portadatain_unconnected_wire_3941,portadatain_unconnected_wire_3942,portadatain_unconnected_wire_3943,portadatain_unconnected_wire_3944,\fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[8] }), .portaaddr({portaaddr_unconnected_wire_3945,portaaddr_unconnected_wire_3946,portaaddr_unconnected_wire_3947,portaaddr_unconnected_wire_3948,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3949,portbaddr_unconnected_wire_3950,portbaddr_unconnected_wire_3951,portbaddr_unconnected_wire_3952, \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[8] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8 .logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8 .first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama8 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add33~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[7] )); defparam \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[7]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3953,portadatain_unconnected_wire_3954,portadatain_unconnected_wire_3955,portadatain_unconnected_wire_3956,portadatain_unconnected_wire_3957,portadatain_unconnected_wire_3958,portadatain_unconnected_wire_3959, portadatain_unconnected_wire_3960,portadatain_unconnected_wire_3961,portadatain_unconnected_wire_3962,portadatain_unconnected_wire_3963,portadatain_unconnected_wire_3964,portadatain_unconnected_wire_3965,portadatain_unconnected_wire_3966, portadatain_unconnected_wire_3967,portadatain_unconnected_wire_3968,portadatain_unconnected_wire_3969,portadatain_unconnected_wire_3970,portadatain_unconnected_wire_3971,\fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[7] }), .portaaddr({portaaddr_unconnected_wire_3972,portaaddr_unconnected_wire_3973,portaaddr_unconnected_wire_3974,portaaddr_unconnected_wire_3975,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_3976,portbaddr_unconnected_wire_3977,portbaddr_unconnected_wire_3978,portbaddr_unconnected_wire_3979, \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[7] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7 .logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7 .first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama7 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add33~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[6] )); defparam \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[6]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_3980,portadatain_unconnected_wire_3981,portadatain_unconnected_wire_3982,portadatain_unconnected_wire_3983,portadatain_unconnected_wire_3984,portadatain_unconnected_wire_3985,portadatain_unconnected_wire_3986, portadatain_unconnected_wire_3987,portadatain_unconnected_wire_3988,portadatain_unconnected_wire_3989,portadatain_unconnected_wire_3990,portadatain_unconnected_wire_3991,portadatain_unconnected_wire_3992,portadatain_unconnected_wire_3993, portadatain_unconnected_wire_3994,portadatain_unconnected_wire_3995,portadatain_unconnected_wire_3996,portadatain_unconnected_wire_3997,portadatain_unconnected_wire_3998,\fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[6] }), .portaaddr({portaaddr_unconnected_wire_3999,portaaddr_unconnected_wire_4000,portaaddr_unconnected_wire_4001,portaaddr_unconnected_wire_4002,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4003,portbaddr_unconnected_wire_4004,portbaddr_unconnected_wire_4005,portbaddr_unconnected_wire_4006, \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[6] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6 .logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6 .first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama6 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add33~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[5] )); defparam \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[5]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4007,portadatain_unconnected_wire_4008,portadatain_unconnected_wire_4009,portadatain_unconnected_wire_4010,portadatain_unconnected_wire_4011,portadatain_unconnected_wire_4012,portadatain_unconnected_wire_4013, portadatain_unconnected_wire_4014,portadatain_unconnected_wire_4015,portadatain_unconnected_wire_4016,portadatain_unconnected_wire_4017,portadatain_unconnected_wire_4018,portadatain_unconnected_wire_4019,portadatain_unconnected_wire_4020, portadatain_unconnected_wire_4021,portadatain_unconnected_wire_4022,portadatain_unconnected_wire_4023,portadatain_unconnected_wire_4024,portadatain_unconnected_wire_4025,\fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[5] }), .portaaddr({portaaddr_unconnected_wire_4026,portaaddr_unconnected_wire_4027,portaaddr_unconnected_wire_4028,portaaddr_unconnected_wire_4029,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4030,portbaddr_unconnected_wire_4031,portbaddr_unconnected_wire_4032,portbaddr_unconnected_wire_4033, \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[5] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5 .logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5 .first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama5 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add33~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[4] )); defparam \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4034,portadatain_unconnected_wire_4035,portadatain_unconnected_wire_4036,portadatain_unconnected_wire_4037,portadatain_unconnected_wire_4038,portadatain_unconnected_wire_4039,portadatain_unconnected_wire_4040, portadatain_unconnected_wire_4041,portadatain_unconnected_wire_4042,portadatain_unconnected_wire_4043,portadatain_unconnected_wire_4044,portadatain_unconnected_wire_4045,portadatain_unconnected_wire_4046,portadatain_unconnected_wire_4047, portadatain_unconnected_wire_4048,portadatain_unconnected_wire_4049,portadatain_unconnected_wire_4050,portadatain_unconnected_wire_4051,portadatain_unconnected_wire_4052,\fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[4] }), .portaaddr({portaaddr_unconnected_wire_4053,portaaddr_unconnected_wire_4054,portaaddr_unconnected_wire_4055,portaaddr_unconnected_wire_4056,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4057,portbaddr_unconnected_wire_4058,portbaddr_unconnected_wire_4059,portbaddr_unconnected_wire_4060, \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[4] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4 .logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4 .first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama4 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add33~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[3] )); defparam \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[3]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4061,portadatain_unconnected_wire_4062,portadatain_unconnected_wire_4063,portadatain_unconnected_wire_4064,portadatain_unconnected_wire_4065,portadatain_unconnected_wire_4066,portadatain_unconnected_wire_4067, portadatain_unconnected_wire_4068,portadatain_unconnected_wire_4069,portadatain_unconnected_wire_4070,portadatain_unconnected_wire_4071,portadatain_unconnected_wire_4072,portadatain_unconnected_wire_4073,portadatain_unconnected_wire_4074, portadatain_unconnected_wire_4075,portadatain_unconnected_wire_4076,portadatain_unconnected_wire_4077,portadatain_unconnected_wire_4078,portadatain_unconnected_wire_4079,\fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[3] }), .portaaddr({portaaddr_unconnected_wire_4080,portaaddr_unconnected_wire_4081,portaaddr_unconnected_wire_4082,portaaddr_unconnected_wire_4083,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4084,portbaddr_unconnected_wire_4085,portbaddr_unconnected_wire_4086,portbaddr_unconnected_wire_4087, \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[3] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3 .logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3 .first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama3 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add33~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[2] )); defparam \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[2]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4088,portadatain_unconnected_wire_4089,portadatain_unconnected_wire_4090,portadatain_unconnected_wire_4091,portadatain_unconnected_wire_4092,portadatain_unconnected_wire_4093,portadatain_unconnected_wire_4094, portadatain_unconnected_wire_4095,portadatain_unconnected_wire_4096,portadatain_unconnected_wire_4097,portadatain_unconnected_wire_4098,portadatain_unconnected_wire_4099,portadatain_unconnected_wire_4100,portadatain_unconnected_wire_4101, portadatain_unconnected_wire_4102,portadatain_unconnected_wire_4103,portadatain_unconnected_wire_4104,portadatain_unconnected_wire_4105,portadatain_unconnected_wire_4106,\fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[2] }), .portaaddr({portaaddr_unconnected_wire_4107,portaaddr_unconnected_wire_4108,portaaddr_unconnected_wire_4109,portaaddr_unconnected_wire_4110,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4111,portbaddr_unconnected_wire_4112,portbaddr_unconnected_wire_4113,portbaddr_unconnected_wire_4114, \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[2] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2 .logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2 .first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama2 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add33~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[1] )); defparam \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[1]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4115,portadatain_unconnected_wire_4116,portadatain_unconnected_wire_4117,portadatain_unconnected_wire_4118,portadatain_unconnected_wire_4119,portadatain_unconnected_wire_4120,portadatain_unconnected_wire_4121, portadatain_unconnected_wire_4122,portadatain_unconnected_wire_4123,portadatain_unconnected_wire_4124,portadatain_unconnected_wire_4125,portadatain_unconnected_wire_4126,portadatain_unconnected_wire_4127,portadatain_unconnected_wire_4128, portadatain_unconnected_wire_4129,portadatain_unconnected_wire_4130,portadatain_unconnected_wire_4131,portadatain_unconnected_wire_4132,portadatain_unconnected_wire_4133,\fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[1] }), .portaaddr({portaaddr_unconnected_wire_4134,portaaddr_unconnected_wire_4135,portaaddr_unconnected_wire_4136,portaaddr_unconnected_wire_4137,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4138,portbaddr_unconnected_wire_4139,portbaddr_unconnected_wire_4140,portbaddr_unconnected_wire_4141, \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[1] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1 .logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1 .first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama1 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add33~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[0] )); defparam \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[0]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist101_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4142,portadatain_unconnected_wire_4143,portadatain_unconnected_wire_4144,portadatain_unconnected_wire_4145,portadatain_unconnected_wire_4146,portadatain_unconnected_wire_4147,portadatain_unconnected_wire_4148, portadatain_unconnected_wire_4149,portadatain_unconnected_wire_4150,portadatain_unconnected_wire_4151,portadatain_unconnected_wire_4152,portadatain_unconnected_wire_4153,portadatain_unconnected_wire_4154,portadatain_unconnected_wire_4155, portadatain_unconnected_wire_4156,portadatain_unconnected_wire_4157,portadatain_unconnected_wire_4158,portadatain_unconnected_wire_4159,portadatain_unconnected_wire_4160,\fp_pow_0002:fp_pow_inst|expProdPhase1_uid100_fpPowrTest_o[0] }), .portaaddr({portaaddr_unconnected_wire_4161,portaaddr_unconnected_wire_4162,portaaddr_unconnected_wire_4163,portaaddr_unconnected_wire_4164,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist9_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4165,portbaddr_unconnected_wire_4166,portbaddr_unconnected_wire_4167,portbaddr_unconnected_wire_4168, \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0 .logical_ram_depth = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0 .logical_ram_width = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0 .last_address = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][6]~0_I ( .combout(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][6]~0 )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][6]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][6]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][6]~0_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][7]~1_I ( .combout(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][7]~1 )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][7]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][7]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][7]~1_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][8]~2_I ( .combout(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][8]~2 )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][8]~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][8]~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][8]~2_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][9]~3_I ( .combout(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][9]~3 )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][9]~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][9]~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][9]~3_I .lut_mask = "0000000000000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~57 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~61 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~65 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][23]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~69 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][24]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~73 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~77 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][26]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~81 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][27]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~85 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][28]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~89 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][29]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~93 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][30]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][31]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][32]~I .is_wysiwyg = "true"; cyclonev_mac \fp_pow_0002:fp_pow_inst|Mult10~mac ( .sub(gnd), .negate(gnd), .ax({ax_unconnected_wire_4169,ax_unconnected_wire_4170,ax_unconnected_wire_4171,ax_unconnected_wire_4172,ax_unconnected_wire_4173,ax_unconnected_wire_4174,ax_unconnected_wire_4175,ax_unconnected_wire_4176,ax_unconnected_wire_4177,ax_unconnected_wire_4178, ax_unconnected_wire_4179,ax_unconnected_wire_4180,ax_unconnected_wire_4181,ax_unconnected_wire_4182,ax_unconnected_wire_4183,ax_unconnected_wire_4184,ax_unconnected_wire_4185,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][9]~3 , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][8]~2 ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][7]~1 ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_c0[0][6]~0 ,\vcc , \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][22] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][21] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][20] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][19] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][18] }), .ay({ay_unconnected_wire_4186,ay_unconnected_wire_4187,ay_unconnected_wire_4188,ay_unconnected_wire_4189,ay_unconnected_wire_4190,ay_unconnected_wire_4191,ay_unconnected_wire_4192,ay_unconnected_wire_4193,ay_unconnected_wire_4194,ay_unconnected_wire_4195, ay_unconnected_wire_4196,\vcc ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][32] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][31] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][30] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][29] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][28] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][27] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][26] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][25] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][24] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][23] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][22] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][21] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][20] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][19] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][18] }), .clk({clk_unconnected_wire_4197,clk_unconnected_wire_4198,\clk~CLKENA0 }), .aclr({\areset~CLKENA0 ,\areset~CLKENA0 }), .ena({ena_unconnected_wire_4199,ena_unconnected_wire_4200,\vcc }), .resulta({\fp_pow_0002:fp_pow_inst|Mult10~49 ,\fp_pow_0002:fp_pow_inst|Mult10~48 ,\fp_pow_0002:fp_pow_inst|Mult10~47 ,\fp_pow_0002:fp_pow_inst|Mult10~46 ,\fp_pow_0002:fp_pow_inst|Mult10~45 ,\fp_pow_0002:fp_pow_inst|Mult10~44 ,\fp_pow_0002:fp_pow_inst|Mult10~43 , \fp_pow_0002:fp_pow_inst|Mult10~42 ,\fp_pow_0002:fp_pow_inst|Mult10~41 ,\fp_pow_0002:fp_pow_inst|Mult10~40 ,\fp_pow_0002:fp_pow_inst|Mult10~39 ,\fp_pow_0002:fp_pow_inst|Mult10~38 ,\fp_pow_0002:fp_pow_inst|Mult10~37 ,\fp_pow_0002:fp_pow_inst|Mult10~36 , \fp_pow_0002:fp_pow_inst|Mult10~35 ,\fp_pow_0002:fp_pow_inst|Mult10~34 ,\fp_pow_0002:fp_pow_inst|Mult10~33 ,\fp_pow_0002:fp_pow_inst|Mult10~32 ,\fp_pow_0002:fp_pow_inst|Mult10~31 ,\fp_pow_0002:fp_pow_inst|Mult10~30 ,\fp_pow_0002:fp_pow_inst|Mult10~29 , \fp_pow_0002:fp_pow_inst|Mult10~28 ,\fp_pow_0002:fp_pow_inst|Mult10~27 ,\fp_pow_0002:fp_pow_inst|Mult10~26 ,\fp_pow_0002:fp_pow_inst|Mult10~25 ,\fp_pow_0002:fp_pow_inst|Mult10~24 ,\fp_pow_0002:fp_pow_inst|Mult10~23 ,\fp_pow_0002:fp_pow_inst|Mult10~22 , \fp_pow_0002:fp_pow_inst|Mult10~21 ,\fp_pow_0002:fp_pow_inst|Mult10~20 ,\fp_pow_0002:fp_pow_inst|Mult10~19 ,\fp_pow_0002:fp_pow_inst|Mult10~18 ,\fp_pow_0002:fp_pow_inst|Mult10~17 ,\fp_pow_0002:fp_pow_inst|Mult10~16 ,\fp_pow_0002:fp_pow_inst|Mult10~15 , \fp_pow_0002:fp_pow_inst|Mult10~14 ,\fp_pow_0002:fp_pow_inst|Mult10~13 ,\fp_pow_0002:fp_pow_inst|Mult10~12 ,\fp_pow_0002:fp_pow_inst|Mult10~11 ,\fp_pow_0002:fp_pow_inst|Mult10~10 ,\fp_pow_0002:fp_pow_inst|Mult10~9 ,\fp_pow_0002:fp_pow_inst|Mult10~8 , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][21] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][20] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][19] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][18] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][17] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][16] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][15] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][14] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][13] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][12] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][11] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][10] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][9] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][8] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][7] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][6] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][5] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][4] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][3] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][2] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][1] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][0] })); defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .signed_max = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .signed_may = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .signed_mbx = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .signed_mby = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .preadder_subtract_a = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .preadder_subtract_b = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .ay_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .by_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .delay_scan_out_ay = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .delay_scan_out_by = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .use_chainadder = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .enable_double_accum = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .operation_mode = "M18X18_FULL"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .operand_source_max = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .operand_source_may = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .operand_source_mbx = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .operand_source_mby = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .ax_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .ay_scan_in_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .az_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .bx_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .by_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .bz_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .coef_sel_a_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .coef_sel_b_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .sub_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .negate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .accumulate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .load_const_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .output_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .coef_a_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .coef_a_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .coef_a_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .coef_a_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .coef_a_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .coef_a_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .coef_a_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .coef_a_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .coef_b_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .coef_b_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .coef_b_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .coef_b_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .coef_b_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .coef_b_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .coef_b_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .coef_b_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .ax_width = 10; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .ay_scan_in_width = 16; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .mode_sub_location = 0; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .load_const_value = 0; defparam \fp_pow_0002:fp_pow_inst|Mult10~mac .result_a_width = 64; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][57]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][57] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][57]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][57]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][57] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist132_replace_mem_dmem|altera_syncram_ghg3:auto_generated|altsyncram_bqb4:altsyncram1|dataout_reg[3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][9]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][10]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][14]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_c0[1][18]~0_I ( .combout(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_c0[1][18]~0 )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_c0[1][18]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_c0[1][18]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_c0[1][18]~0_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][6]~0_I ( .combout(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][6]~0 )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][6]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][6]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][6]~0_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][7]~1_I ( .combout(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][7]~1 )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][7]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][7]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][7]~1_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][8]~2_I ( .combout(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][8]~2 )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][8]~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][8]~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][8]~2_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][9]~3_I ( .combout(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][9]~3 )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][9]~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][9]~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][9]~3_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][10]~4_I ( .combout(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][10]~4 )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][10]~4_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][10]~4_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][10]~4_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][11]~5_I ( .combout(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][11]~5 )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][11]~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][11]~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][11]~5_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][12]~6_I ( .combout(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][12]~6 )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][12]~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][12]~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][12]~6_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][13]~7_I ( .combout(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][13]~7 )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][13]~7_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][13]~7_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][13]~7_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][14]~8_I ( .combout(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][14]~8 )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][14]~8_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][14]~8_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][14]~8_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][15]~9_I ( .combout(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][15]~9 )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][15]~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][15]~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][15]~9_I .lut_mask = "0000000000000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][0]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~97 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][0]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][0]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][0]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][0]~DUPLICATE_I .created_from = "Q(delay_signals[0][0])"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~101 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~105 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~109 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~113 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~117 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~121 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~125 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~129 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~133 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~137 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~141 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~145 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~149 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~153 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~157 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~161 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~165 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_c0[0][18]~1_I ( .combout(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_c0[0][18]~1 )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_c0[0][18]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_c0[0][18]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_c0[0][18]~1_I .lut_mask = "0000000000000000"; cyclonev_mac \fp_pow_0002:fp_pow_inst|Add24~mac ( .sub(gnd), .negate(gnd), .ax({ax_unconnected_wire_4201,ax_unconnected_wire_4202,ax_unconnected_wire_4203,ax_unconnected_wire_4204,ax_unconnected_wire_4205,ax_unconnected_wire_4206,ax_unconnected_wire_4207,ax_unconnected_wire_4208,ax_unconnected_wire_4209,ax_unconnected_wire_4210, ax_unconnected_wire_4211,\vcc ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][32] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][31] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][30] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][29] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][28] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][27] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][26] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][25] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][24] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][23] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][22] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][21] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][20] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][19] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][18] }), .ay({ay_unconnected_wire_4212,ay_unconnected_wire_4213,ay_unconnected_wire_4214,ay_unconnected_wire_4215,ay_unconnected_wire_4216,ay_unconnected_wire_4217,ay_unconnected_wire_4218,ay_unconnected_wire_4219, \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_c0[1][18]~0 ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][17] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][16] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][15] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][14] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][13] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][12] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][11] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][10] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][9] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][7] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][4] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][1] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][0] }), .bx({bx_unconnected_wire_4220,bx_unconnected_wire_4221,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][15]~9 ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][14]~8 , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][13]~7 ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][12]~6 ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][11]~5 , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][10]~4 ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][9]~3 ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][8]~2 , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][7]~1 ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_a0[0][6]~0 ,\vcc ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][22] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][21] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][20] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][19] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][18] }), .by({\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_c0[0][18]~1 ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][17] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][16] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][15] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][14] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][13] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][12] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][11] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][10] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][9] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][7] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][4] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][1] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][0]~DUPLICATE }), .clk({clk_unconnected_wire_4222,clk_unconnected_wire_4223,\clk~CLKENA0 }), .aclr({\areset~CLKENA0 ,\areset~CLKENA0 }), .ena({ena_unconnected_wire_4224,ena_unconnected_wire_4225,\vcc }), .resulta({\fp_pow_0002:fp_pow_inst|Add24~35 ,\fp_pow_0002:fp_pow_inst|Add24~34 ,\fp_pow_0002:fp_pow_inst|Add24~33 ,\fp_pow_0002:fp_pow_inst|Add24~32 ,\fp_pow_0002:fp_pow_inst|Add24~31 ,\fp_pow_0002:fp_pow_inst|Add24~30 ,\fp_pow_0002:fp_pow_inst|Add24~29 , \fp_pow_0002:fp_pow_inst|Add24~28 ,\fp_pow_0002:fp_pow_inst|Add24~27 ,\fp_pow_0002:fp_pow_inst|Add24~26 ,\fp_pow_0002:fp_pow_inst|Add24~25 ,\fp_pow_0002:fp_pow_inst|Add24~24 ,\fp_pow_0002:fp_pow_inst|Add24~23 ,\fp_pow_0002:fp_pow_inst|Add24~22 , \fp_pow_0002:fp_pow_inst|Add24~21 ,\fp_pow_0002:fp_pow_inst|Add24~20 ,\fp_pow_0002:fp_pow_inst|Add24~19 ,\fp_pow_0002:fp_pow_inst|Add24~18 ,\fp_pow_0002:fp_pow_inst|Add24~17 ,\fp_pow_0002:fp_pow_inst|Add24~16 ,\fp_pow_0002:fp_pow_inst|Add24~15 , \fp_pow_0002:fp_pow_inst|Add24~14 ,\fp_pow_0002:fp_pow_inst|Add24~13 ,\fp_pow_0002:fp_pow_inst|Add24~12 ,\fp_pow_0002:fp_pow_inst|Add24~11 ,\fp_pow_0002:fp_pow_inst|Add24~10 ,\fp_pow_0002:fp_pow_inst|Add24~9 ,\fp_pow_0002:fp_pow_inst|Add24~8 , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][35] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][34] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][33] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][32] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][31] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][30] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][29] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][28] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][27] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][26] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][25] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][24] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][23] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][22] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][21] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][20] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][19] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][18] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][17] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][16] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][15] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][14] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][13] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][12] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][11] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][10] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][9] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][8] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][7] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][6] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][5] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][4] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][3] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][2] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][1] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][0] })); defparam \fp_pow_0002:fp_pow_inst|Add24~mac .signed_max = "false"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .signed_may = "true"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .signed_mbx = "false"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .signed_mby = "true"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .preadder_subtract_a = "false"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .preadder_subtract_b = "false"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .ay_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .by_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .delay_scan_out_ay = "false"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .delay_scan_out_by = "false"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .use_chainadder = "false"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .enable_double_accum = "false"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .operation_mode = "M18X18_SUMOF2"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .operand_source_max = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .operand_source_may = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .operand_source_mbx = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .operand_source_mby = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .ax_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .ay_scan_in_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .az_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .bx_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .by_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .bz_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .coef_sel_a_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .coef_sel_b_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .sub_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .negate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .accumulate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .load_const_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .output_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .coef_a_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .coef_a_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .coef_a_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .coef_a_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .coef_a_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .coef_a_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .coef_a_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .coef_a_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .coef_b_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .coef_b_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .coef_b_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .coef_b_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .coef_b_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .coef_b_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .coef_b_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .coef_b_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .ax_width = 16; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .ay_scan_in_width = 19; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .bx_width = 16; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .by_width = 19; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .mode_sub_location = 0; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .load_const_value = 0; defparam \fp_pow_0002:fp_pow_inst|Add24~mac .result_a_width = 64; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][35] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][35]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist4|delay_signals[0][5]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][35] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist4|delay_signals[0][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist4|delay_signals[0][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist4|delay_signals[0][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist4|delay_signals[0][5]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist4|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist4|delay_signals[0][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist4|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist4|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist4|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][56]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][20] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][56] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][56]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][56]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][56] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][55]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][55] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][55]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][55]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][55] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][54]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][54] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][54]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][54]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][54] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][53]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im10_cma_s[0][17] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][53]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][53]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][53]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][53]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][53]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][53]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][53] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][53]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][53]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][53] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][34]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][34] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][34]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][34]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][34]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][34]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][34]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][34]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist4|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][34] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist4|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist4|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist4|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][52]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][52] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][52]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][52]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][52] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist5|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][33]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][33] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][33]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][33]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][33]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][33]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][33]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][51]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im10_cma_s[0][15] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][51]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][51]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][51]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][51]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][51]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][51]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][51] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][51]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][51]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][32] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][50]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im10_cma_s[0][14] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][50]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][50]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][50]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][50]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][50]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][50]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][50] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][50]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][50]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][31] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][31]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][49]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][49] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][49]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][49]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][48]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][48] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][48]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][48]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][30] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][30]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][47]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][47] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][47]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][47]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][29] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][46]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im10_cma_s[0][10] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][46]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][46]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][46]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][46]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][46]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][46]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][46] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][46]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][46]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][28]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][28] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][28]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][28]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][28]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][28]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][28]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][28]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][45]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][45] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][45]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][45]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][27] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][27]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][44]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][44] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][44]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][44]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][26] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][26]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][43]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][43] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][43]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][43]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][25] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][24] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][42]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im10_cma_s[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][42]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][42]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][42]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][42]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][42]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][42]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][42] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][42]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][41]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im10_cma_s[0][5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][41]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][41]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][41]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][41]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][41]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][41]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][41] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][41]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][23] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][23]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][22] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][40]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][40] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][40]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][39]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][39] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][39]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][38]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][38] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][38]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][20] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][37]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im10_cma_s[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][37]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][37]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][37]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][37]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][37]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][37] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][37]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][36]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im10_cma_s[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][36] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][36]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][17]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][17] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][17]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][17]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][17]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][17]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][17]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~97 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][13]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add23~149 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][13]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][13]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][13]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][13]~DUPLICATE_I .created_from = "Q(delay_signals[0][13])"; cyclonev_mac \fp_pow_0002:fp_pow_inst|Mult11~mac ( .sub(gnd), .negate(gnd), .ax({ax_unconnected_wire_4226,ax_unconnected_wire_4227,ax_unconnected_wire_4228,ax_unconnected_wire_4229,ax_unconnected_wire_4230,ax_unconnected_wire_4231,ax_unconnected_wire_4232,ax_unconnected_wire_4233,ax_unconnected_wire_4234, \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][17] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][16] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][15] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][14] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][13]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][12] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][11] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][10] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][9] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist104|delay_signals[0][0] }), .ay({ay_unconnected_wire_4235,ay_unconnected_wire_4236,ay_unconnected_wire_4237,ay_unconnected_wire_4238,ay_unconnected_wire_4239,ay_unconnected_wire_4240,ay_unconnected_wire_4241,ay_unconnected_wire_4242,ay_unconnected_wire_4243, \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][17] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][16] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][15] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][14] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][13] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][12] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][11] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][10] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][9] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist132_outputreg|delay_signals[0][0] }), .clk({clk_unconnected_wire_4244,clk_unconnected_wire_4245,\clk~CLKENA0 }), .aclr({\areset~CLKENA0 ,\areset~CLKENA0 }), .ena({ena_unconnected_wire_4246,ena_unconnected_wire_4247,\vcc }), .resulta({\fp_pow_0002:fp_pow_inst|Mult11~35 ,\fp_pow_0002:fp_pow_inst|Mult11~34 ,\fp_pow_0002:fp_pow_inst|Mult11~33 ,\fp_pow_0002:fp_pow_inst|Mult11~32 ,\fp_pow_0002:fp_pow_inst|Mult11~31 ,\fp_pow_0002:fp_pow_inst|Mult11~30 ,\fp_pow_0002:fp_pow_inst|Mult11~29 , \fp_pow_0002:fp_pow_inst|Mult11~28 ,\fp_pow_0002:fp_pow_inst|Mult11~27 ,\fp_pow_0002:fp_pow_inst|Mult11~26 ,\fp_pow_0002:fp_pow_inst|Mult11~25 ,\fp_pow_0002:fp_pow_inst|Mult11~24 ,\fp_pow_0002:fp_pow_inst|Mult11~23 ,\fp_pow_0002:fp_pow_inst|Mult11~22 , \fp_pow_0002:fp_pow_inst|Mult11~21 ,\fp_pow_0002:fp_pow_inst|Mult11~20 ,\fp_pow_0002:fp_pow_inst|Mult11~19 ,\fp_pow_0002:fp_pow_inst|Mult11~18 ,\fp_pow_0002:fp_pow_inst|Mult11~17 ,\fp_pow_0002:fp_pow_inst|Mult11~16 ,\fp_pow_0002:fp_pow_inst|Mult11~15 , \fp_pow_0002:fp_pow_inst|Mult11~14 ,\fp_pow_0002:fp_pow_inst|Mult11~13 ,\fp_pow_0002:fp_pow_inst|Mult11~12 ,\fp_pow_0002:fp_pow_inst|Mult11~11 ,\fp_pow_0002:fp_pow_inst|Mult11~10 ,\fp_pow_0002:fp_pow_inst|Mult11~9 ,\fp_pow_0002:fp_pow_inst|Mult11~8 , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][35] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][34] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][33] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][32] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][31] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][30] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][29] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][28] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][27] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][26] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][25] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][24] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][23] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][22] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][21] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][20] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][19] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][18] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][17] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][16] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][15] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][14] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][13] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][12] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][11] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][10] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][9] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][8] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][7] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][6] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][5] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][4] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][3] , \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][2] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][1] ,\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_p[0][0] })); defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .signed_max = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .signed_may = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .signed_mbx = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .signed_mby = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .preadder_subtract_a = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .preadder_subtract_b = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .ay_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .by_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .delay_scan_out_ay = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .delay_scan_out_by = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .use_chainadder = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .enable_double_accum = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .operation_mode = "M18X18_FULL"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .operand_source_max = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .operand_source_may = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .operand_source_mbx = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .operand_source_mby = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .ax_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .ay_scan_in_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .az_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .bx_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .by_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .bz_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .coef_sel_a_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .coef_sel_b_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .sub_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .negate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .accumulate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .load_const_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .output_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .coef_a_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .coef_a_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .coef_a_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .coef_a_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .coef_a_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .coef_a_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .coef_a_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .coef_a_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .coef_b_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .coef_b_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .coef_b_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .coef_b_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .coef_b_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .coef_b_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .coef_b_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .coef_b_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .ax_width = 18; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .ay_scan_in_width = 18; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .mode_sub_location = 0; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .load_const_value = 0; defparam \fp_pow_0002:fp_pow_inst|Mult11~mac .result_a_width = 64; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][35]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][35] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][35]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][35]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][35]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][35]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][35]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][35]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][34] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][16]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][16] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][16]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][16]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][16]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][16]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][16]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][33]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][33] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][33]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][33]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][33]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][33]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][33]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][15]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][15] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][15]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][15]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][15]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][15]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][15]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][14] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][32]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][32] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][32]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][32]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][32]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][32]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][32]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][31]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][31] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][31]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][31]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][31]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][31]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][31]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][13]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][13] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][13]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][13]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][13]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][13]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][13]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][12]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][12] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][12]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][12]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][12]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][12]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][12]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][30] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][11]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][11] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][11]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][11]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][11]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][11]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][11]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][29] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][28]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][28] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][28]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][28]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][28]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][28]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][28]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][10]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][10] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][10]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][10]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][10]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][10]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][10]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][9]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][9] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][9]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][9]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][9]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][9]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][9]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][27]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][27] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][27]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][27]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][27]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][27]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][27]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][27]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][26] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][8]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][8] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][8]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][8]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][8]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][8]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][8]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][25]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][25] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][25]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][25]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][25]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][25]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][25]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][7]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][7] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][7]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][24]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][24] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][24]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][24]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][24]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][24]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][24]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][6]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][6]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][23] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][5]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][5]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][22]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][22] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][22]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][22]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][22]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][22]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][22]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][21]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][21] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][21]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][21]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][21]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][21]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][21]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][20] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_im0_cma_s[0][19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][18]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_im0_cma_s[0][18] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][18]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][18]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][18]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][18]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][18]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist21|delay_signals[0][18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_ma3_cma_s[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist0|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~138_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][18] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][0] ), .cin(gnd), .cout(\fp_pow_0002:fp_pow_inst|Add25~138 )); defparam \fp_pow_0002:fp_pow_inst|Add25~138_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~138_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~138_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~134_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][19] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][1] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~138 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~134 )); defparam \fp_pow_0002:fp_pow_inst|Add25~134_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~134_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~134_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~130_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][20] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][2] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~134 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~130 )); defparam \fp_pow_0002:fp_pow_inst|Add25~130_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~130_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~130_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~126_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][21] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][3] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~130 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~126 )); defparam \fp_pow_0002:fp_pow_inst|Add25~126_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~126_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~126_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~122_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][22] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][4] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~126 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~122 )); defparam \fp_pow_0002:fp_pow_inst|Add25~122_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~122_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~122_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~101_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][23] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~122 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~101 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~102 )); defparam \fp_pow_0002:fp_pow_inst|Add25~101_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~101_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~101_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~105_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][24] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][6] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~102 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~105 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~106 )); defparam \fp_pow_0002:fp_pow_inst|Add25~105_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~105_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~105_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~113_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][25] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~106 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~113 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~114 )); defparam \fp_pow_0002:fp_pow_inst|Add25~113_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~113_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~113_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~117_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][26] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][8] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~114 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~117 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~118 )); defparam \fp_pow_0002:fp_pow_inst|Add25~117_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~117_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~117_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~109_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][9] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][27] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~118 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~109 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~110 )); defparam \fp_pow_0002:fp_pow_inst|Add25~109_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~109_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~109_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~97_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][28] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][10] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~110 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~97 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~98 )); defparam \fp_pow_0002:fp_pow_inst|Add25~97_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~97_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~97_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~93_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][11] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][29] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~98 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~93 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~94 )); defparam \fp_pow_0002:fp_pow_inst|Add25~93_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~93_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~93_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~89_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][12] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][30] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~94 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~89 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~90 )); defparam \fp_pow_0002:fp_pow_inst|Add25~89_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~89_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~89_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~85_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][31] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][13] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~90 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~85 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~86 )); defparam \fp_pow_0002:fp_pow_inst|Add25~85_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~85_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~85_I .lut_mask = "0000FF00000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~81_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][14] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][32] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~86 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~81 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~82 )); defparam \fp_pow_0002:fp_pow_inst|Add25~81_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~81_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~81_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~77_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][33] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][15] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~82 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~78 )); defparam \fp_pow_0002:fp_pow_inst|Add25~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~77_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~73_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][34] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][16] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~73 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~74 )); defparam \fp_pow_0002:fp_pow_inst|Add25~73_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~73_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~73_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~69_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][17] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][35] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~74 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~69 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~70 )); defparam \fp_pow_0002:fp_pow_inst|Add25~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~69_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~65_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][36] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][18] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~70 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~65 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~66 )); defparam \fp_pow_0002:fp_pow_inst|Add25~65_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~65_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~65_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~61_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][37] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][19] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~66 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~62 )); defparam \fp_pow_0002:fp_pow_inst|Add25~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~61_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~53_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][38] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][20] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~54 )); defparam \fp_pow_0002:fp_pow_inst|Add25~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~53_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~49_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][39] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][21] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~50 )); defparam \fp_pow_0002:fp_pow_inst|Add25~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~49_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~1_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][22] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][40] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~1 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~2 )); defparam \fp_pow_0002:fp_pow_inst|Add25~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~1_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][41] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][23] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~2 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~6 )); defparam \fp_pow_0002:fp_pow_inst|Add25~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~5_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~25_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][24] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][42] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~26 )); defparam \fp_pow_0002:fp_pow_inst|Add25~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~25_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~29_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][25] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~30 )); defparam \fp_pow_0002:fp_pow_inst|Add25~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~29_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~17_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][44] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][26] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~18 )); defparam \fp_pow_0002:fp_pow_inst|Add25~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~17_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~21_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][45] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][27] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~22 )); defparam \fp_pow_0002:fp_pow_inst|Add25~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~21_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~41_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][46] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][28] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~42 )); defparam \fp_pow_0002:fp_pow_inst|Add25~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~41_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~45_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][47] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][29] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~46 )); defparam \fp_pow_0002:fp_pow_inst|Add25~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~45_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~9_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][48] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][30] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~10 )); defparam \fp_pow_0002:fp_pow_inst|Add25~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~9_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~13_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][31] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][49] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~14 )); defparam \fp_pow_0002:fp_pow_inst|Add25~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~13_I .lut_mask = "0000FF00000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~33_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][32] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][50] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~34 )); defparam \fp_pow_0002:fp_pow_inst|Add25~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~33_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~37_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist0|__ALT_INV__delay_signals[0][33] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist21|__ALT_INV__delay_signals[0][51] ), .cin(\fp_pow_0002:fp_pow_inst|Add25~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add25~38 )); defparam \fp_pow_0002:fp_pow_inst|Add25~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~37_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add25~57_I ( .cin(\fp_pow_0002:fp_pow_inst|Add25~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add25~57 )); defparam \fp_pow_0002:fp_pow_inst|Add25~57_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~57_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add25~57_I .lut_mask = "0000FFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[53]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~57 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[53] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[53]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[53]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add26~26_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[53] ), .cin(gnd), .cout(\fp_pow_0002:fp_pow_inst|Add26~26 )); defparam \fp_pow_0002:fp_pow_inst|Add26~26_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add26~26_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add26~26_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add26~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist4|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist5|__ALT_INV__delay_signals[0][0] ), .cin(\fp_pow_0002:fp_pow_inst|Add26~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add26~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add26~6 )); defparam \fp_pow_0002:fp_pow_inst|Add26~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add26~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add26~5_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add26~9_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist5|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist4|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add26~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add26~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add26~10 )); defparam \fp_pow_0002:fp_pow_inst|Add26~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add26~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add26~9_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add26~13_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist5|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist4|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add26~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add26~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add26~14 )); defparam \fp_pow_0002:fp_pow_inst|Add26~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add26~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add26~13_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add26~17_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist5|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist4|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add26~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add26~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add26~18 )); defparam \fp_pow_0002:fp_pow_inst|Add26~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add26~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add26~17_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add26~21_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist5|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist4|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add26~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add26~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add26~22 )); defparam \fp_pow_0002:fp_pow_inst|Add26~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add26~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add26~21_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add26~1_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist5|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist4|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add26~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add26~1 )); defparam \fp_pow_0002:fp_pow_inst|Add26~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add26~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add26~1_I .lut_mask = "0000CCCC000000FF"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add26~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add34~21_I ( .dataa(\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add34~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add34~22 )); defparam \fp_pow_0002:fp_pow_inst|Add34~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add34~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add34~21_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add34~37_I ( .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[1] ), .cin(\fp_pow_0002:fp_pow_inst|Add34~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add34~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add34~38 )); defparam \fp_pow_0002:fp_pow_inst|Add34~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add34~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add34~37_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add34~29_I ( .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[2] ), .cin(\fp_pow_0002:fp_pow_inst|Add34~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add34~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add34~30 )); defparam \fp_pow_0002:fp_pow_inst|Add34~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add34~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add34~29_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add34~33_I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[3] ), .cin(\fp_pow_0002:fp_pow_inst|Add34~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add34~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add34~34 )); defparam \fp_pow_0002:fp_pow_inst|Add34~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add34~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add34~33_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add34~41_I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[4] ), .cin(\fp_pow_0002:fp_pow_inst|Add34~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add34~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add34~42 )); defparam \fp_pow_0002:fp_pow_inst|Add34~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add34~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add34~41_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add34~25_I ( .dataa(\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[5] ), .cin(\fp_pow_0002:fp_pow_inst|Add34~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add34~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add34~26 )); defparam \fp_pow_0002:fp_pow_inst|Add34~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add34~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add34~25_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add34~17_I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[6] ), .cin(\fp_pow_0002:fp_pow_inst|Add34~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add34~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add34~18 )); defparam \fp_pow_0002:fp_pow_inst|Add34~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add34~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add34~17_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add34~13_I ( .dataa(\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[7] ), .cin(\fp_pow_0002:fp_pow_inst|Add34~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add34~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add34~14 )); defparam \fp_pow_0002:fp_pow_inst|Add34~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add34~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add34~13_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add34~9_I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[8] ), .cin(\fp_pow_0002:fp_pow_inst|Add34~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add34~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add34~10 )); defparam \fp_pow_0002:fp_pow_inst|Add34~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add34~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add34~9_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add34~5_I ( .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[9] ), .cin(\fp_pow_0002:fp_pow_inst|Add34~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add34~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add34~6 )); defparam \fp_pow_0002:fp_pow_inst|Add34~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add34~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add34~5_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add34~1_I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:redist101_replace_mem_dmem|altera_syncram_idg3:auto_generated|altsyncram_dmb4:altsyncram1|__ALT_INV__dataout_reg[9] ), .cin(\fp_pow_0002:fp_pow_inst|Add34~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add34~1 )); defparam \fp_pow_0002:fp_pow_inst|Add34~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add34~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add34~1_I .lut_mask = "0000FFFF00003333"; dffeas \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add34~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[10] )); defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add34~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[9] )); defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add34~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[8] )); defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add34~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[7] )); defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add34~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[6] )); defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add34~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[5] )); defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add34~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[4] )); defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add34~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[3] )); defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add34~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[2] )); defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add34~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[1] )); defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add34~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[0] )); defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add35~37_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[1] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[0] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add35~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add35~38 )); defparam \fp_pow_0002:fp_pow_inst|Add35~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add35~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add35~37_I .lut_mask = "0000FF0000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add35~29_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[2] ), .cin(\fp_pow_0002:fp_pow_inst|Add35~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add35~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add35~30 )); defparam \fp_pow_0002:fp_pow_inst|Add35~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add35~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add35~29_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add35~33_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[3] ), .cin(\fp_pow_0002:fp_pow_inst|Add35~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add35~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add35~34 )); defparam \fp_pow_0002:fp_pow_inst|Add35~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add35~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add35~33_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add35~41_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[4] ), .cin(\fp_pow_0002:fp_pow_inst|Add35~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add35~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add35~42 )); defparam \fp_pow_0002:fp_pow_inst|Add35~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add35~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add35~41_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add35~25_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[5] ), .cin(\fp_pow_0002:fp_pow_inst|Add35~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add35~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add35~26 )); defparam \fp_pow_0002:fp_pow_inst|Add35~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add35~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add35~25_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add35~21_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[6] ), .cin(\fp_pow_0002:fp_pow_inst|Add35~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add35~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add35~22 )); defparam \fp_pow_0002:fp_pow_inst|Add35~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add35~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add35~21_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add35~17_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[7] ), .cin(\fp_pow_0002:fp_pow_inst|Add35~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add35~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add35~18 )); defparam \fp_pow_0002:fp_pow_inst|Add35~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add35~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add35~17_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add35~13_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[8] ), .cin(\fp_pow_0002:fp_pow_inst|Add35~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add35~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add35~14 )); defparam \fp_pow_0002:fp_pow_inst|Add35~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add35~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add35~13_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add35~9_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[9] ), .cin(\fp_pow_0002:fp_pow_inst|Add35~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add35~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add35~10 )); defparam \fp_pow_0002:fp_pow_inst|Add35~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add35~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add35~9_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add35~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[10] ), .cin(\fp_pow_0002:fp_pow_inst|Add35~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add35~1 ), .cout(\fp_pow_0002:fp_pow_inst|Add35~2 )); defparam \fp_pow_0002:fp_pow_inst|Add35~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add35~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add35~1_I .lut_mask = "0000000000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add35~5_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[10] ), .cin(\fp_pow_0002:fp_pow_inst|Add35~2 ), .sumout(\fp_pow_0002:fp_pow_inst|Add35~5 )); defparam \fp_pow_0002:fp_pow_inst|Add35~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add35~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add35~5_I .lut_mask = "0000000000000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add35~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|Add35~5 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add35~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|Add35~5 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add35~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|Add35~5 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add35~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|Add35~5 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add35~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|Add35~5 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add35~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|Add35~5 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add35~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|Add35~5 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add35~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|Add35~5 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add36~50_I ( .cin(gnd), .sharein(gnd), .cout(\fp_pow_0002:fp_pow_inst|Add36~50 ), .shareout(\fp_pow_0002:fp_pow_inst|Add36~51 )); defparam \fp_pow_0002:fp_pow_inst|Add36~50_I .shared_arith = "on"; defparam \fp_pow_0002:fp_pow_inst|Add36~50_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add36~50_I .lut_mask = "0000FFFF0000FFFF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add36~46_I ( .cin(\fp_pow_0002:fp_pow_inst|Add36~50 ), .sharein(\fp_pow_0002:fp_pow_inst|Add36~51 ), .cout(\fp_pow_0002:fp_pow_inst|Add36~46 ), .shareout(\fp_pow_0002:fp_pow_inst|Add36~47 )); defparam \fp_pow_0002:fp_pow_inst|Add36~46_I .shared_arith = "on"; defparam \fp_pow_0002:fp_pow_inst|Add36~46_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add36~46_I .lut_mask = "0000FFFF00000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add36~42_I ( .cin(\fp_pow_0002:fp_pow_inst|Add36~46 ), .sharein(\fp_pow_0002:fp_pow_inst|Add36~47 ), .cout(\fp_pow_0002:fp_pow_inst|Add36~42 ), .shareout(\fp_pow_0002:fp_pow_inst|Add36~43 )); defparam \fp_pow_0002:fp_pow_inst|Add36~42_I .shared_arith = "on"; defparam \fp_pow_0002:fp_pow_inst|Add36~42_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add36~42_I .lut_mask = "0000FFFF00000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add36~38_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][3] ), .cin(\fp_pow_0002:fp_pow_inst|Add36~42 ), .sharein(\fp_pow_0002:fp_pow_inst|Add36~43 ), .cout(\fp_pow_0002:fp_pow_inst|Add36~38 ), .shareout(\fp_pow_0002:fp_pow_inst|Add36~39 )); defparam \fp_pow_0002:fp_pow_inst|Add36~38_I .shared_arith = "on"; defparam \fp_pow_0002:fp_pow_inst|Add36~38_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add36~38_I .lut_mask = "000000000000AAAA"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add36~33_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][4] ), .cin(\fp_pow_0002:fp_pow_inst|Add36~38 ), .sharein(\fp_pow_0002:fp_pow_inst|Add36~39 ), .sumout(\fp_pow_0002:fp_pow_inst|Add36~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add36~34 ), .shareout(\fp_pow_0002:fp_pow_inst|Add36~35 )); defparam \fp_pow_0002:fp_pow_inst|Add36~33_I .shared_arith = "on"; defparam \fp_pow_0002:fp_pow_inst|Add36~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add36~33_I .lut_mask = "000000000000CCCC"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add36~29_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add36~34 ), .sharein(\fp_pow_0002:fp_pow_inst|Add36~35 ), .sumout(\fp_pow_0002:fp_pow_inst|Add36~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add36~30 ), .shareout(\fp_pow_0002:fp_pow_inst|Add36~31 )); defparam \fp_pow_0002:fp_pow_inst|Add36~29_I .shared_arith = "on"; defparam \fp_pow_0002:fp_pow_inst|Add36~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add36~29_I .lut_mask = "000000000000AAAA"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add36~25_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][6] ), .cin(\fp_pow_0002:fp_pow_inst|Add36~30 ), .sharein(\fp_pow_0002:fp_pow_inst|Add36~31 ), .sumout(\fp_pow_0002:fp_pow_inst|Add36~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add36~26 ), .shareout(\fp_pow_0002:fp_pow_inst|Add36~27 )); defparam \fp_pow_0002:fp_pow_inst|Add36~25_I .shared_arith = "on"; defparam \fp_pow_0002:fp_pow_inst|Add36~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add36~25_I .lut_mask = "000000000000CCCC"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add36~21_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add36~26 ), .sharein(\fp_pow_0002:fp_pow_inst|Add36~27 ), .sumout(\fp_pow_0002:fp_pow_inst|Add36~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add36~22 ), .shareout(\fp_pow_0002:fp_pow_inst|Add36~23 )); defparam \fp_pow_0002:fp_pow_inst|Add36~21_I .shared_arith = "on"; defparam \fp_pow_0002:fp_pow_inst|Add36~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add36~21_I .lut_mask = "0000F0F000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add36~17_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][8] ), .cin(\fp_pow_0002:fp_pow_inst|Add36~22 ), .sharein(\fp_pow_0002:fp_pow_inst|Add36~23 ), .sumout(\fp_pow_0002:fp_pow_inst|Add36~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add36~18 ), .shareout(\fp_pow_0002:fp_pow_inst|Add36~19 )); defparam \fp_pow_0002:fp_pow_inst|Add36~17_I .shared_arith = "on"; defparam \fp_pow_0002:fp_pow_inst|Add36~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add36~17_I .lut_mask = "000000000000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add36~13_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][9] ), .cin(\fp_pow_0002:fp_pow_inst|Add36~18 ), .sharein(\fp_pow_0002:fp_pow_inst|Add36~19 ), .sumout(\fp_pow_0002:fp_pow_inst|Add36~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add36~14 ), .shareout(\fp_pow_0002:fp_pow_inst|Add36~15 )); defparam \fp_pow_0002:fp_pow_inst|Add36~13_I .shared_arith = "on"; defparam \fp_pow_0002:fp_pow_inst|Add36~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add36~13_I .lut_mask = "000000000000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add36~9_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][10] ), .cin(\fp_pow_0002:fp_pow_inst|Add36~14 ), .sharein(\fp_pow_0002:fp_pow_inst|Add36~15 ), .sumout(\fp_pow_0002:fp_pow_inst|Add36~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add36~10 ), .shareout(\fp_pow_0002:fp_pow_inst|Add36~11 )); defparam \fp_pow_0002:fp_pow_inst|Add36~9_I .shared_arith = "on"; defparam \fp_pow_0002:fp_pow_inst|Add36~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add36~9_I .lut_mask = "000000000000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add36~5_I ( .cin(\fp_pow_0002:fp_pow_inst|Add36~10 ), .sharein(\fp_pow_0002:fp_pow_inst|Add36~11 ), .sumout(\fp_pow_0002:fp_pow_inst|Add36~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add36~6 ), .shareout(\fp_pow_0002:fp_pow_inst|Add36~7 )); defparam \fp_pow_0002:fp_pow_inst|Add36~5_I .shared_arith = "on"; defparam \fp_pow_0002:fp_pow_inst|Add36~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add36~5_I .lut_mask = "000000000000FFFF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add36~1_I ( .cin(\fp_pow_0002:fp_pow_inst|Add36~6 ), .sharein(\fp_pow_0002:fp_pow_inst|Add36~7 ), .sumout(\fp_pow_0002:fp_pow_inst|Add36~1 )); defparam \fp_pow_0002:fp_pow_inst|Add36~1_I .shared_arith = "on"; defparam \fp_pow_0002:fp_pow_inst|Add36~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add36~1_I .lut_mask = "000000000000FFFF"; dffeas \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add36~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[12] )); defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[0]~0_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[0] ), .combout(\fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[0]~0_I .lut_mask = "F0F0F0F0F0F0F0F0"; dffeas \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[0]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[1]~DUPLICATE ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[1] )); defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[2]~DUPLICATE ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[2] )); defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[3]~DUPLICATE ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[3] )); defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4]~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4]~DUPLICATE_I .created_from = "Q(redist75_replace_rdcnt_i[4])"; dffeas \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4]~DUPLICATE ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[4] )); defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0]~0_I ( .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "FFFF0000FFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[1] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[1] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[2]~DUPLICATE ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[2] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[3]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4]~DUPLICATE ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[4] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist97_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4248,portadatain_unconnected_wire_4249,portadatain_unconnected_wire_4250,portadatain_unconnected_wire_4251,portadatain_unconnected_wire_4252,portadatain_unconnected_wire_4253,portadatain_unconnected_wire_4254, portadatain_unconnected_wire_4255,portadatain_unconnected_wire_4256,portadatain_unconnected_wire_4257,portadatain_unconnected_wire_4258,portadatain_unconnected_wire_4259,portadatain_unconnected_wire_4260,portadatain_unconnected_wire_4261, portadatain_unconnected_wire_4262,portadatain_unconnected_wire_4263,portadatain_unconnected_wire_4264,portadatain_unconnected_wire_4265,portadatain_unconnected_wire_4266,\fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[12] }), .portaaddr({portaaddr_unconnected_wire_4267,\fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4268,\fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .logical_ram_depth = 21; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .logical_ram_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .last_address = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist78_sticky_ena_q[0]~feeder_I ( .combout(\fp_pow_0002:fp_pow_inst|redist78_sticky_ena_q[0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist78_sticky_ena_q[0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist78_sticky_ena_q[0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist78_sticky_ena_q[0]~feeder_I .lut_mask = "FFFFFFFFFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist78_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist78_sticky_ena_q[0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|redist78_cmpReg_q[0] ), .q(\fp_pow_0002:fp_pow_inst|redist78_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist78_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist78_sticky_ena_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:InvXEQOneAbs_uid163_fpPowrTest_delay|delay_signals[0][0]~0_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:InvXEQOneAbs_uid163_fpPowrTest_delay|delay_signals[0][0]~0 )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:InvXEQOneAbs_uid163_fpPowrTest_delay|delay_signals[0][0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:InvXEQOneAbs_uid163_fpPowrTest_delay|delay_signals[0][0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:InvXEQOneAbs_uid163_fpPowrTest_delay|delay_signals[0][0]~0_I .lut_mask = "F0F0F0F0F0F0F0F0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:InvXEQOneAbs_uid163_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:InvXEQOneAbs_uid163_fpPowrTest_delay|delay_signals[0][0]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:InvXEQOneAbs_uid163_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:InvXEQOneAbs_uid163_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:InvXEQOneAbs_uid163_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "AAAAAAAAAAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[1] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[2] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[3]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[4] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist78_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4269,portadatain_unconnected_wire_4270,portadatain_unconnected_wire_4271,portadatain_unconnected_wire_4272,portadatain_unconnected_wire_4273,portadatain_unconnected_wire_4274,portadatain_unconnected_wire_4275, portadatain_unconnected_wire_4276,portadatain_unconnected_wire_4277,portadatain_unconnected_wire_4278,portadatain_unconnected_wire_4279,portadatain_unconnected_wire_4280,portadatain_unconnected_wire_4281,portadatain_unconnected_wire_4282, portadatain_unconnected_wire_4283,portadatain_unconnected_wire_4284,portadatain_unconnected_wire_4285,portadatain_unconnected_wire_4286,portadatain_unconnected_wire_4287, \fp_pow_0002:fp_pow_inst|dspba_delay:InvXEQOneAbs_uid163_fpPowrTest_delay|delay_signals[0][0] }), .portaaddr({portaaddr_unconnected_wire_4288,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~DUPLICATE , \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4289,\fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_depth = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .last_address = 22; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist116|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist115|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist116|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist116|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist116|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|signRLog0_uid82_fpPowrTest_q_i[0]~I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__finalSumLogsumAHighB_uid72_fpPowrTest_o[45] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist116|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|signRLog0_uid82_fpPowrTest_q_i[0] )); defparam \fp_pow_0002:fp_pow_inst|signRLog0_uid82_fpPowrTest_q_i[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|signRLog0_uid82_fpPowrTest_q_i[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|signRLog0_uid82_fpPowrTest_q_i[0]~I .lut_mask = "3333FFFF3333FFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:signRLog0_uid82_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|signRLog0_uid82_fpPowrTest_q_i[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:signRLog0_uid82_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:signRLog0_uid82_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:signRLog0_uid82_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[14][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:signRLog0_uid82_fpPowrTest_delay|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[14][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[14][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[14][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[13][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|__ALT_INV__delay_signals[14][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[13][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[13][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[13][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[13][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[13][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[13][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[13][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[13][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[13][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[12][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[13][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[12][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[12][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[12][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[11][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[12][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[11][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[11][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[11][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[10][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[11][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[10][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[10][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[10][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[9][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[10][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[9][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[9][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[9][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[8][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[9][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[8][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[8][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[8][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[7][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[8][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[7][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[7][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[7][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[6][0]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|__ALT_INV__delay_signals[7][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[6][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[6][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[6][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[6][0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[6][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[6][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[6][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[6][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[6][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[5][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[6][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[5][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[5][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[5][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[4][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[5][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[4][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[4][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[4][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[3][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[4][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[3][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[3][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[3][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[2][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|__ALT_INV__delay_signals[3][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[2][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[2][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[2][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[2][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[2][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist106|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|signProd_uid106_fpPowrTest_q_i[0]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist129|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__exc_R_uid35_fpPowrTest_q[0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist106|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|signProd_uid106_fpPowrTest_q_i[0] )); defparam \fp_pow_0002:fp_pow_inst|signProd_uid106_fpPowrTest_q_i[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|signProd_uid106_fpPowrTest_q_i[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|signProd_uid106_fpPowrTest_q_i[0]~I .lut_mask = "333333333333CCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|signProd_uid106_fpPowrTest_q_i[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[4][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[4][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[4][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[4][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[3][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[4][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[3][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[3][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[3][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[2][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[3][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[2][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[2][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[2][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[2][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[2][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[2][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[1][0]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[2][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[1][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[1][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[1][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[1][0]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[1][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][43]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][43] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][43]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][43]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[17][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][43] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[17][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[17][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[17][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[17][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[17][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[17][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[17][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[17][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[17][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[16][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[17][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[16][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[16][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[16][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[15][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[16][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[15][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[15][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[15][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[14][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[15][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[14][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[14][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[14][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[13][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[14][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[13][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[13][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[13][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[12][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[13][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[12][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[12][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[12][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[11][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[12][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[11][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[11][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[11][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[10][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[11][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[10][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[10][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[10][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[9][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[10][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[9][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[9][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[9][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[8][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[9][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[8][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[8][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[8][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[7][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[8][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[7][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[7][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[7][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[6][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[7][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[6][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[6][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[6][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[5][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[6][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[5][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[5][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[5][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[4][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|__ALT_INV__delay_signals[5][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[4][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[4][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[4][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[4][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[4][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[4][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[4][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[4][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[4][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[3][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[4][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[3][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[3][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[3][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[2][0]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|__ALT_INV__delay_signals[3][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[2][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[2][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[2][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[2][0]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[2][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|zeroCase6_uid165_fpPowrTest_q_i[0]~0_I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist82_outputreg|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist117_outputreg|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|zeroCase6_uid165_fpPowrTest_q_i[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|zeroCase6_uid165_fpPowrTest_q_i[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|zeroCase6_uid165_fpPowrTest_q_i[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|zeroCase6_uid165_fpPowrTest_q_i[0]~0_I .lut_mask = "0000000000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|infCase5_uid184_fpPowrTest_q_i[0]~I ( .dataa(\fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__zeroCase6_uid165_fpPowrTest_q_i[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|infCase5_uid184_fpPowrTest_q_i[0] )); defparam \fp_pow_0002:fp_pow_inst|infCase5_uid184_fpPowrTest_q_i[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|infCase5_uid184_fpPowrTest_q_i[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|infCase5_uid184_fpPowrTest_q_i[0]~I .lut_mask = "0000000005000500"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:infCase5_uid184_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|infCase5_uid184_fpPowrTest_q_i[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:infCase5_uid184_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:infCase5_uid184_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:infCase5_uid184_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist123_sticky_ena_q[0]~feeder_I ( .combout(\fp_pow_0002:fp_pow_inst|redist123_sticky_ena_q[0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist123_sticky_ena_q[0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist123_sticky_ena_q[0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist123_sticky_ena_q[0]~feeder_I .lut_mask = "FFFFFFFFFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist123_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist123_sticky_ena_q[0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|redist78_cmpReg_q[0] ), .q(\fp_pow_0002:fp_pow_inst|redist123_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist123_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist123_sticky_ena_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|exc_I_uid30_fpPowrTest_q[0]~I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist125|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist124_outputreg|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|exc_I_uid30_fpPowrTest_q[0] )); defparam \fp_pow_0002:fp_pow_inst|exc_I_uid30_fpPowrTest_q[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|exc_I_uid30_fpPowrTest_q[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|exc_I_uid30_fpPowrTest_q[0]~I .lut_mask = "00000F0F00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist123_inputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|exc_I_uid30_fpPowrTest_q[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist123_inputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist123_inputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist123_inputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "AAAAAAAAAAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[1] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~DUPLICATE ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[4] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist123_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4290,portadatain_unconnected_wire_4291,portadatain_unconnected_wire_4292,portadatain_unconnected_wire_4293,portadatain_unconnected_wire_4294,portadatain_unconnected_wire_4295,portadatain_unconnected_wire_4296, portadatain_unconnected_wire_4297,portadatain_unconnected_wire_4298,portadatain_unconnected_wire_4299,portadatain_unconnected_wire_4300,portadatain_unconnected_wire_4301,portadatain_unconnected_wire_4302,portadatain_unconnected_wire_4303, portadatain_unconnected_wire_4304,portadatain_unconnected_wire_4305,portadatain_unconnected_wire_4306,portadatain_unconnected_wire_4307,portadatain_unconnected_wire_4308,\fp_pow_0002:fp_pow_inst|dspba_delay:redist123_inputreg|delay_signals[0][0] }), .portaaddr({portaaddr_unconnected_wire_4309,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~DUPLICATE , \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4310,\fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_depth = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .last_address = 22; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|infCase3_uid191_fpPowrTest_q_i[0]~I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist130_outputreg|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist117_outputreg|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist82_outputreg|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|infCase3_uid191_fpPowrTest_q_i[0] )); defparam \fp_pow_0002:fp_pow_inst|infCase3_uid191_fpPowrTest_q_i[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|infCase3_uid191_fpPowrTest_q_i[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|infCase3_uid191_fpPowrTest_q_i[0]~I .lut_mask = "00000000002A002A"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:infCase3_uid191_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|infCase3_uid191_fpPowrTest_q_i[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:infCase3_uid191_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:infCase3_uid191_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:infCase3_uid191_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[1]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add48~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[1]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[1]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[1]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[1]~DUPLICATE_I .created_from = "Q(redist96_replace_rdcnt_i[1])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[2]~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_eq ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[2] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[1]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[2]~0 )); defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[2]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[2]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[2]~0_I .lut_mask = "0AF50AF5AF50AF50"; dffeas \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[2]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[2] )); defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[3]~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_eq ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[1] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[3] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[3]~1 )); defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[3]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[3]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[3]~1_I .lut_mask = "0000FFFF0AAFF550"; dffeas \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[3]~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[3] )); defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal19~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[3] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|Equal19~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal19~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal19~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal19~0_I .lut_mask = "0000000000500050"; dffeas \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_eq~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal19~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_eq )); defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_eq~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_eq~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add48~0_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_eq ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[1] ), .combout(\fp_pow_0002:fp_pow_inst|Add48~0 )); defparam \fp_pow_0002:fp_pow_inst|Add48~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add48~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add48~0_I .lut_mask = "F00F0FF0F00F0FF0"; dffeas \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add48~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[1] )); defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal18~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[3] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|Equal18~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal18~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal18~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal18~0_I .lut_mask = "0000000000A000A0"; dffeas \fp_pow_0002:fp_pow_inst|redist96_cmpReg_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal18~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist96_cmpReg_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist96_cmpReg_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist96_cmpReg_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0]~0_I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_sticky_ena_q[0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_cmpReg_q[0] ), .combout(\fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0]~0_I .lut_mask = "00FF00FFFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add26~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[4] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[32]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[4] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[32]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[32]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[32]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[32]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add26~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[5] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[32]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[32] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[32]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add26~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[3] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[31]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[3] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[31]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[31]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[31]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[31]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[31]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[31] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[31]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add26~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[2] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[30]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[2] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[30]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[30]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[30]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[30]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[30]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[30] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[30]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add26~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[1] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[29]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[1] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[29]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[29]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[29]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[29]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[29]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[29] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[29]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[52]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[52] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[52]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[52]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][51]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[52] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][51] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][51]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][51]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[28]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][51] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[28]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[28]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[28]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[28]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[28]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[28] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[28]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[51]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[51] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[51]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[51]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][50]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[51] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][50] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][50]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][50]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[27]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][50] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[27]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[27]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[27]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[27]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[27]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][51] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[27] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[27]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[50]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[50] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[50]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[50]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][49]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[50] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][49] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][49]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][49]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[26]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][49] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[26]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[26]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[26]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[26]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[26]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][50] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[26] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[26]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[49]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[49] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[49]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[49]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][48]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[49] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][48] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][48]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][48]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[25]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][48] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[25]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[25]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[25]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[25]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[25]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][49] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[25] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[48]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[48] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[48]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[48]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][47]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[48] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][47]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][47]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][47]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][47]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][47]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][47]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][47] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][47]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][47]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[24]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][47] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[24]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[24]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[24]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[24]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[24]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][48] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[24] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[24]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[47]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[47] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[47]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[47]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][46]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[47] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][46]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][46]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][46]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][46]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][46]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][46]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][46] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][46]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][46]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[23]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][46] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[23]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[23]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[23]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[23]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[23]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][47] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[23] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[23]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[46]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[46] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[46]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[46]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][45]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[46] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][45] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][45]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][45]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[22]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][45] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[22]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[22]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[22]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[22]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[22]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][46] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[22] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[45]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[45] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[45]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[45]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][44]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[45] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][44]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][44]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][44]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][44]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][44]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][44]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][44] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][44]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][44]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[21]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][44] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[21]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[21]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[21]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[21]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[21]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][45] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[21] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[44]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[44] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[44]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[44]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][43]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[44] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][43] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][43]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][43]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[20]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][43] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[20]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[20]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[20]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[20]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[20]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][44] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[20] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[43]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[43] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[43]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[43]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][42]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[43] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][42]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][42]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][42]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][42]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][42]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][42]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][42] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][42]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[19]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][42] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[19]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[19]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[19]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[19]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[19]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][43] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[19] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[42]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[42] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[42]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][41]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[42] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][41]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][41]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][41]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][41]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][41]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][41]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][41] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][41]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[18]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][41] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[18]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[18]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[18]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[18]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[18]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][42] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[18] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[41]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[41] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[41]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][40]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[41] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][40] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][40]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[17]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][40] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[17]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[17]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[17]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[17]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[17]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][41] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[17] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[40]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[40] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[40]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][39]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[40] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][39] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][39]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[16]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][39] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[16]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[16]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[16]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[16]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[16]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][40] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[16] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[39]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[39] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[39]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][38]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[39] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][38]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][38]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][38]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][38]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][38]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][38]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][38] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][38]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[15]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][38] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[15]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[15]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[15]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[15]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[15]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][39] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[15] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[38]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~61 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[38] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[38]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][37]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[38] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][37]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][37]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][37]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][37]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][37]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][37] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][37]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[14]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][37] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[14]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[14]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[14]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[14]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[14]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][38] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[14] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~65 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[37] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[37]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][36]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[37] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][36] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][36]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[13]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][36] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[13]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[13]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[13]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[13]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[13]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][37] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[13] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[36]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~69 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[36] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[36]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][35]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[36] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][35]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][35]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][35]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][35]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][35]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][35]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[12]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][35] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[12]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[12]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[12]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[12]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[12]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][36] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[12] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~73 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[35] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[35]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[35] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[11]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][34] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[11]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[11]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[11]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[11]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[11]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][35] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[11] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~77 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[34] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][33]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[34] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][33]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][33]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][33]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][33]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][33]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[10]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][33] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[10]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[10]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[10]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[10]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[10]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][34] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[10] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~81 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[33] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][32]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[33] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][32]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][32]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][32]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][32]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][32]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[9]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][32] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[9]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[9]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[9]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[9]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[9]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[9]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][33] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[9]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[9]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[9]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[9]~DUPLICATE_I .created_from = "Q(normProdYLogX_uid98_fpPowrTest_q[9])"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~85 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[32] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][31]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[32] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][31]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][31]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][31]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][31]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][31]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[8]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][31] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[8]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[8]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[8]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[8]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[8]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][32] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[8] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~89 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[31] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][30]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[31] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][30]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][30]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][30]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][30]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][30]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[7]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][30] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[7]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[7]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][31] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[7] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~93 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[30] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[30]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[30] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[6]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][29] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[6]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[6]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][30] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[6] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~97 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[29] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][28]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[29] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][28]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][28]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][28]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][28]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][28]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[5]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][28] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[5]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[5]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][29] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[5] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~109 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[28] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][27]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[28] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][27]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][27]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][27]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][27]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][27]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[4]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][27] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[4]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[4]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][28] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[4] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~117 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[27] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][26]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[27] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][26]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][26]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][26]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][26]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][26]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][26] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[3]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][27] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[3] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~113 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[26] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][25]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[26] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][25]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][25]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][25]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][25]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][25]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[2]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][25] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[2]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[2]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][26] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[2] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~105 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[25] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][24]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[25] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][24]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][24]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][24]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][24]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][24]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[1]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][24] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[1]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[1]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][25] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[1] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add25~101 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[24] )); defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][23]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodYLogX_uid93_fpPowrTest_result_add_0_0_p1_of_2_o[24] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][23]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][23]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][23]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][23]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][23]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[0]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|__ALT_INV__delay_signals[0][23] ), .combout(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[0]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][24] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[0] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~137_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[0] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add27~137 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~138 )); defparam \fp_pow_0002:fp_pow_inst|Add27~137_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~137_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~137_I .lut_mask = "0000A5A500005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~133_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[1] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~138 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~133 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~134 )); defparam \fp_pow_0002:fp_pow_inst|Add27~133_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~133_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~133_I .lut_mask = "0000FFFF00005A5A"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~129_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[2] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~134 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~129 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~130 )); defparam \fp_pow_0002:fp_pow_inst|Add27~129_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~129_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~129_I .lut_mask = "0000FFFF00005A5A"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~125_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[3] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~130 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~125 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~126 )); defparam \fp_pow_0002:fp_pow_inst|Add27~125_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~125_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~125_I .lut_mask = "0000AA5500000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~121_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[4] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~126 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~121 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~122 )); defparam \fp_pow_0002:fp_pow_inst|Add27~121_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~121_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~121_I .lut_mask = "0000FFFF00005A5A"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~117_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[5] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~122 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~117 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~118 )); defparam \fp_pow_0002:fp_pow_inst|Add27~117_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~117_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~117_I .lut_mask = "0000FFFF00005A5A"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~113_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[6] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~118 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~113 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~114 )); defparam \fp_pow_0002:fp_pow_inst|Add27~113_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~113_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~113_I .lut_mask = "0000FFFF00005A5A"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~109_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[7] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~114 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~109 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~110 )); defparam \fp_pow_0002:fp_pow_inst|Add27~109_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~109_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~109_I .lut_mask = "0000AA5500000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~105_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[8] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~110 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~105 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~106 )); defparam \fp_pow_0002:fp_pow_inst|Add27~105_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~105_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~105_I .lut_mask = "0000FFFF00005A5A"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~101_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[9]~DUPLICATE ), .cin(\fp_pow_0002:fp_pow_inst|Add27~106 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~101 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~102 )); defparam \fp_pow_0002:fp_pow_inst|Add27~101_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~101_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~101_I .lut_mask = "0000FFFF00005A5A"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~97_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[10] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~102 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~97 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~98 )); defparam \fp_pow_0002:fp_pow_inst|Add27~97_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~97_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~97_I .lut_mask = "0000FFFF00005A5A"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~93_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[11] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~98 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~93 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~94 )); defparam \fp_pow_0002:fp_pow_inst|Add27~93_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~93_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~93_I .lut_mask = "0000FFFF000055AA"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~89_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[12] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~94 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~89 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~90 )); defparam \fp_pow_0002:fp_pow_inst|Add27~89_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~89_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~89_I .lut_mask = "0000FFFF00005A5A"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~85_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[13] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~90 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~85 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~86 )); defparam \fp_pow_0002:fp_pow_inst|Add27~85_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~85_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~85_I .lut_mask = "0000FFFF00005A5A"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~81_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[14] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~86 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~81 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~82 )); defparam \fp_pow_0002:fp_pow_inst|Add27~81_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~81_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~81_I .lut_mask = "0000AA5500000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~77_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[15] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~82 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~78 )); defparam \fp_pow_0002:fp_pow_inst|Add27~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~77_I .lut_mask = "0000FFFF00005A5A"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~73_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[16] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~73 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~74 )); defparam \fp_pow_0002:fp_pow_inst|Add27~73_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~73_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~73_I .lut_mask = "0000FFFF00005A5A"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~69_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[17] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~74 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~69 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~70 )); defparam \fp_pow_0002:fp_pow_inst|Add27~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~69_I .lut_mask = "0000FFFF000055AA"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~53_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[18] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~70 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~54 )); defparam \fp_pow_0002:fp_pow_inst|Add27~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~53_I .lut_mask = "0000AA5500000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~57_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[19] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~57 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~58 )); defparam \fp_pow_0002:fp_pow_inst|Add27~57_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~57_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~57_I .lut_mask = "0000FFFF00005A5A"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~61_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[20] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~58 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~62 )); defparam \fp_pow_0002:fp_pow_inst|Add27~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~61_I .lut_mask = "0000FFFF00003C3C"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~65_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[21] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~65 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~66 )); defparam \fp_pow_0002:fp_pow_inst|Add27~65_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~65_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~65_I .lut_mask = "0000FFFF00003C3C"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~49_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[22] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~66 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~50 )); defparam \fp_pow_0002:fp_pow_inst|Add27~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~49_I .lut_mask = "0000FFFF00003C3C"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~45_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[23] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~46 )); defparam \fp_pow_0002:fp_pow_inst|Add27~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~45_I .lut_mask = "0000FFFF00003C3C"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~9_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[24] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~10 )); defparam \fp_pow_0002:fp_pow_inst|Add27~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~9_I .lut_mask = "0000FFFF00003C3C"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~13_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[25] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~14 )); defparam \fp_pow_0002:fp_pow_inst|Add27~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~13_I .lut_mask = "0000FFFF000033CC"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~17_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[26] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~18 )); defparam \fp_pow_0002:fp_pow_inst|Add27~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~17_I .lut_mask = "0000FFFF00003C3C"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~21_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[27] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~22 )); defparam \fp_pow_0002:fp_pow_inst|Add27~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~21_I .lut_mask = "0000FFFF00003C3C"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~5_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[28] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~6 )); defparam \fp_pow_0002:fp_pow_inst|Add27~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~5_I .lut_mask = "0000FFFF00003C3C"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~25_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[29] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~26 )); defparam \fp_pow_0002:fp_pow_inst|Add27~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~25_I .lut_mask = "0000FFFF00003C3C"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~37_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[30] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~38 )); defparam \fp_pow_0002:fp_pow_inst|Add27~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~37_I .lut_mask = "0000FFFF00003C3C"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~33_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[31] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~34 )); defparam \fp_pow_0002:fp_pow_inst|Add27~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~33_I .lut_mask = "0000FFFF000033CC"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~41_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__normProdYLogX_uid98_fpPowrTest_q[32] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~42 )); defparam \fp_pow_0002:fp_pow_inst|Add27~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~41_I .lut_mask = "0000FFFF00003C3C"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~29_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add27~30 )); defparam \fp_pow_0002:fp_pow_inst|Add27~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~29_I .lut_mask = "0000FFFF0000CCCC"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add27~1_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:signProd_uid106_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .cin(\fp_pow_0002:fp_pow_inst|Add27~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add27~1 )); defparam \fp_pow_0002:fp_pow_inst|Add27~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add27~1_I .lut_mask = "0000FF0000000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[41]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[41] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[41]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~2 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~2_I .lut_mask = "1111111157775777"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[40]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[40] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[40]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~8_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~8 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~8_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~8_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~8_I .lut_mask = "6667666739193919"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[39]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~8 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[39] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[39]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~3_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~3 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~3_I .lut_mask = "133E133EC383C383"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[38]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~3 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[38] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[38]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~9_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~9 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~9_I .lut_mask = "42F442F43D0B3D0B"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[37] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[37]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~0 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~0_I .lut_mask = "43964396C396C396"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[36]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[36] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[36]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~40_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~40 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~40_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~40_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~40_I .lut_mask = "00150015FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist46|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][36]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~40 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][36] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][36]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~39_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~39 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~39_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~39_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~39_I .lut_mask = "05AA05AA05A815A0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~39 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][35]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~5 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~5_I .lut_mask = "5F005F00FF00FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~6_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram6~5 ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~6 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~6_I .lut_mask = "0FF00FF00FF00FF0"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~6 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[35] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[35]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~1 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~1_I .lut_mask = "463B463966396239"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~4_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~4 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~4_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~4_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~4_I .lut_mask = "3FFD3FFDC400C400"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~4 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[34] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~10_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~10 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~10_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~10_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~10_I .lut_mask = "3DC23DC23BC43BC4"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~10 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[33] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~3_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~3 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~3_I .lut_mask = "0FCF30187030EFF7"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~3 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~0 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~0_I .lut_mask = "17C3C36887C1E178"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~1 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~1_I .lut_mask = "1E1E1E1E58785878"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[32] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~2 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~2_I .lut_mask = "2BD554AB99466299"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~7_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~7 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~7_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~7_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~7_I .lut_mask = "3226322699BB99BB"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~7 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[31] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~38_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~38 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~38_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~38_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~38_I .lut_mask = "5BAAAA246555559A"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~38 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~11_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~11 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~11_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~11_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~11_I .lut_mask = "16361636C993C993"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~11 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[30] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~4_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~4 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~4_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~4_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~4_I .lut_mask = "1EA55A8686A59EA5"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~4 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~12_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~12 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~12_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~12_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~12_I .lut_mask = "658E658E58E558E5"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~12 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[29] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~5 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~5_I .lut_mask = "77108CFF3108CE73"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~13_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~13 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~13_I .lut_mask = "496C496C6C966C96"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[28] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~37_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~37 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~37_I .lut_mask = "67733118988CE6E7"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~6_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~6 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~6_I .lut_mask = "544AAFF5522BA550"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~6 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~36_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~36 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~36_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~36_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~36_I .lut_mask = "3C2B2BC23D4343D4"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~36 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~14_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~14 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~14_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~14_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~14_I .lut_mask = "2FD42FD44AA54AA5"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~14 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[25] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~15_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~15 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~15_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~15_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~15_I .lut_mask = "30DB30DBCF24CF24"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~15 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[24] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~35_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~35 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~35_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~35_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~35_I .lut_mask = "1EE7799E18866118"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~35 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~34_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~34 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~34_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~34_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~34_I .lut_mask = "3D6B6BD6D6BDBD6B"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~34 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~16_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~16 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~16_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~16_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~16_I .lut_mask = "33CC33CC3CC33CC3"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~16 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[23] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[23]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~5 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[22] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~33_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~33 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~33_I .lut_mask = "56BDBD6B6BD6D6BD"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~17_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~17 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~17_I .lut_mask = "400040003FFF3FFF"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[21] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~9_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~9 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~9_I .lut_mask = "9988998888668866"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~7_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~7 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~7_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~7_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~7_I .lut_mask = "6611661111881188"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~8_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~8 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~8_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~8_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~8_I .lut_mask = "8686868661616161"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~10_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram5~9 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram5~7 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram5~8 ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~10 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~10_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~10_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~10_I .lut_mask = "ACF0ACF0AC0FAC0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~10 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~32_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~32 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~32_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~32_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~32_I .lut_mask = "54ADAB524AD4F5AB"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~32 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~18_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~18 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~18_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~18_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~18_I .lut_mask = "432F432FC30BC30B"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~18 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[20] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~19_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~19 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~19_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~19_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~19_I .lut_mask = "61E361E3C387C387"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~19 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~11_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~11 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~11_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~11_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~11_I .lut_mask = "3634C9DB6C4DB2B6"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~11 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~12_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~12 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~12_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~12_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~12_I .lut_mask = "4699669C629CB966"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~12 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~20_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~20 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~20_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~20_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~20_I .lut_mask = "189A189AAEA6AEA6"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~20 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~13_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~13 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~13_I .lut_mask = "0381FC7E7E7E0381"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~21_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~21 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~21_I .lut_mask = "49CB49CB362C362C"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~14_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~14 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~14_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~14_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~14_I .lut_mask = "52B55A5A96A55A52"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~14 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~22_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~22 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~22_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~22_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~22_I .lut_mask = "65A765A7A51AA51A"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~22 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~23_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~23 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~23_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~23_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~23_I .lut_mask = "34D234D2CB4DCB4D"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~23 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~31_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~31 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~31_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~31_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~31_I .lut_mask = "54DDD59D2B222A42"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~31 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~15_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~15 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~15_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~15_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~15_I .lut_mask = "4C3032CFFB0C04B3"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~15 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~24_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~24 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~24_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~24_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~24_I .lut_mask = "4B2C4B2C6D346D34"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~24 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~25_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~25 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~25_I .lut_mask = "6798679851E651E6"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~16_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~16 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~16_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~16_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~16_I .lut_mask = "4CC3C9C3362C346C"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~16 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~17_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~17 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~17_I .lut_mask = "6AA1575AE8A5567A"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~18_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~18 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~18_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~18_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~18_I .lut_mask = "4F20B2DFF24D04F2"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~18 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~26_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~26 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~26_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~26_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~26_I .lut_mask = "32CB32CBCB2CCB2C"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~26 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~19_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~19 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~19_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~19_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~19_I .lut_mask = "1839E786969C61E7"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~19 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~27_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~27 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~27_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~27_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~27_I .lut_mask = "17E917E91E811E81"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~27 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~30_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~30 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~30_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~30_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~30_I .lut_mask = "615A791E8EE5A771"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~30 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~20_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~20 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~20_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~20_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~20_I .lut_mask = "300DDBB2DBB00DCB"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~20 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~28_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~28 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~28_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~28_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~28_I .lut_mask = "5A5AA4A46565DADA"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~28 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~29_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~29 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~29_I .lut_mask = "3DC629966B9C4239"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~29_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~29 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~29_I .lut_mask = "077E077EE107E107"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~30_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~30 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~30_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~30_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~30_I .lut_mask = "3996399663296329"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~30 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~28_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~28 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~28_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~28_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~28_I .lut_mask = "01EC3781EC3781EC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~28 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~21_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram5~9 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram5~7 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram5~8 ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~21 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~21_I .lut_mask = "A3F5A3F5A305A305"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~31_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~31 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~31_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~31_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~31_I .lut_mask = "52AF52AFB54AB54A"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~31 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~22_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~22 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~22_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~22_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~22_I .lut_mask = "669871E679669871"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~22 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~32_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~32 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~32_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~32_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~32_I .lut_mask = "05A005F0FA5F5A0F"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~32 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~23_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~23 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~23_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~23_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~23_I .lut_mask = "362CD3926DC9366C"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~23 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~33_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~33 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~33_I .lut_mask = "692D692D69A569A5"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~27_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~27 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~27_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~27_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~27_I .lut_mask = "5A2DB45B2DB05A2D"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~27 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~34_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~34 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~34_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~34_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~34_I .lut_mask = "44BB44BBCC33CC33"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~34 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~35_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~35 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~35_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~35_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~35_I .lut_mask = "7777777788888888"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~35 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~24_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~24 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~24_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~24_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~24_I .lut_mask = "18866159799AE769"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~24 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram6~36_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist45|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram6~36 )); defparam \fp_pow_0002:fp_pow_inst|Ram6~36_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~36_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram6~36_I .lut_mask = "6666666666666666"; dffeas \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram6~36 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] )); defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~25_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~25 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~25_I .lut_mask = "711CC7381CC3710E"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist43|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~165_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][0] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add30~165 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~166 )); defparam \fp_pow_0002:fp_pow_inst|Add30~165_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~165_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~165_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~161_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][1] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~166 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~161 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~162 )); defparam \fp_pow_0002:fp_pow_inst|Add30~161_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~161_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~161_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~157_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~162 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~157 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~158 )); defparam \fp_pow_0002:fp_pow_inst|Add30~157_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~157_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~157_I .lut_mask = "000000FF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~153_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~158 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~153 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~154 )); defparam \fp_pow_0002:fp_pow_inst|Add30~153_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~153_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~153_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~149_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~154 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~149 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~150 )); defparam \fp_pow_0002:fp_pow_inst|Add30~149_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~149_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~149_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~145_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~150 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~145 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~146 )); defparam \fp_pow_0002:fp_pow_inst|Add30~145_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~145_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~145_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~141_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][6] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~146 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~141 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~142 )); defparam \fp_pow_0002:fp_pow_inst|Add30~141_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~141_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~141_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~137_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][7] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~142 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~137 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~138 )); defparam \fp_pow_0002:fp_pow_inst|Add30~137_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~137_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~137_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~133_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][8] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~138 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~133 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~134 )); defparam \fp_pow_0002:fp_pow_inst|Add30~133_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~133_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~133_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~129_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][9] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~134 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~129 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~130 )); defparam \fp_pow_0002:fp_pow_inst|Add30~129_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~129_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~129_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~125_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][10] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~130 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~125 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~126 )); defparam \fp_pow_0002:fp_pow_inst|Add30~125_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~125_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~125_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~121_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][11] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[29] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~126 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~121 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~122 )); defparam \fp_pow_0002:fp_pow_inst|Add30~121_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~121_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~121_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~117_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[30] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][12] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~122 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~117 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~118 )); defparam \fp_pow_0002:fp_pow_inst|Add30~117_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~117_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~117_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~113_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][13] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~118 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~113 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~114 )); defparam \fp_pow_0002:fp_pow_inst|Add30~113_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~113_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~113_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~109_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][14] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~114 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~109 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~110 )); defparam \fp_pow_0002:fp_pow_inst|Add30~109_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~109_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~109_I .lut_mask = "0000FF0000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~105_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][15] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~110 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~105 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~106 )); defparam \fp_pow_0002:fp_pow_inst|Add30~105_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~105_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~105_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~101_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][16] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~106 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~101 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~102 )); defparam \fp_pow_0002:fp_pow_inst|Add30~101_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~101_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~101_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~97_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][17] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~102 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~97 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~98 )); defparam \fp_pow_0002:fp_pow_inst|Add30~97_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~97_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~97_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~93_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][18] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~98 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~93 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~94 )); defparam \fp_pow_0002:fp_pow_inst|Add30~93_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~93_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~93_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~89_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][19] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~94 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~89 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~90 )); defparam \fp_pow_0002:fp_pow_inst|Add30~89_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~89_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~89_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~85_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][20] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[20] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~90 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~85 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~86 )); defparam \fp_pow_0002:fp_pow_inst|Add30~85_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~85_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~85_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~81_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[21] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][21] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~86 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~81 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~82 )); defparam \fp_pow_0002:fp_pow_inst|Add30~81_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~81_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~81_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~77_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[22] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][22] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~82 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~78 )); defparam \fp_pow_0002:fp_pow_inst|Add30~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~77_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~73_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][23] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[23] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~73 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~74 )); defparam \fp_pow_0002:fp_pow_inst|Add30~73_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~73_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~73_I .lut_mask = "0000FF0000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~69_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[24] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~74 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~69 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~70 )); defparam \fp_pow_0002:fp_pow_inst|Add30~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~69_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~65_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][25] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[25] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~70 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~65 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~66 )); defparam \fp_pow_0002:fp_pow_inst|Add30~65_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~65_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~65_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~61_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[28] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][26] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~66 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~62 )); defparam \fp_pow_0002:fp_pow_inst|Add30~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~61_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~57_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][27] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[29] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~57 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~58 )); defparam \fp_pow_0002:fp_pow_inst|Add30~57_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~57_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~57_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~53_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][28] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[28] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~58 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~54 )); defparam \fp_pow_0002:fp_pow_inst|Add30~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~53_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~49_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][29] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[29] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~50 )); defparam \fp_pow_0002:fp_pow_inst|Add30~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~49_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~45_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][30] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[30] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~46 )); defparam \fp_pow_0002:fp_pow_inst|Add30~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~45_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~29_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][31] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[31] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~30 )); defparam \fp_pow_0002:fp_pow_inst|Add30~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~29_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~9_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][32] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[32] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~10 )); defparam \fp_pow_0002:fp_pow_inst|Add30~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~9_I .lut_mask = "0000FF0000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~41_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[33] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][33] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~42 )); defparam \fp_pow_0002:fp_pow_inst|Add30~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~41_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~21_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][34] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[34] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~22 )); defparam \fp_pow_0002:fp_pow_inst|Add30~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~21_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~25_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][35] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[35] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~26 )); defparam \fp_pow_0002:fp_pow_inst|Add30~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~25_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[36] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist43|__ALT_INV__delay_signals[0][36] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~6 )); defparam \fp_pow_0002:fp_pow_inst|Add30~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~5_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~37_I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[37] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~38 )); defparam \fp_pow_0002:fp_pow_inst|Add30~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~37_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~17_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[38] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~18 )); defparam \fp_pow_0002:fp_pow_inst|Add30~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~17_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~33_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[39] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~34 )); defparam \fp_pow_0002:fp_pow_inst|Add30~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~33_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~13_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[40] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add30~14 )); defparam \fp_pow_0002:fp_pow_inst|Add30~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~13_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add30~1_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p5_uid333_qTimesOOlog2Ext_uid115_fpPowrTest_q[41] ), .cin(\fp_pow_0002:fp_pow_inst|Add30~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add30~1 )); defparam \fp_pow_0002:fp_pow_inst|Add30~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add30~1_I .lut_mask = "0000FFFF00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][42]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][42] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][42]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][41]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][41] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][41]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][40]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][40] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][40]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][39]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][39] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][39]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][38]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][38] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][38]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][37] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][37]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][36]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][36] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][36]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][35]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][34]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][33]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][32]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~65 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~57 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~61 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~34_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~34 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~34_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~34_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~34_I .lut_mask = "01FF01FF05FF05FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist47|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~34 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[31] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~33_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~33 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~33_I .lut_mask = "1111AAA81115A8A8"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[30] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~0 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~0_I .lut_mask = "073E073CF00FE00F"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[29] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~1 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~1_I .lut_mask = "18CE19CC7731E733"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[28] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~2 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~2_I .lut_mask = "49366CB2C92C6C36"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[27] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~3_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~3 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~3_I .lut_mask = "2BD5994654AB6299"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~3 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[26] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~32_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~32 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~32_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~32_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~32_I .lut_mask = "7A7E81A00581FA7E"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~32 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[25] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~85 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~77 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~81 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~73 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~89 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~25_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~25 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~25_I .lut_mask = "01FF03FF01FF03FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~69 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist48|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[25] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~24_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~24 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~24_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~24_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~24_I .lut_mask = "0F0E0F0C00F010F0"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~24 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[24] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~4_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~4 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~4_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~4_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~4_I .lut_mask = "2D69694AA529AD69"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~4 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[24] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~5 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~5_I .lut_mask = "6363C7E361396361"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[23] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~0 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~0_I .lut_mask = "333244CC00CCFFB3"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[23] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~1 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~1_I .lut_mask = "18CE19CC7731E733"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[22] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~31_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~31 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~31_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~31_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~31_I .lut_mask = "54BF02D4AB40F5AB"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~31 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[22] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~2 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~2_I .lut_mask = "24BAAA5B5F4545A0"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[21] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~6_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~6 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~6_I .lut_mask = "544AADD4566AA556"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~6 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[21] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~3_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~3 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~3_I .lut_mask = "611E8EE1E5181EE5"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~3 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[20] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~30_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~30 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~30_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~30_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~30_I .lut_mask = "3624DB92246D92B6"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~30 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[20] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~29_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~29 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~29_I .lut_mask = "366DDBB624499224"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~23_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~23 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~23_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~23_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~23_I .lut_mask = "399969B994969994"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~23 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~4_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~4 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~4_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~4_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~4_I .lut_mask = "5A9A654559DAA465"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~4 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~28_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~28 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~28_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~28_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~28_I .lut_mask = "1EE7799EE7799EE7"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~28 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~5 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~5_I .lut_mask = "5DA204DF4DBA20DD"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~27_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~27 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~27_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~27_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~27_I .lut_mask = "366DDBB6DBB66DDB"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~27 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~22_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~22 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~22_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~22_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~22_I .lut_mask = "5542BD54AADD42AB"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~22 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~8_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~8 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~8_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~8_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~8_I .lut_mask = "8866886666116611"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~9_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~9 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~9_I .lut_mask = "A5A0A5A0A05AA05A"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~7_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~7 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~7_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~7_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~7_I .lut_mask = "6611661111881188"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~10_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram4~8 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram4~9 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram4~7 ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~10 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~10_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~10_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~10_I .lut_mask = "F399F399C099C099"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~10 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~26_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~26 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~26_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~26_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~26_I .lut_mask = "333CC9B3C9B33CC9"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~26 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~6_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~6 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~6_I .lut_mask = "11E8E8761789E876"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~6 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~11_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~11 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~11_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~11_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~11_I .lut_mask = "0FF15A875A8FF11A"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~11 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~21_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~21 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~21_I .lut_mask = "0137EC81EC8137EC"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~12_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~12 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~12_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~12_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~12_I .lut_mask = "0F5A70E5F1870E58"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~12 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~20_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~20 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~20_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~20_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~20_I .lut_mask = "1EE71886799E6118"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~20 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~13_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~13 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~13_I .lut_mask = "15AA956A769956A9"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~19_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~19 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~19_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~19_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~19_I .lut_mask = "679E79E779E79E79"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~19 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~14_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~14 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~14_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~14_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~14_I .lut_mask = "4333C2C39CCC3CBC"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~14 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~18_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~18 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~18_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~18_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~18_I .lut_mask = "1E79E79EE79E79E7"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~18 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~17_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~17 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~17_I .lut_mask = "679E79E769C69C69"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~25_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~25 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~25_I .lut_mask = "700EE1F05A0FF078"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~16_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~16 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~16_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~16_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~16_I .lut_mask = "0E58E58EF1AF1AF1"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~16 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~15_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~15 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~15_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~15_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~15_I .lut_mask = "2B54A946629D6295"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~15 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~7_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~7 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~7_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~7_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~7_I .lut_mask = "544A5AABAFB5B552"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~7 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~16_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~16 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~16_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~16_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~16_I .lut_mask = "2BA9999D54466262"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~16 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~17_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~17 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~17_I .lut_mask = "65A5869EE5A7961A"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~8_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~8 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~8_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~8_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~8_I .lut_mask = "1EE1711E1AE7E118"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~8 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~9_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~9 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~9_I .lut_mask = "20DF45BA5F20FA45"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~18_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~18 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~18_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~18_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~18_I .lut_mask = "7C3E81C81381FC7E"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~18 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~19_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~19 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~19_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~19_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~19_I .lut_mask = "0E78A75AA51E7187"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~19 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~10_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~10 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~10_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~10_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~10_I .lut_mask = "25659ABAA4655A9A"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~10 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~15_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~15 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~15_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~15_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~15_I .lut_mask = "730CEF1000EFF708"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~15 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~24_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~24 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~24_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~24_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~24_I .lut_mask = "0EA7E571785A1EA7"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~24 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~20_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~20 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~20_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~20_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~20_I .lut_mask = "3D6B29429439BD69"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~20 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~11_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~11 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~11_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~11_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~11_I .lut_mask = "73E318180C18E7C7"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~11 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~12_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~12 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~12_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~12_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~12_I .lut_mask = "6EEA11151517E8A8"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~12 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~23_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~23 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~23_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~23_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~23_I .lut_mask = "3624DB92DB92246D"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~23 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~13_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~13 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~13_I .lut_mask = "399DB994949696D6"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~22_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~22 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~22_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~22_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~22_I .lut_mask = "5B6D492449246DB6"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~22 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram4~21_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram4~8 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist47|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram4~9 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram4~7 ), .combout(\fp_pow_0002:fp_pow_inst|Ram4~21 )); defparam \fp_pow_0002:fp_pow_inst|Ram4~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram4~21_I .lut_mask = "E023E023EC2FEC2F"; dffeas \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram4~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] )); defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram3~14_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist48|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram3~14 )); defparam \fp_pow_0002:fp_pow_inst|Ram3~14_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~14_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram3~14_I .lut_mask = "52B4D0ADBD0B2F4A"; dffeas \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram3~14 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] )); defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~129_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add29~129 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~130 )); defparam \fp_pow_0002:fp_pow_inst|Add29~129_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~129_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~129_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~125_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~130 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~125 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~126 )); defparam \fp_pow_0002:fp_pow_inst|Add29~125_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~125_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~125_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~121_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~126 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~121 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~122 )); defparam \fp_pow_0002:fp_pow_inst|Add29~121_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~121_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~121_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~117_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~122 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~117 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~118 )); defparam \fp_pow_0002:fp_pow_inst|Add29~117_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~117_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~117_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~113_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~118 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~113 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~114 )); defparam \fp_pow_0002:fp_pow_inst|Add29~113_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~113_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~113_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~109_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~114 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~109 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~110 )); defparam \fp_pow_0002:fp_pow_inst|Add29~109_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~109_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~109_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~105_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~110 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~105 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~106 )); defparam \fp_pow_0002:fp_pow_inst|Add29~105_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~105_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~105_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~101_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~106 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~101 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~102 )); defparam \fp_pow_0002:fp_pow_inst|Add29~101_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~101_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~101_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~97_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~102 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~97 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~98 )); defparam \fp_pow_0002:fp_pow_inst|Add29~97_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~97_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~97_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~93_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~98 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~93 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~94 )); defparam \fp_pow_0002:fp_pow_inst|Add29~93_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~93_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~93_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~89_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~94 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~89 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~90 )); defparam \fp_pow_0002:fp_pow_inst|Add29~89_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~89_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~89_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~85_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~90 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~85 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~86 )); defparam \fp_pow_0002:fp_pow_inst|Add29~85_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~85_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~85_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~81_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~86 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~81 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~82 )); defparam \fp_pow_0002:fp_pow_inst|Add29~81_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~81_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~81_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~77_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~82 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~78 )); defparam \fp_pow_0002:fp_pow_inst|Add29~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~77_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~73_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~73 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~74 )); defparam \fp_pow_0002:fp_pow_inst|Add29~73_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~73_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~73_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~69_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~74 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~69 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~70 )); defparam \fp_pow_0002:fp_pow_inst|Add29~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~69_I .lut_mask = "0000CCCC00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~65_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~70 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~65 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~66 )); defparam \fp_pow_0002:fp_pow_inst|Add29~65_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~65_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~65_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~61_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~66 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~62 )); defparam \fp_pow_0002:fp_pow_inst|Add29~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~61_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~57_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~57 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~58 )); defparam \fp_pow_0002:fp_pow_inst|Add29~57_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~57_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~57_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~53_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~58 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~54 )); defparam \fp_pow_0002:fp_pow_inst|Add29~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~53_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~49_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[20] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[20] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~50 )); defparam \fp_pow_0002:fp_pow_inst|Add29~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~49_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~45_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[21] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[21] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~46 )); defparam \fp_pow_0002:fp_pow_inst|Add29~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~45_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~41_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[22] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[22] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~42 )); defparam \fp_pow_0002:fp_pow_inst|Add29~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~41_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~37_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[23] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[23] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~38 )); defparam \fp_pow_0002:fp_pow_inst|Add29~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~37_I .lut_mask = "0000FF0000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~33_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[24] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[24] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~34 )); defparam \fp_pow_0002:fp_pow_inst|Add29~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~33_I .lut_mask = "0000FF0000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~29_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[25] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p2_uid336_qTimesOOlog2Ext_uid115_fpPowrTest_q[25] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~30 )); defparam \fp_pow_0002:fp_pow_inst|Add29~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~29_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~25_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[26] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~26 )); defparam \fp_pow_0002:fp_pow_inst|Add29~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~25_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~21_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[27] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~22 )); defparam \fp_pow_0002:fp_pow_inst|Add29~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~21_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~17_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[28] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~18 )); defparam \fp_pow_0002:fp_pow_inst|Add29~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~17_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~13_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[29] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~14 )); defparam \fp_pow_0002:fp_pow_inst|Add29~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~13_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~9_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[30] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~10 )); defparam \fp_pow_0002:fp_pow_inst|Add29~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~9_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~5_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p3_uid335_qTimesOOlog2Ext_uid115_fpPowrTest_q[31] ), .cin(\fp_pow_0002:fp_pow_inst|Add29~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add29~6 )); defparam \fp_pow_0002:fp_pow_inst|Add29~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~5_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add29~1_I ( .cin(\fp_pow_0002:fp_pow_inst|Add29~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add29~1 )); defparam \fp_pow_0002:fp_pow_inst|Add29~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add29~1_I .lut_mask = "0000FFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[32] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[32]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[31] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[31]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][31]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][30]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[30] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[30]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][29]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[29] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[29]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[28] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[28]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~57 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][28]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[27] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[27]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~61 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][27]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~65 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][26]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[26] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[26]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[25] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~69 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~73 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][24]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[24] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[24]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~77 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][23]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[23] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[23]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~81 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[22] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~85 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[21] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~89 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[20] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[19] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~93 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~57 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[18] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~97 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~61 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[17] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~101 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~105 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~65 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[16] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~69 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[15] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~109 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~113 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~73 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[14] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~77 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[13] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~117 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~121 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~81 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[12] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~125 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~85 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[11] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~129 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~89 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[10] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~133 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~93 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[9] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~97 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[8] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~137 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~101 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[7] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~141 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~105 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[6] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~145 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~109 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[5] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~149 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~153 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~113 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[4] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~157 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~117 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[3] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~121 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[2] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~161 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add30~165 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~125 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[1] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add29~129 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[0] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram5~26_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist46|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram5~26 )); defparam \fp_pow_0002:fp_pow_inst|Ram5~26_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~26_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram5~26_I .lut_mask = "6187E5861A7978E1"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist44|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram5~26 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist44|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist44|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist44|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist44|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist42|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~169_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][0] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add31~169 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~170 )); defparam \fp_pow_0002:fp_pow_inst|Add31~169_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~169_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~169_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~165_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[1] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~170 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~165 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~166 )); defparam \fp_pow_0002:fp_pow_inst|Add31~165_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~165_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~165_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~161_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][2] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~166 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~161 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~162 )); defparam \fp_pow_0002:fp_pow_inst|Add31~161_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~161_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~161_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~157_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[3] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~162 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~157 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~158 )); defparam \fp_pow_0002:fp_pow_inst|Add31~157_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~157_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~157_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~153_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[4] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~158 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~153 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~154 )); defparam \fp_pow_0002:fp_pow_inst|Add31~153_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~153_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~153_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~149_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~154 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~149 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~150 )); defparam \fp_pow_0002:fp_pow_inst|Add31~149_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~149_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~149_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~145_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[6] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][6] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~150 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~145 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~146 )); defparam \fp_pow_0002:fp_pow_inst|Add31~145_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~145_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~145_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~141_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[7] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~146 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~141 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~142 )); defparam \fp_pow_0002:fp_pow_inst|Add31~141_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~141_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~141_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~137_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[8] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][8] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~142 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~137 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~138 )); defparam \fp_pow_0002:fp_pow_inst|Add31~137_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~137_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~137_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~133_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][9] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[9] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~138 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~133 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~134 )); defparam \fp_pow_0002:fp_pow_inst|Add31~133_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~133_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~133_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~129_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][10] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[10] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~134 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~129 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~130 )); defparam \fp_pow_0002:fp_pow_inst|Add31~129_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~129_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~129_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~125_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][11] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[11] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~130 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~125 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~126 )); defparam \fp_pow_0002:fp_pow_inst|Add31~125_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~125_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~125_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~121_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][12] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[12] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~126 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~121 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~122 )); defparam \fp_pow_0002:fp_pow_inst|Add31~121_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~121_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~121_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~117_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[13] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][13] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~122 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~117 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~118 )); defparam \fp_pow_0002:fp_pow_inst|Add31~117_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~117_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~117_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~113_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][14] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[14] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~118 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~113 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~114 )); defparam \fp_pow_0002:fp_pow_inst|Add31~113_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~113_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~113_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~109_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[15] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][15] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~114 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~109 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~110 )); defparam \fp_pow_0002:fp_pow_inst|Add31~109_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~109_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~109_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~105_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][16] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[16] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~110 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~105 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~106 )); defparam \fp_pow_0002:fp_pow_inst|Add31~105_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~105_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~105_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~101_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[17] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][17] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~106 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~101 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~102 )); defparam \fp_pow_0002:fp_pow_inst|Add31~101_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~101_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~101_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~97_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[18] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][18] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~102 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~97 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~98 )); defparam \fp_pow_0002:fp_pow_inst|Add31~97_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~97_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~97_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~93_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[19] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][19] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~98 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~93 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~94 )); defparam \fp_pow_0002:fp_pow_inst|Add31~93_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~93_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~93_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~89_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][20] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[20] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~94 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~89 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~90 )); defparam \fp_pow_0002:fp_pow_inst|Add31~89_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~89_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~89_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~85_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][21] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[21] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~90 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~85 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~86 )); defparam \fp_pow_0002:fp_pow_inst|Add31~85_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~85_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~85_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~81_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][22] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[22] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~86 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~81 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~82 )); defparam \fp_pow_0002:fp_pow_inst|Add31~81_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~81_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~81_I .lut_mask = "0000FF0000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~77_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][23] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[23] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~82 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~78 )); defparam \fp_pow_0002:fp_pow_inst|Add31~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~77_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~73_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][24] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[24] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~73 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~74 )); defparam \fp_pow_0002:fp_pow_inst|Add31~73_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~73_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~73_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~69_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[25] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][25] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~74 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~69 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~70 )); defparam \fp_pow_0002:fp_pow_inst|Add31~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~69_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~65_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][26] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[26] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~70 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~65 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~66 )); defparam \fp_pow_0002:fp_pow_inst|Add31~65_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~65_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~65_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~61_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[27] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][27] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~66 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~62 )); defparam \fp_pow_0002:fp_pow_inst|Add31~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~61_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~57_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[28] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][28] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~57 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~58 )); defparam \fp_pow_0002:fp_pow_inst|Add31~57_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~57_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~57_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~53_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][29] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[29] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~58 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~54 )); defparam \fp_pow_0002:fp_pow_inst|Add31~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~53_I .lut_mask = "0000FF0000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~49_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][30] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[30] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~50 )); defparam \fp_pow_0002:fp_pow_inst|Add31~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~49_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~45_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[31] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][31] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~46 )); defparam \fp_pow_0002:fp_pow_inst|Add31~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~45_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~29_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][32] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a1_uid343_qTimesOOlog2Ext_uid115_fpPowrTest_o[32] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~30 )); defparam \fp_pow_0002:fp_pow_inst|Add31~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~29_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~9_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][33] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~10 )); defparam \fp_pow_0002:fp_pow_inst|Add31~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~9_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~41_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][34] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~42 )); defparam \fp_pow_0002:fp_pow_inst|Add31~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~41_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~21_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][35] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~22 )); defparam \fp_pow_0002:fp_pow_inst|Add31~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~21_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~25_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][36] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~26 )); defparam \fp_pow_0002:fp_pow_inst|Add31~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~25_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~5_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][37] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~6 )); defparam \fp_pow_0002:fp_pow_inst|Add31~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~5_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~37_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][38] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~38 )); defparam \fp_pow_0002:fp_pow_inst|Add31~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~37_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~17_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][39] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~18 )); defparam \fp_pow_0002:fp_pow_inst|Add31~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~17_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~33_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][40] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~34 )); defparam \fp_pow_0002:fp_pow_inst|Add31~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~33_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~13_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][41] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add31~14 )); defparam \fp_pow_0002:fp_pow_inst|Add31~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~13_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add31~1_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist42|__ALT_INV__delay_signals[0][42] ), .cin(\fp_pow_0002:fp_pow_inst|Add31~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add31~1 )); defparam \fp_pow_0002:fp_pow_inst|Add31~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add31~1_I .lut_mask = "0000FFFF00003333"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[42]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[42] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[42]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[41]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[41] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[41]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[40]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[40] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[40]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[39]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[39] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[39]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[38]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[38] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[38]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[37] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[37]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[36]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[36] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[36]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[35] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[35]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[34] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[34]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[33] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[33]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[32] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[32]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[31] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[31]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[30] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[30]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[29] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[29]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~57 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[28] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[28]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~61 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[27] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[27]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~65 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[26] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[26]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~69 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[25] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~73 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[24] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[24]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~77 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[23] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[23]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~81 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[22] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~85 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[21] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~89 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[20] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~113 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~101 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~97 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][4]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[1][4] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][4]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][4]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~105 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~109 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram2~19_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][4] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram2~19 )); defparam \fp_pow_0002:fp_pow_inst|Ram2~19_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~19_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~19_I .lut_mask = "00FF03FF00FF0FFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~93 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[1][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist49|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram2~19 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][5] ), .q(\fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram2~18_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram2~18 )); defparam \fp_pow_0002:fp_pow_inst|Ram2~18_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~18_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~18_I .lut_mask = "05AA05A805AA15A0"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram2~18 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram2~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram2~0 )); defparam \fp_pow_0002:fp_pow_inst|Ram2~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~0_I .lut_mask = "500F5AAD50AF4AA5"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram2~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram2~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram2~1 )); defparam \fp_pow_0002:fp_pow_inst|Ram2~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~1_I .lut_mask = "1AAA55595A5AE575"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram2~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram2~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram2~2 )); defparam \fp_pow_0002:fp_pow_inst|Ram2~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~2_I .lut_mask = "1AA675589AA6519A"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram2~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram2~3_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram2~3 )); defparam \fp_pow_0002:fp_pow_inst|Ram2~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~3_I .lut_mask = "4CB332CC9B26649B"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram2~3 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~121 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~129 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~133 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[1][1] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~137 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~125 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram1~13_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram1~13 )); defparam \fp_pow_0002:fp_pow_inst|Ram1~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~13_I .lut_mask = "33333333333F3F3F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add27~117 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram1~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][5] ), .q(\fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] )); defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram2~17_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram2~17 )); defparam \fp_pow_0002:fp_pow_inst|Ram2~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~17_I .lut_mask = "686AA9E856955656"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram2~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram2~4_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram2~4 )); defparam \fp_pow_0002:fp_pow_inst|Ram2~4_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~4_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~4_I .lut_mask = "569994996694D699"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram2~4 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram1~12_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram1~12 )); defparam \fp_pow_0002:fp_pow_inst|Ram1~12_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~12_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~12_I .lut_mask = "4444444666626262"; dffeas \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram1~12 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] )); defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram2~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram2~5 )); defparam \fp_pow_0002:fp_pow_inst|Ram2~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~5_I .lut_mask = "2204DFBAFB2004FF"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram2~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][2]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][2]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][2]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][2]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][2]~DUPLICATE_I .created_from = "Q(delay_signals[0][2])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram1~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][4] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Ram1~0 )); defparam \fp_pow_0002:fp_pow_inst|Ram1~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~0_I .lut_mask = "07A507A55EA55A85"; dffeas \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram1~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] )); defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram2~16_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram2~16 )); defparam \fp_pow_0002:fp_pow_inst|Ram2~16_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~16_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~16_I .lut_mask = "22DB24BAD964DB45"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram2~16 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram1~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][2] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram1~1 )); defparam \fp_pow_0002:fp_pow_inst|Ram1~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~1_I .lut_mask = "197339679C999999"; dffeas \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram1~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] )); defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram2~6_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram2~6 )); defparam \fp_pow_0002:fp_pow_inst|Ram2~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~6_I .lut_mask = "3636246CDB939296"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram2~6 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][4]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][4]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][4]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][4]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][4]~DUPLICATE_I .created_from = "Q(delay_signals[0][4])"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][0]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][0]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][0]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][0]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist50|delay_signals[0][0]~DUPLICATE_I .created_from = "Q(delay_signals[0][0])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram1~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][4]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][3] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram1~2 )); defparam \fp_pow_0002:fp_pow_inst|Ram1~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~2_I .lut_mask = "7A055FA015E881FA"; dffeas \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram1~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] )); defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram2~15_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram2~15 )); defparam \fp_pow_0002:fp_pow_inst|Ram2~15_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~15_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~15_I .lut_mask = "5A4D5B254DA425B2"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram2~15 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram1~3_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Ram1~3 )); defparam \fp_pow_0002:fp_pow_inst|Ram1~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~3_I .lut_mask = "6586A59E5A695865"; dffeas \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram1~3 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] )); defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram2~14_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram2~14 )); defparam \fp_pow_0002:fp_pow_inst|Ram2~14_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~14_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~14_I .lut_mask = "1EE7799E18866118"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram2~14 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram1~11_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Ram1~11 )); defparam \fp_pow_0002:fp_pow_inst|Ram1~11_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~11_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~11_I .lut_mask = "66398C63CE339866"; dffeas \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram1~11 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] )); defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram2~13_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram2~13 )); defparam \fp_pow_0002:fp_pow_inst|Ram2~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~13_I .lut_mask = "5B6DB6DB6DB6DB6D"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram2~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram1~4_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][4] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Ram1~4 )); defparam \fp_pow_0002:fp_pow_inst|Ram1~4_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~4_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~4_I .lut_mask = "2D2F4AD2F0B40F0B"; dffeas \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram1~4 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] )); defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram2~12_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram2~12 )); defparam \fp_pow_0002:fp_pow_inst|Ram2~12_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~12_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~12_I .lut_mask = "1EE7799EE7799EE7"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram2~12 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram1~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][2] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram1~5 )); defparam \fp_pow_0002:fp_pow_inst|Ram1~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~5_I .lut_mask = "54A595AD5695D4A5"; dffeas \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram1~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] )); defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram1~10_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][4]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][3] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram1~10 )); defparam \fp_pow_0002:fp_pow_inst|Ram1~10_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~10_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~10_I .lut_mask = "0E1CC78EF3C33871"; dffeas \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram1~10 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] )); defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram2~11_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram2~11 )); defparam \fp_pow_0002:fp_pow_inst|Ram2~11_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~11_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~11_I .lut_mask = "5B6DB6DB69B4D269"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram2~11 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram2~10_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram2~10 )); defparam \fp_pow_0002:fp_pow_inst|Ram2~10_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~10_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~10_I .lut_mask = "66659A967959E665"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram2~10 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram1~6_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram1~6 )); defparam \fp_pow_0002:fp_pow_inst|Ram1~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~6_I .lut_mask = "5552ADA55A2AD552"; dffeas \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram1~6 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] )); defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram1~9_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][4]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][3] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram1~9 )); defparam \fp_pow_0002:fp_pow_inst|Ram1~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~9_I .lut_mask = "1EE718861886799E"; dffeas \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram1~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] )); defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram2~7_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][5] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram2~7 )); defparam \fp_pow_0002:fp_pow_inst|Ram2~7_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~7_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~7_I .lut_mask = "0F3C3CF1E3C7871C"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram2~7 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram2~8_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram2~8 )); defparam \fp_pow_0002:fp_pow_inst|Ram2~8_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~8_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~8_I .lut_mask = "34C32CD23CD2CB3C"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram2~8 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram1~8_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][4]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][3] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram1~8 )); defparam \fp_pow_0002:fp_pow_inst|Ram1~8_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~8_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~8_I .lut_mask = "67796118799E1886"; dffeas \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram1~8 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] )); defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram1~7_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][4] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist50|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Ram1~7 )); defparam \fp_pow_0002:fp_pow_inst|Ram1~7_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~7_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram1~7_I .lut_mask = "697E7E977E9797E9"; dffeas \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram1~7 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] )); defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram2~9_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][2] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist49|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Ram2~9 )); defparam \fp_pow_0002:fp_pow_inst|Ram2~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram2~9_I .lut_mask = "343C963C6D693C69"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram2~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add28~81_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[0] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add28~81 ), .cout(\fp_pow_0002:fp_pow_inst|Add28~82 )); defparam \fp_pow_0002:fp_pow_inst|Add28~81_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~81_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~81_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add28~77_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[1] ), .cin(\fp_pow_0002:fp_pow_inst|Add28~82 ), .sumout(\fp_pow_0002:fp_pow_inst|Add28~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add28~78 )); defparam \fp_pow_0002:fp_pow_inst|Add28~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~77_I .lut_mask = "0000FF0000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add28~73_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[2] ), .cin(\fp_pow_0002:fp_pow_inst|Add28~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add28~73 ), .cout(\fp_pow_0002:fp_pow_inst|Add28~74 )); defparam \fp_pow_0002:fp_pow_inst|Add28~73_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~73_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~73_I .lut_mask = "0000FF0000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add28~69_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[3] ), .cin(\fp_pow_0002:fp_pow_inst|Add28~74 ), .sumout(\fp_pow_0002:fp_pow_inst|Add28~69 ), .cout(\fp_pow_0002:fp_pow_inst|Add28~70 )); defparam \fp_pow_0002:fp_pow_inst|Add28~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~69_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add28~65_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[4] ), .cin(\fp_pow_0002:fp_pow_inst|Add28~70 ), .sumout(\fp_pow_0002:fp_pow_inst|Add28~65 ), .cout(\fp_pow_0002:fp_pow_inst|Add28~66 )); defparam \fp_pow_0002:fp_pow_inst|Add28~65_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~65_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~65_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add28~61_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[5] ), .cin(\fp_pow_0002:fp_pow_inst|Add28~66 ), .sumout(\fp_pow_0002:fp_pow_inst|Add28~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add28~62 )); defparam \fp_pow_0002:fp_pow_inst|Add28~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~61_I .lut_mask = "0000FF0000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add28~57_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[6] ), .cin(\fp_pow_0002:fp_pow_inst|Add28~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add28~57 ), .cout(\fp_pow_0002:fp_pow_inst|Add28~58 )); defparam \fp_pow_0002:fp_pow_inst|Add28~57_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~57_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~57_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add28~53_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[7] ), .cin(\fp_pow_0002:fp_pow_inst|Add28~58 ), .sumout(\fp_pow_0002:fp_pow_inst|Add28~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add28~54 )); defparam \fp_pow_0002:fp_pow_inst|Add28~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~53_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add28~49_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[8] ), .cin(\fp_pow_0002:fp_pow_inst|Add28~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add28~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add28~50 )); defparam \fp_pow_0002:fp_pow_inst|Add28~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~49_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add28~45_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[9] ), .cin(\fp_pow_0002:fp_pow_inst|Add28~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add28~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add28~46 )); defparam \fp_pow_0002:fp_pow_inst|Add28~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~45_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add28~41_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[10] ), .cin(\fp_pow_0002:fp_pow_inst|Add28~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add28~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add28~42 )); defparam \fp_pow_0002:fp_pow_inst|Add28~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~41_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add28~37_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[11] ), .cin(\fp_pow_0002:fp_pow_inst|Add28~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add28~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add28~38 )); defparam \fp_pow_0002:fp_pow_inst|Add28~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~37_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add28~33_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[12] ), .cin(\fp_pow_0002:fp_pow_inst|Add28~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add28~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add28~34 )); defparam \fp_pow_0002:fp_pow_inst|Add28~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~33_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add28~29_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p0_uid338_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[13] ), .cin(\fp_pow_0002:fp_pow_inst|Add28~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add28~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add28~30 )); defparam \fp_pow_0002:fp_pow_inst|Add28~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~29_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add28~25_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[14] ), .cin(\fp_pow_0002:fp_pow_inst|Add28~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add28~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add28~26 )); defparam \fp_pow_0002:fp_pow_inst|Add28~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~25_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add28~21_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[15] ), .cin(\fp_pow_0002:fp_pow_inst|Add28~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add28~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add28~22 )); defparam \fp_pow_0002:fp_pow_inst|Add28~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~21_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add28~17_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[16] ), .cin(\fp_pow_0002:fp_pow_inst|Add28~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add28~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add28~18 )); defparam \fp_pow_0002:fp_pow_inst|Add28~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~17_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add28~13_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[17] ), .cin(\fp_pow_0002:fp_pow_inst|Add28~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add28~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add28~14 )); defparam \fp_pow_0002:fp_pow_inst|Add28~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~13_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add28~9_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[18] ), .cin(\fp_pow_0002:fp_pow_inst|Add28~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add28~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add28~10 )); defparam \fp_pow_0002:fp_pow_inst|Add28~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~9_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add28~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid337_qTimesOOlog2Ext_uid115_fpPowrTest_q[19] ), .cin(\fp_pow_0002:fp_pow_inst|Add28~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add28~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add28~6 )); defparam \fp_pow_0002:fp_pow_inst|Add28~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~5_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add28~1_I ( .cin(\fp_pow_0002:fp_pow_inst|Add28~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add28~1 )); defparam \fp_pow_0002:fp_pow_inst|Add28~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add28~1_I .lut_mask = "0000FFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add28~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[20] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~93 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[19] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add28~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[19] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~97 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[18] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add28~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[18] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add28~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[17] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~101 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[17] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~105 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[16] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add28~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[16] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add28~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[15] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~109 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[15] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add28~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[14] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~113 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[14] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~117 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[13] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add28~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[13] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~121 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[12] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add28~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[12] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~125 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[11] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add28~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[11] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~129 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[10] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add28~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[10] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~133 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[9] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add28~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[9] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~137 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[8] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add28~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[8] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~141 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[7] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add28~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[7] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~145 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[6] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add28~57 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[6] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~149 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[5] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add28~61 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[5] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~153 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[4] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add28~65 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[4] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~157 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[3] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add28~69 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[3] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add28~73 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[2] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~161 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[2] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~165 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[1] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add28~77 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[1] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add31~169 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[0] )); defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add28~81 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[0] )); defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~170_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[0] ), .cin(gnd), .cout(\fp_pow_0002:fp_pow_inst|Add32~170 )); defparam \fp_pow_0002:fp_pow_inst|Add32~170_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~170_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~170_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~166_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[1] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~170 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~166 )); defparam \fp_pow_0002:fp_pow_inst|Add32~166_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~166_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~166_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~162_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[2] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[2] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~166 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~162 )); defparam \fp_pow_0002:fp_pow_inst|Add32~162_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~162_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~162_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~158_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[3] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[3] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~162 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~158 )); defparam \fp_pow_0002:fp_pow_inst|Add32~158_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~158_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~158_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~154_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[4] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[4] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~158 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~154 )); defparam \fp_pow_0002:fp_pow_inst|Add32~154_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~154_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~154_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~150_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[5] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[5] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~154 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~150 )); defparam \fp_pow_0002:fp_pow_inst|Add32~150_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~150_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~150_I .lut_mask = "0000FF0000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~146_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[6] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[6] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~150 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~146 )); defparam \fp_pow_0002:fp_pow_inst|Add32~146_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~146_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~146_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~142_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[7] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[7] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~146 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~142 )); defparam \fp_pow_0002:fp_pow_inst|Add32~142_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~142_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~142_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~138_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[8] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[8] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~142 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~138 )); defparam \fp_pow_0002:fp_pow_inst|Add32~138_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~138_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~138_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~134_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[9] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[9] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~138 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~134 )); defparam \fp_pow_0002:fp_pow_inst|Add32~134_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~134_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~134_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~130_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[10] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[10] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~134 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~130 )); defparam \fp_pow_0002:fp_pow_inst|Add32~130_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~130_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~130_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~126_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[11] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[11] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~130 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~126 )); defparam \fp_pow_0002:fp_pow_inst|Add32~126_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~126_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~126_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~122_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[12] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[12] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~126 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~122 )); defparam \fp_pow_0002:fp_pow_inst|Add32~122_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~122_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~122_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~118_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[13] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[13] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~122 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~118 )); defparam \fp_pow_0002:fp_pow_inst|Add32~118_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~118_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~118_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~114_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[14] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[14] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~118 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~114 )); defparam \fp_pow_0002:fp_pow_inst|Add32~114_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~114_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~114_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~110_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[15] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[15] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~114 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~110 )); defparam \fp_pow_0002:fp_pow_inst|Add32~110_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~110_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~110_I .lut_mask = "0000AAAA00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~106_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[16] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[16] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~110 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~106 )); defparam \fp_pow_0002:fp_pow_inst|Add32~106_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~106_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~106_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~102_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[17] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[17] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~106 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~102 )); defparam \fp_pow_0002:fp_pow_inst|Add32~102_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~102_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~102_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~98_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[18] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[18] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~102 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~98 )); defparam \fp_pow_0002:fp_pow_inst|Add32~98_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~98_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~98_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~94_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[19] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[19] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~98 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~94 )); defparam \fp_pow_0002:fp_pow_inst|Add32~94_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~94_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~94_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~90_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[20] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev1_a2_uid344_qTimesOOlog2Ext_uid115_fpPowrTest_o[20] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~94 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~90 )); defparam \fp_pow_0002:fp_pow_inst|Add32~90_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~90_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~90_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~86_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[21] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~90 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~86 )); defparam \fp_pow_0002:fp_pow_inst|Add32~86_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~86_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~86_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~82_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[22] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~86 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~82 )); defparam \fp_pow_0002:fp_pow_inst|Add32~82_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~82_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~82_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~78_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[23] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~82 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~78 )); defparam \fp_pow_0002:fp_pow_inst|Add32~78_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~78_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~78_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~74_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[24] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~78 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~74 )); defparam \fp_pow_0002:fp_pow_inst|Add32~74_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~74_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~74_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~70_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[25] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~74 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~70 )); defparam \fp_pow_0002:fp_pow_inst|Add32~70_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~70_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~70_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~66_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[26] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~70 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~66 )); defparam \fp_pow_0002:fp_pow_inst|Add32~66_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~66_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~66_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~62_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[27] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~66 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~62 )); defparam \fp_pow_0002:fp_pow_inst|Add32~62_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~62_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~62_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~58_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[28] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~62 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~58 )); defparam \fp_pow_0002:fp_pow_inst|Add32~58_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~58_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~58_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~54_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[29] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~58 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~54 )); defparam \fp_pow_0002:fp_pow_inst|Add32~54_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~54_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~54_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~50_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[30] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~54 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~50 )); defparam \fp_pow_0002:fp_pow_inst|Add32~50_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~50_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~50_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~46_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[31] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~50 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~46 )); defparam \fp_pow_0002:fp_pow_inst|Add32~46_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~46_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~46_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~29_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[32] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add32~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~30 )); defparam \fp_pow_0002:fp_pow_inst|Add32~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~29_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~9_I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[33] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add32~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~10 )); defparam \fp_pow_0002:fp_pow_inst|Add32~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~9_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~41_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[34] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add32~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~42 )); defparam \fp_pow_0002:fp_pow_inst|Add32~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~41_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~21_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[35] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add32~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~22 )); defparam \fp_pow_0002:fp_pow_inst|Add32~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~21_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~25_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[36] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add32~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~26 )); defparam \fp_pow_0002:fp_pow_inst|Add32~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~25_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[37] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add32~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~6 )); defparam \fp_pow_0002:fp_pow_inst|Add32~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~5_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~37_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[38] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add32~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~38 )); defparam \fp_pow_0002:fp_pow_inst|Add32~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~37_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~17_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[39] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add32~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~18 )); defparam \fp_pow_0002:fp_pow_inst|Add32~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~17_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~33_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[40] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add32~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~34 )); defparam \fp_pow_0002:fp_pow_inst|Add32~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~33_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~13_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[41] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add32~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add32~14 )); defparam \fp_pow_0002:fp_pow_inst|Add32~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~13_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add32~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__lev2_a0_uid345_qTimesOOlog2Ext_uid115_fpPowrTest_o[42] ), .cin(\fp_pow_0002:fp_pow_inst|Add32~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add32~1 )); defparam \fp_pow_0002:fp_pow_inst|Add32~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add32~1_I .lut_mask = "0000FFFF00005555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][38]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add32~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][38] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][38]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][38] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[1]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1] )); defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2] )); defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[3] ), .combout(\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3] )); defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0]~0_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "FFFFFFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[1]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[2]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[2]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[2]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[2]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[2]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[2]~DUPLICATE_I .created_from = "Q(redist96_replace_rdcnt_i[2])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist96_replace_rdcnt_i[2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist96_replace_rdcnt_i[3] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[3] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[3]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4311,portadatain_unconnected_wire_4312,portadatain_unconnected_wire_4313,portadatain_unconnected_wire_4314,portadatain_unconnected_wire_4315,portadatain_unconnected_wire_4316,portadatain_unconnected_wire_4317, portadatain_unconnected_wire_4318,portadatain_unconnected_wire_4319,portadatain_unconnected_wire_4320,portadatain_unconnected_wire_4321,portadatain_unconnected_wire_4322,portadatain_unconnected_wire_4323,portadatain_unconnected_wire_4324, portadatain_unconnected_wire_4325,portadatain_unconnected_wire_4326,portadatain_unconnected_wire_4327,portadatain_unconnected_wire_4328,portadatain_unconnected_wire_4329,\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][10] }), .portaaddr({portaaddr_unconnected_wire_4330,portaaddr_unconnected_wire_4331,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4332,portbaddr_unconnected_wire_4333,\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[10] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10 .logical_ram_depth = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10 .logical_ram_width = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10 .first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10 .last_address = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama10 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add36~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[11] )); defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add36~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[10] )); defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add36~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[9] )); defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add36~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[8] )); defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add36~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[7] )); defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add36~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[6] )); defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add36~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[5] )); defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add36~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[4] )); defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[3] )); defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add35~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|Add35~5 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[2]~1_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[2]~1 )); defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[2]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[2]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[2]~1_I .lut_mask = "F0F0F0F0F0F0F0F0"; dffeas \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[2]~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[2] )); defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add35~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|Add35~5 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[1]~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[1]~2 )); defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[1]~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[1]~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[1]~2_I .lut_mask = "AAAAAAAAAAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[1]~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[1] )); defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[0]~_wirecell_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__expProdPhase2_uid101_fpPowrTest_o[0] ), .combout(\fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[0]~_wirecell )); defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[0]~_wirecell_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[0]~_wirecell_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[0]~_wirecell_I .lut_mask = "CCCCCCCCCCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|expProdPhase2_uid101_fpPowrTest_o[0]~_wirecell ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|Add35~5 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[0]~0_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:expProd_uid105_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[0]~0_I .lut_mask = "FF00FF00FF00FF00"; dffeas \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[0]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[0] )); defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|shiftValuePreSatExp_uid118_fpPowrTest_o[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add37~50_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[1] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[0] ), .cin(gnd), .cout(\fp_pow_0002:fp_pow_inst|Add37~50 )); defparam \fp_pow_0002:fp_pow_inst|Add37~50_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~50_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~50_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add37~46_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[2] ), .cin(\fp_pow_0002:fp_pow_inst|Add37~50 ), .cout(\fp_pow_0002:fp_pow_inst|Add37~46 )); defparam \fp_pow_0002:fp_pow_inst|Add37~46_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~46_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~46_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add37~42_I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[3] ), .cin(\fp_pow_0002:fp_pow_inst|Add37~46 ), .cout(\fp_pow_0002:fp_pow_inst|Add37~42 )); defparam \fp_pow_0002:fp_pow_inst|Add37~42_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~42_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~42_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add37~38_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[4] ), .cin(\fp_pow_0002:fp_pow_inst|Add37~42 ), .cout(\fp_pow_0002:fp_pow_inst|Add37~38 )); defparam \fp_pow_0002:fp_pow_inst|Add37~38_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~38_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~38_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add37~34_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[5] ), .cin(\fp_pow_0002:fp_pow_inst|Add37~38 ), .cout(\fp_pow_0002:fp_pow_inst|Add37~34 )); defparam \fp_pow_0002:fp_pow_inst|Add37~34_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~34_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~34_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add37~30_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[6] ), .cin(\fp_pow_0002:fp_pow_inst|Add37~34 ), .cout(\fp_pow_0002:fp_pow_inst|Add37~30 )); defparam \fp_pow_0002:fp_pow_inst|Add37~30_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~30_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~30_I .lut_mask = "0000000000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add37~26_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[7] ), .cin(\fp_pow_0002:fp_pow_inst|Add37~30 ), .cout(\fp_pow_0002:fp_pow_inst|Add37~26 )); defparam \fp_pow_0002:fp_pow_inst|Add37~26_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~26_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~26_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add37~22_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[8] ), .cin(\fp_pow_0002:fp_pow_inst|Add37~26 ), .cout(\fp_pow_0002:fp_pow_inst|Add37~22 )); defparam \fp_pow_0002:fp_pow_inst|Add37~22_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~22_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~22_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add37~18_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[9] ), .cin(\fp_pow_0002:fp_pow_inst|Add37~22 ), .cout(\fp_pow_0002:fp_pow_inst|Add37~18 )); defparam \fp_pow_0002:fp_pow_inst|Add37~18_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~18_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~18_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add37~14_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[10] ), .cin(\fp_pow_0002:fp_pow_inst|Add37~18 ), .cout(\fp_pow_0002:fp_pow_inst|Add37~14 )); defparam \fp_pow_0002:fp_pow_inst|Add37~14_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~14_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~14_I .lut_mask = "0000000000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add37~10_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[11] ), .cin(\fp_pow_0002:fp_pow_inst|Add37~14 ), .cout(\fp_pow_0002:fp_pow_inst|Add37~10 )); defparam \fp_pow_0002:fp_pow_inst|Add37~10_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~10_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~10_I .lut_mask = "0000000000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add37~6_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[12] ), .cin(\fp_pow_0002:fp_pow_inst|Add37~10 ), .cout(\fp_pow_0002:fp_pow_inst|Add37~6 )); defparam \fp_pow_0002:fp_pow_inst|Add37~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~6_I .lut_mask = "0000000000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add37~1_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[12] ), .cin(\fp_pow_0002:fp_pow_inst|Add37~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add37~1 )); defparam \fp_pow_0002:fp_pow_inst|Add37~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add37~1_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rightShiftStageSel1Dto0_uid639_fxpInPostAlignExp_uid123_fpPowrTest_b[0]~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add37~1 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[0] ), .combout(\fp_pow_0002:fp_pow_inst|rightShiftStageSel1Dto0_uid639_fxpInPostAlignExp_uid123_fpPowrTest_b[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStageSel1Dto0_uid639_fxpInPostAlignExp_uid123_fpPowrTest_b[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStageSel1Dto0_uid639_fxpInPostAlignExp_uid123_fpPowrTest_b[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStageSel1Dto0_uid639_fxpInPostAlignExp_uid123_fpPowrTest_b[0]~0_I .lut_mask = "AFAFAFAFAFAFAFAF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rightShiftStageSel1Dto0_uid639_fxpInPostAlignExp_uid123_fpPowrTest_b[0]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add32~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][37] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][37]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rightShiftStageSel1Dto0_uid639_fxpInPostAlignExp_uid123_fpPowrTest_b[1]~1_I ( .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[1] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add37~1 ), .combout(\fp_pow_0002:fp_pow_inst|rightShiftStageSel1Dto0_uid639_fxpInPostAlignExp_uid123_fpPowrTest_b[1]~1 )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStageSel1Dto0_uid639_fxpInPostAlignExp_uid123_fpPowrTest_b[1]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStageSel1Dto0_uid639_fxpInPostAlignExp_uid123_fpPowrTest_b[1]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStageSel1Dto0_uid639_fxpInPostAlignExp_uid123_fpPowrTest_b[1]~1_I .lut_mask = "FFFFFFFF0000FFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[2][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rightShiftStageSel1Dto0_uid639_fxpInPostAlignExp_uid123_fpPowrTest_b[1]~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[2][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[2][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[2][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[1][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[2][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[1][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[1][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[1][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[1][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rightShiftStageSel3Dto2_uid628_fxpInPostAlignExp_uid123_fpPowrTest_b[0]~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add37~1 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[2] ), .combout(\fp_pow_0002:fp_pow_inst|rightShiftStageSel3Dto2_uid628_fxpInPostAlignExp_uid123_fpPowrTest_b[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStageSel3Dto2_uid628_fxpInPostAlignExp_uid123_fpPowrTest_b[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStageSel3Dto2_uid628_fxpInPostAlignExp_uid123_fpPowrTest_b[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStageSel3Dto2_uid628_fxpInPostAlignExp_uid123_fpPowrTest_b[0]~0_I .lut_mask = "0505050505050505"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rightShiftStageSel3Dto2_uid628_fxpInPostAlignExp_uid123_fpPowrTest_b[0]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rightShiftStageSel5Dto4_uid617_fxpInPostAlignExp_uid123_fpPowrTest_b[0]~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add37~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[4] ), .combout(\fp_pow_0002:fp_pow_inst|rightShiftStageSel5Dto4_uid617_fxpInPostAlignExp_uid123_fpPowrTest_b[0]~1 )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStageSel5Dto4_uid617_fxpInPostAlignExp_uid123_fpPowrTest_b[0]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStageSel5Dto4_uid617_fxpInPostAlignExp_uid123_fpPowrTest_b[0]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStageSel5Dto4_uid617_fxpInPostAlignExp_uid123_fpPowrTest_b[0]~1_I .lut_mask = "1111111111111111"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rightShiftStageSel5Dto4_uid617_fxpInPostAlignExp_uid123_fpPowrTest_b[0]~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rightShiftStageSel5Dto4_uid617_fxpInPostAlignExp_uid123_fpPowrTest_b[1]~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add37~1 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[5] ), .combout(\fp_pow_0002:fp_pow_inst|rightShiftStageSel5Dto4_uid617_fxpInPostAlignExp_uid123_fpPowrTest_b[1]~0 )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStageSel5Dto4_uid617_fxpInPostAlignExp_uid123_fpPowrTest_b[1]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStageSel5Dto4_uid617_fxpInPostAlignExp_uid123_fpPowrTest_b[1]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStageSel5Dto4_uid617_fxpInPostAlignExp_uid123_fpPowrTest_b[1]~0_I .lut_mask = "BBBBBBBBBBBBBBBB"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[2][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rightShiftStageSel5Dto4_uid617_fxpInPostAlignExp_uid123_fpPowrTest_b[1]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[2][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[2][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[2][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[1][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[2][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[1][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[1][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[1][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[1][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux154~0_I ( .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist19|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist19|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Mux154~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux154~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux154~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux154~0_I .lut_mask = "FFFF000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|rightShiftStageSel3Dto2_uid628_fxpInPostAlignExp_uid123_fpPowrTest_b[1]~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add37~1 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__shiftValuePreSatExp_uid118_fpPowrTest_o[3] ), .combout(\fp_pow_0002:fp_pow_inst|rightShiftStageSel3Dto2_uid628_fxpInPostAlignExp_uid123_fpPowrTest_b[1]~1 )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStageSel3Dto2_uid628_fxpInPostAlignExp_uid123_fpPowrTest_b[1]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStageSel3Dto2_uid628_fxpInPostAlignExp_uid123_fpPowrTest_b[1]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStageSel3Dto2_uid628_fxpInPostAlignExp_uid123_fpPowrTest_b[1]~1_I .lut_mask = "AAAAFFFFAAAAFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[2][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|rightShiftStageSel3Dto2_uid628_fxpInPostAlignExp_uid123_fpPowrTest_b[1]~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[2][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[2][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[2][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[1][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[2][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[1][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[1][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[1][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[1][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux167~0_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux154~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Mux167~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux167~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux167~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux167~0_I .lut_mask = "0F0F0F0F00000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux172~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux167~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux172~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux172~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux172~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux172~0_I .lut_mask = "00000000AA00AA00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux172~1_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][37] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][38] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux172~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux172~1 )); defparam \fp_pow_0002:fp_pow_inst|Mux172~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux172~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux172~1_I .lut_mask = "00FF00FF0C3F0C3F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux172~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4334,portadatain_unconnected_wire_4335,portadatain_unconnected_wire_4336,portadatain_unconnected_wire_4337,portadatain_unconnected_wire_4338,portadatain_unconnected_wire_4339,portadatain_unconnected_wire_4340, portadatain_unconnected_wire_4341,portadatain_unconnected_wire_4342,portadatain_unconnected_wire_4343,portadatain_unconnected_wire_4344,portadatain_unconnected_wire_4345,portadatain_unconnected_wire_4346,portadatain_unconnected_wire_4347, portadatain_unconnected_wire_4348,portadatain_unconnected_wire_4349,portadatain_unconnected_wire_4350,portadatain_unconnected_wire_4351,portadatain_unconnected_wire_4352,\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][9] }), .portaaddr({portaaddr_unconnected_wire_4353,portaaddr_unconnected_wire_4354,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4355,portbaddr_unconnected_wire_4356,\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[9] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9 .logical_ram_depth = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9 .logical_ram_width = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9 .first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9 .last_address = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama9 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][9]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|__ALT_INV__dataout_reg[9] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][9]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][9]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][9]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][9]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][9]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][36]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add32~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][36] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][36]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~282_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][38] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][37] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][36] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux172~0 ), .combout(\rtl~282 )); defparam \rtl~282_I .shared_arith = "off"; defparam \rtl~282_I .extended_lut = "off"; defparam \rtl~282_I .lut_mask = "3333333305AF05AF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~282 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4357,portadatain_unconnected_wire_4358,portadatain_unconnected_wire_4359,portadatain_unconnected_wire_4360,portadatain_unconnected_wire_4361,portadatain_unconnected_wire_4362,portadatain_unconnected_wire_4363, portadatain_unconnected_wire_4364,portadatain_unconnected_wire_4365,portadatain_unconnected_wire_4366,portadatain_unconnected_wire_4367,portadatain_unconnected_wire_4368,portadatain_unconnected_wire_4369,portadatain_unconnected_wire_4370, portadatain_unconnected_wire_4371,portadatain_unconnected_wire_4372,portadatain_unconnected_wire_4373,portadatain_unconnected_wire_4374,portadatain_unconnected_wire_4375,\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][8] }), .portaaddr({portaaddr_unconnected_wire_4376,portaaddr_unconnected_wire_4377,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4378,portbaddr_unconnected_wire_4379,\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[8] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8 .logical_ram_depth = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8 .logical_ram_width = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8 .first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8 .last_address = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama8 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][8]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|__ALT_INV__dataout_reg[8] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][8]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][8]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][8]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][8]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][8]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][35]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add32~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][35]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][35]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][35]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][35]~DUPLICATE_I .created_from = "Q(delay_signals[0][35])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux164~0_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][38] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][35]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux167~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux164~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux164~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux164~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux164~0_I .lut_mask = "3333333303F303F3"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux162~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][38] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][37] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux167~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux162~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux162~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux162~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux162~0_I .lut_mask = "3333333311BB11BB"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux163~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][38] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][36] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux167~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux163~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux163~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux163~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux163~0_I .lut_mask = "3333333311BB11BB"; cyclonev_lcell_comb \rtl~40_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux164~0 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux162~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][38] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux163~0 ), .combout(\rtl~40 )); defparam \rtl~40_I .shared_arith = "off"; defparam \rtl~40_I .extended_lut = "off"; defparam \rtl~40_I .lut_mask = "5300530F53F053FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~40 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4380,portadatain_unconnected_wire_4381,portadatain_unconnected_wire_4382,portadatain_unconnected_wire_4383,portadatain_unconnected_wire_4384,portadatain_unconnected_wire_4385,portadatain_unconnected_wire_4386, portadatain_unconnected_wire_4387,portadatain_unconnected_wire_4388,portadatain_unconnected_wire_4389,portadatain_unconnected_wire_4390,portadatain_unconnected_wire_4391,portadatain_unconnected_wire_4392,portadatain_unconnected_wire_4393, portadatain_unconnected_wire_4394,portadatain_unconnected_wire_4395,portadatain_unconnected_wire_4396,portadatain_unconnected_wire_4397,portadatain_unconnected_wire_4398,\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][7] }), .portaaddr({portaaddr_unconnected_wire_4399,portaaddr_unconnected_wire_4400,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4401,portbaddr_unconnected_wire_4402,\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[7] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7 .logical_ram_depth = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7 .logical_ram_width = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7 .first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7 .last_address = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama7 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][7]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|__ALT_INV__dataout_reg[7] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][7]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add32~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux165~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][38] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux167~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][34] ), .combout(\fp_pow_0002:fp_pow_inst|Mux165~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux165~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux165~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux165~0_I .lut_mask = "0F050F050FAF0FAF"; cyclonev_lcell_comb \rtl~39_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux165~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux163~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux162~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux164~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][0] ), .combout(\rtl~39 )); defparam \rtl~39_I .shared_arith = "off"; defparam \rtl~39_I .extended_lut = "off"; defparam \rtl~39_I .lut_mask = "272727270055AAFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~39 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4403,portadatain_unconnected_wire_4404,portadatain_unconnected_wire_4405,portadatain_unconnected_wire_4406,portadatain_unconnected_wire_4407,portadatain_unconnected_wire_4408,portadatain_unconnected_wire_4409, portadatain_unconnected_wire_4410,portadatain_unconnected_wire_4411,portadatain_unconnected_wire_4412,portadatain_unconnected_wire_4413,portadatain_unconnected_wire_4414,portadatain_unconnected_wire_4415,portadatain_unconnected_wire_4416, portadatain_unconnected_wire_4417,portadatain_unconnected_wire_4418,portadatain_unconnected_wire_4419,portadatain_unconnected_wire_4420,portadatain_unconnected_wire_4421,\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][6] }), .portaaddr({portaaddr_unconnected_wire_4422,portaaddr_unconnected_wire_4423,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4424,portbaddr_unconnected_wire_4425,\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[6] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6 .logical_ram_depth = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6 .logical_ram_width = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6 .first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6 .last_address = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama6 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][6]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|__ALT_INV__dataout_reg[6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][6]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][33]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add32~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][33]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][33]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][33]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][33]~DUPLICATE_I .created_from = "Q(delay_signals[0][33])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux166~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][38] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][33]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux167~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][37] ), .combout(\fp_pow_0002:fp_pow_inst|Mux166~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux166~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux166~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux166~0_I .lut_mask = "330A330A335F335F"; cyclonev_lcell_comb \rtl~38_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux165~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux164~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux166~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux163~0 ), .combout(\rtl~38 )); defparam \rtl~38_I .shared_arith = "off"; defparam \rtl~38_I .extended_lut = "off"; defparam \rtl~38_I .lut_mask = "0252A2F20757A7F7"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~38 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4426,portadatain_unconnected_wire_4427,portadatain_unconnected_wire_4428,portadatain_unconnected_wire_4429,portadatain_unconnected_wire_4430,portadatain_unconnected_wire_4431,portadatain_unconnected_wire_4432, portadatain_unconnected_wire_4433,portadatain_unconnected_wire_4434,portadatain_unconnected_wire_4435,portadatain_unconnected_wire_4436,portadatain_unconnected_wire_4437,portadatain_unconnected_wire_4438,portadatain_unconnected_wire_4439, portadatain_unconnected_wire_4440,portadatain_unconnected_wire_4441,portadatain_unconnected_wire_4442,portadatain_unconnected_wire_4443,portadatain_unconnected_wire_4444,\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][5] }), .portaaddr({portaaddr_unconnected_wire_4445,portaaddr_unconnected_wire_4446,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4447,portbaddr_unconnected_wire_4448,\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[5] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5 .logical_ram_depth = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5 .logical_ram_width = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5 .first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5 .last_address = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama5 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][5]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|__ALT_INV__dataout_reg[5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][5]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add32~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux168~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][36] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][32] ), .combout(\fp_pow_0002:fp_pow_inst|Mux168~2 )); defparam \fp_pow_0002:fp_pow_inst|Mux168~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux168~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux168~2_I .lut_mask = "05AF05AF05AF05AF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux167~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux168~2 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][38] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux167~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux167~1 )); defparam \fp_pow_0002:fp_pow_inst|Mux167~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux167~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux167~1_I .lut_mask = "0F550F550F550F55"; cyclonev_lcell_comb \rtl~37_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux166~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux167~1 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux164~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux165~0 ), .combout(\rtl~37 )); defparam \rtl~37_I .shared_arith = "off"; defparam \rtl~37_I .extended_lut = "off"; defparam \rtl~37_I .lut_mask = "028A139B46CE57DF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4449,portadatain_unconnected_wire_4450,portadatain_unconnected_wire_4451,portadatain_unconnected_wire_4452,portadatain_unconnected_wire_4453,portadatain_unconnected_wire_4454,portadatain_unconnected_wire_4455, portadatain_unconnected_wire_4456,portadatain_unconnected_wire_4457,portadatain_unconnected_wire_4458,portadatain_unconnected_wire_4459,portadatain_unconnected_wire_4460,portadatain_unconnected_wire_4461,portadatain_unconnected_wire_4462, portadatain_unconnected_wire_4463,portadatain_unconnected_wire_4464,portadatain_unconnected_wire_4465,portadatain_unconnected_wire_4466,portadatain_unconnected_wire_4467,\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][4] }), .portaaddr({portaaddr_unconnected_wire_4468,portaaddr_unconnected_wire_4469,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4470,portbaddr_unconnected_wire_4471,\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[4] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4 .logical_ram_depth = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4 .logical_ram_width = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4 .first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4 .last_address = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama4 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][4]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|__ALT_INV__dataout_reg[4] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][4]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][4]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add32~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~281_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][35]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][37] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][31] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][33]~DUPLICATE ), .combout(\rtl~281 )); defparam \rtl~281_I .shared_arith = "off"; defparam \rtl~281_I .extended_lut = "off"; defparam \rtl~281_I .lut_mask = "11DD030311DDCFCF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux178~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux168~2 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~281 ), .combout(\fp_pow_0002:fp_pow_inst|Mux178~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux178~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux178~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux178~0_I .lut_mask = "00500050FF50FF50"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux178~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][38] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux167~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux165~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux178~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Mux178~1 )); defparam \fp_pow_0002:fp_pow_inst|Mux178~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux178~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux178~1_I .lut_mask = "30303F3F20752F7F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux178~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4472,portadatain_unconnected_wire_4473,portadatain_unconnected_wire_4474,portadatain_unconnected_wire_4475,portadatain_unconnected_wire_4476,portadatain_unconnected_wire_4477,portadatain_unconnected_wire_4478, portadatain_unconnected_wire_4479,portadatain_unconnected_wire_4480,portadatain_unconnected_wire_4481,portadatain_unconnected_wire_4482,portadatain_unconnected_wire_4483,portadatain_unconnected_wire_4484,portadatain_unconnected_wire_4485, portadatain_unconnected_wire_4486,portadatain_unconnected_wire_4487,portadatain_unconnected_wire_4488,portadatain_unconnected_wire_4489,portadatain_unconnected_wire_4490,\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][3] }), .portaaddr({portaaddr_unconnected_wire_4491,portaaddr_unconnected_wire_4492,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4493,portbaddr_unconnected_wire_4494,\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[3] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3 .logical_ram_depth = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3 .logical_ram_width = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3 .first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3 .last_address = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama3 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add32~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~280_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][34] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][30] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux168~2 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~280 )); defparam \rtl~280_I .shared_arith = "off"; defparam \rtl~280_I .extended_lut = "off"; defparam \rtl~280_I .lut_mask = "1B1B1B1B00FF00FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux179~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux167~0 ), .datab(\__ALT_INV__rtl~280 ), .datac(\__ALT_INV__rtl~281 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][38] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Mux179~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux179~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux179~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux179~0_I .lut_mask = "11BB11BB05AF05AF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux179~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4495,portadatain_unconnected_wire_4496,portadatain_unconnected_wire_4497,portadatain_unconnected_wire_4498,portadatain_unconnected_wire_4499,portadatain_unconnected_wire_4500,portadatain_unconnected_wire_4501, portadatain_unconnected_wire_4502,portadatain_unconnected_wire_4503,portadatain_unconnected_wire_4504,portadatain_unconnected_wire_4505,portadatain_unconnected_wire_4506,portadatain_unconnected_wire_4507,portadatain_unconnected_wire_4508, portadatain_unconnected_wire_4509,portadatain_unconnected_wire_4510,portadatain_unconnected_wire_4511,portadatain_unconnected_wire_4512,portadatain_unconnected_wire_4513,\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][2] }), .portaaddr({portaaddr_unconnected_wire_4514,portaaddr_unconnected_wire_4515,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4516,portbaddr_unconnected_wire_4517,\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[2] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2 .logical_ram_depth = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2 .logical_ram_width = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2 .first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2 .last_address = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama2 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux168~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][38] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux154~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][37] ), .combout(\fp_pow_0002:fp_pow_inst|Mux168~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux168~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux168~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux168~0_I .lut_mask = "313131313B3B3B3B"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add32~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][35]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~274_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][38] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux154~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][35] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][31] ), .combout(\rtl~274 )); defparam \rtl~274_I .shared_arith = "off"; defparam \rtl~274_I .extended_lut = "off"; defparam \rtl~274_I .lut_mask = "4447444777477747"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add32~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][29]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add32~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~273_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][38] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux154~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][29] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][33] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|__ALT_INV__delay_signals[0][0] ), .combout(\rtl~273 )); defparam \rtl~273_I .shared_arith = "off"; defparam \rtl~273_I .extended_lut = "off"; defparam \rtl~273_I .lut_mask = "4747474744774477"; cyclonev_lcell_comb \rtl~9_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][38] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux168~0 ), .datae(\__ALT_INV__rtl~274 ), .dataf(\__ALT_INV__rtl~273 ), .combout(\rtl~9 )); defparam \rtl~9_I .shared_arith = "off"; defparam \rtl~9_I .extended_lut = "off"; defparam \rtl~9_I .lut_mask = "01510B5BA1F1ABFB"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux180~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux167~0 ), .datab(\__ALT_INV__rtl~280 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][38] ), .dataf(\__ALT_INV__rtl~9 ), .combout(\fp_pow_0002:fp_pow_inst|Mux180~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux180~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux180~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux180~0_I .lut_mask = "010B010BF1FBF1FB"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux180~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4518,portadatain_unconnected_wire_4519,portadatain_unconnected_wire_4520,portadatain_unconnected_wire_4521,portadatain_unconnected_wire_4522,portadatain_unconnected_wire_4523,portadatain_unconnected_wire_4524, portadatain_unconnected_wire_4525,portadatain_unconnected_wire_4526,portadatain_unconnected_wire_4527,portadatain_unconnected_wire_4528,portadatain_unconnected_wire_4529,portadatain_unconnected_wire_4530,portadatain_unconnected_wire_4531, portadatain_unconnected_wire_4532,portadatain_unconnected_wire_4533,portadatain_unconnected_wire_4534,portadatain_unconnected_wire_4535,portadatain_unconnected_wire_4536,\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][1] }), .portaaddr({portaaddr_unconnected_wire_4537,portaaddr_unconnected_wire_4538,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4539,portbaddr_unconnected_wire_4540,\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[1] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1 .logical_ram_depth = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1 .logical_ram_width = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1 .first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1 .last_address = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama1 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|__ALT_INV__dataout_reg[1] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add32~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist41|delay_signals[0][28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~275_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux154~0 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][38] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][32] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][28] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|__ALT_INV__delay_signals[0][0] ), .combout(\rtl~275 )); defparam \rtl~275_I .shared_arith = "off"; defparam \rtl~275_I .extended_lut = "off"; defparam \rtl~275_I .lut_mask = "2277227727272727"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux168~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][36] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][38] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux154~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux168~1 )); defparam \fp_pow_0002:fp_pow_inst|Mux168~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux168~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux168~1_I .lut_mask = "00FF00FF0A5F0A5F"; cyclonev_lcell_comb \rtl~276_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux154~0 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][38] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][30] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][34] ), .combout(\rtl~276 )); defparam \rtl~276_I .shared_arith = "off"; defparam \rtl~276_I .extended_lut = "off"; defparam \rtl~276_I .lut_mask = "2722272227772777"; cyclonev_lcell_comb \rtl~4_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][1] ), .datab(\__ALT_INV__rtl~275 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist41|__ALT_INV__delay_signals[0][38] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux168~1 ), .dataf(\__ALT_INV__rtl~276 ), .combout(\rtl~4 )); defparam \rtl~4_I .shared_arith = "off"; defparam \rtl~4_I .extended_lut = "off"; defparam \rtl~4_I .lut_mask = "20252A2F70757A7F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux181~0_I ( .dataa(\__ALT_INV__rtl~9 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~4 ), .combout(\fp_pow_0002:fp_pow_inst|Mux181~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux181~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux181~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux181~0_I .lut_mask = "05050505F5F5F5F5"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux181~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist96_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4541,portadatain_unconnected_wire_4542,portadatain_unconnected_wire_4543,portadatain_unconnected_wire_4544,portadatain_unconnected_wire_4545,portadatain_unconnected_wire_4546,portadatain_unconnected_wire_4547, portadatain_unconnected_wire_4548,portadatain_unconnected_wire_4549,portadatain_unconnected_wire_4550,portadatain_unconnected_wire_4551,portadatain_unconnected_wire_4552,portadatain_unconnected_wire_4553,portadatain_unconnected_wire_4554, portadatain_unconnected_wire_4555,portadatain_unconnected_wire_4556,portadatain_unconnected_wire_4557,portadatain_unconnected_wire_4558,portadatain_unconnected_wire_4559,\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][0] }), .portaaddr({portaaddr_unconnected_wire_4560,portaaddr_unconnected_wire_4561,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist96_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4562,portbaddr_unconnected_wire_4563,\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0 .logical_ram_depth = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0 .logical_ram_width = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0 .address_width = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0 .last_address = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist96_replace_mem_dmem|altera_syncram_sgg3:auto_generated|altsyncram_npb4:altsyncram1|dataout_reg[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add49~34_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][0] ), .cin(gnd), .cout(\fp_pow_0002:fp_pow_inst|Add49~34 )); defparam \fp_pow_0002:fp_pow_inst|Add49~34_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~34_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~34_I .lut_mask = "00000000000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add49~1_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][1] ), .cin(\fp_pow_0002:fp_pow_inst|Add49~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add49~1 ), .cout(\fp_pow_0002:fp_pow_inst|Add49~2 )); defparam \fp_pow_0002:fp_pow_inst|Add49~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~1_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add49~5_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][2] ), .cin(\fp_pow_0002:fp_pow_inst|Add49~2 ), .sumout(\fp_pow_0002:fp_pow_inst|Add49~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add49~6 )); defparam \fp_pow_0002:fp_pow_inst|Add49~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~5_I .lut_mask = "0000000000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add49~9_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][3] ), .cin(\fp_pow_0002:fp_pow_inst|Add49~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add49~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add49~10 )); defparam \fp_pow_0002:fp_pow_inst|Add49~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~9_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add49~13_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][4] ), .cin(\fp_pow_0002:fp_pow_inst|Add49~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add49~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add49~14 )); defparam \fp_pow_0002:fp_pow_inst|Add49~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~13_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add49~17_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add49~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add49~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add49~18 )); defparam \fp_pow_0002:fp_pow_inst|Add49~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~17_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add49~21_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][6] ), .cin(\fp_pow_0002:fp_pow_inst|Add49~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add49~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add49~22 )); defparam \fp_pow_0002:fp_pow_inst|Add49~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~21_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add49~25_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add49~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add49~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add49~26 )); defparam \fp_pow_0002:fp_pow_inst|Add49~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~25_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add49~45_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][8] ), .cin(\fp_pow_0002:fp_pow_inst|Add49~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add49~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add49~46 )); defparam \fp_pow_0002:fp_pow_inst|Add49~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~45_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add49~41_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][9] ), .cin(\fp_pow_0002:fp_pow_inst|Add49~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add49~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add49~42 )); defparam \fp_pow_0002:fp_pow_inst|Add49~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~41_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add49~37_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][10] ), .cin(\fp_pow_0002:fp_pow_inst|Add49~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add49~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add49~38 )); defparam \fp_pow_0002:fp_pow_inst|Add49~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~37_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add49~29_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][10] ), .cin(\fp_pow_0002:fp_pow_inst|Add49~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add49~29 )); defparam \fp_pow_0002:fp_pow_inst|Add49~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add49~29_I .lut_mask = "0000FFFF00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add49~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[11] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add49~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[10] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add49~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[9] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add49~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[8] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add49~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[7] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add49~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[6] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add49~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[5] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add49~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[4] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add49~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[3] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add49~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[2] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add49~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[1] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[0]~0_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist96_outputreg|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[0]~0_I .lut_mask = "CCCCCCCCCCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[0]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[0] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc0_uid147_fpPowrTest_o[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0]~feeder_I ( .combout(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0]~feeder_I .lut_mask = "FFFFFFFFFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|redist88_cmpReg_q[0] ), .q(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~27_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~27 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~27_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~27_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~27_I .lut_mask = "6EA86EA8EAA8EAA8"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~27 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[12] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~18_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~18 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~18_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~18_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~18_I .lut_mask = "8080808000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~36_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~36 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~36_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~36_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~36_I .lut_mask = "0000000001010101"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~19_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~18 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~36 ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~19 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~19_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~19_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~19_I .lut_mask = "AA0AAA0AA505A505"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~19 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~29_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~29 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~29_I .lut_mask = "70F0F0F0F0F0F0E3"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~31_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~31 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~31_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~31_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~31_I .lut_mask = "69A969A95A6A5A6A"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~31 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[11] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~30_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~30 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~30_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~30_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~30_I .lut_mask = "6969696966666666"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~30 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[10] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][2]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux179~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][2]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][2]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][2]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][2]~DUPLICATE_I .created_from = "Q(delay_signals[0][2])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~30_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~30 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~30_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~30_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~30_I .lut_mask = "7FFEFFFA00010005"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~30 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~28_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~28 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~28_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~28_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~28_I .lut_mask = "7EFE0105FEFA0105"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~28 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~29_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~29 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~29_I .lut_mask = "5555AAAA5555AAAA"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[9] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~27_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~27 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~27_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~27_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~27_I .lut_mask = "7C03FC07FC03F00F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~27 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[8] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~26_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~26 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~26_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~26_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~26_I .lut_mask = "3B99BB9DBBDD99DD"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~26 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[7] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~9_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~9 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~9_I .lut_mask = "C8C8C8C8C8C8C8C8"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~10_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~10 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~10_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~10_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~10_I .lut_mask = "9113911391139113"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~25_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~9 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~10 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~25 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~25_I .lut_mask = "F0F0CCCC0F0F3333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~24_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~24 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~24_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~24_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~24_I .lut_mask = "599A599AA6A6A6A6"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~24 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~13_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~13 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~13_I .lut_mask = "6969696966666666"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~15_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~15 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~15_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~15_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~15_I .lut_mask = "0F0F0F0FF0F0F0F0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~15 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~181_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][2] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][1] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add38~181 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~182 )); defparam \fp_pow_0002:fp_pow_inst|Add38~181_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~181_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~181_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~145_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][3] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~182 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~145 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~146 )); defparam \fp_pow_0002:fp_pow_inst|Add38~145_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~145_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~145_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~149_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][4] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~146 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~149 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~150 )); defparam \fp_pow_0002:fp_pow_inst|Add38~149_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~149_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~149_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~153_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~150 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~153 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~154 )); defparam \fp_pow_0002:fp_pow_inst|Add38~153_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~153_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~153_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~157_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][6] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~154 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~157 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~158 )); defparam \fp_pow_0002:fp_pow_inst|Add38~157_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~157_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~157_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~161_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][7] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[7] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~158 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~161 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~162 )); defparam \fp_pow_0002:fp_pow_inst|Add38~161_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~161_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~161_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~165_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][8] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[8] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~162 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~165 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~166 )); defparam \fp_pow_0002:fp_pow_inst|Add38~165_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~165_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~165_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~169_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][9] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[9] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~166 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~169 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~170 )); defparam \fp_pow_0002:fp_pow_inst|Add38~169_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~169_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~169_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~173_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[10] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][10] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~170 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~173 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~174 )); defparam \fp_pow_0002:fp_pow_inst|Add38~173_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~173_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~173_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~177_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][11] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[11] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~174 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~177 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~178 )); defparam \fp_pow_0002:fp_pow_inst|Add38~177_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~177_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~177_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~125_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[12] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][12] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~178 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~125 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~126 )); defparam \fp_pow_0002:fp_pow_inst|Add38~125_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~125_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~125_I .lut_mask = "0000CCCC000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~125 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[0][0]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[0][0]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[0][0]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[0][0]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist98|delay_signals[0][0]~DUPLICATE_I .created_from = "Q(delay_signals[0][0])"; dffeas \fp_pow_0002:fp_pow_inst|redist102_cmpReg_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add54~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist102_cmpReg_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist102_cmpReg_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist102_cmpReg_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0]~0_I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist102_sticky_ena_q[0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist102_cmpReg_q[0] ), .combout(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0]~0_I .lut_mask = "00FF00FFFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0]~0_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "FFFFFFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[1]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4564,portadatain_unconnected_wire_4565,portadatain_unconnected_wire_4566,portadatain_unconnected_wire_4567,portadatain_unconnected_wire_4568,portadatain_unconnected_wire_4569,portadatain_unconnected_wire_4570, portadatain_unconnected_wire_4571,portadatain_unconnected_wire_4572,portadatain_unconnected_wire_4573,portadatain_unconnected_wire_4574,portadatain_unconnected_wire_4575,portadatain_unconnected_wire_4576,portadatain_unconnected_wire_4577, portadatain_unconnected_wire_4578,portadatain_unconnected_wire_4579,portadatain_unconnected_wire_4580,portadatain_unconnected_wire_4581,portadatain_unconnected_wire_4582,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[12] }), .portaaddr({portaaddr_unconnected_wire_4583,portaaddr_unconnected_wire_4584,portaaddr_unconnected_wire_4585,portaaddr_unconnected_wire_4586,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4587,portbaddr_unconnected_wire_4588,portbaddr_unconnected_wire_4589,portbaddr_unconnected_wire_4590, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[12] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12 .first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama12 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[21]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[12] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[21] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[21]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[21]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[21]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][21]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4591,portadatain_unconnected_wire_4592,portadatain_unconnected_wire_4593,portadatain_unconnected_wire_4594,portadatain_unconnected_wire_4595,portadatain_unconnected_wire_4596,portadatain_unconnected_wire_4597, portadatain_unconnected_wire_4598,portadatain_unconnected_wire_4599,portadatain_unconnected_wire_4600,portadatain_unconnected_wire_4601,portadatain_unconnected_wire_4602,portadatain_unconnected_wire_4603,portadatain_unconnected_wire_4604, portadatain_unconnected_wire_4605,portadatain_unconnected_wire_4606,portadatain_unconnected_wire_4607,portadatain_unconnected_wire_4608,portadatain_unconnected_wire_4609,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[11] }), .portaaddr({portaaddr_unconnected_wire_4610,portaaddr_unconnected_wire_4611,portaaddr_unconnected_wire_4612,portaaddr_unconnected_wire_4613,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4614,portbaddr_unconnected_wire_4615,portbaddr_unconnected_wire_4616,portbaddr_unconnected_wire_4617, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[11] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11 .first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama11 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[20]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[11] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[20] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[20]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[20]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[20]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[20] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4618,portadatain_unconnected_wire_4619,portadatain_unconnected_wire_4620,portadatain_unconnected_wire_4621,portadatain_unconnected_wire_4622,portadatain_unconnected_wire_4623,portadatain_unconnected_wire_4624, portadatain_unconnected_wire_4625,portadatain_unconnected_wire_4626,portadatain_unconnected_wire_4627,portadatain_unconnected_wire_4628,portadatain_unconnected_wire_4629,portadatain_unconnected_wire_4630,portadatain_unconnected_wire_4631, portadatain_unconnected_wire_4632,portadatain_unconnected_wire_4633,portadatain_unconnected_wire_4634,portadatain_unconnected_wire_4635,portadatain_unconnected_wire_4636,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[10] }), .portaaddr({portaaddr_unconnected_wire_4637,portaaddr_unconnected_wire_4638,portaaddr_unconnected_wire_4639,portaaddr_unconnected_wire_4640,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4641,portbaddr_unconnected_wire_4642,portbaddr_unconnected_wire_4643,portbaddr_unconnected_wire_4644, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[10] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10 .first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama10 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[19]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[10] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[19] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[19]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[19]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[19]~I .lut_mask = "33CC33CC33CC33CC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[9]~feeder ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist3|delay_signals[0][33] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|prodYLogX_uid93_fpPowrTest_result_add_0_0_p2_of_2_o[6] ), .q(\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[9] )); defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[9]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4645,portadatain_unconnected_wire_4646,portadatain_unconnected_wire_4647,portadatain_unconnected_wire_4648,portadatain_unconnected_wire_4649,portadatain_unconnected_wire_4650,portadatain_unconnected_wire_4651, portadatain_unconnected_wire_4652,portadatain_unconnected_wire_4653,portadatain_unconnected_wire_4654,portadatain_unconnected_wire_4655,portadatain_unconnected_wire_4656,portadatain_unconnected_wire_4657,portadatain_unconnected_wire_4658, portadatain_unconnected_wire_4659,portadatain_unconnected_wire_4660,portadatain_unconnected_wire_4661,portadatain_unconnected_wire_4662,portadatain_unconnected_wire_4663,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[9] }), .portaaddr({portaaddr_unconnected_wire_4664,portaaddr_unconnected_wire_4665,portaaddr_unconnected_wire_4666,portaaddr_unconnected_wire_4667,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4668,portbaddr_unconnected_wire_4669,portbaddr_unconnected_wire_4670,portbaddr_unconnected_wire_4671, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[9] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9 .first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama9 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[18]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[9] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[18] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[18]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[18]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[18]~I .lut_mask = "33CC33CC33CC33CC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4672,portadatain_unconnected_wire_4673,portadatain_unconnected_wire_4674,portadatain_unconnected_wire_4675,portadatain_unconnected_wire_4676,portadatain_unconnected_wire_4677,portadatain_unconnected_wire_4678, portadatain_unconnected_wire_4679,portadatain_unconnected_wire_4680,portadatain_unconnected_wire_4681,portadatain_unconnected_wire_4682,portadatain_unconnected_wire_4683,portadatain_unconnected_wire_4684,portadatain_unconnected_wire_4685, portadatain_unconnected_wire_4686,portadatain_unconnected_wire_4687,portadatain_unconnected_wire_4688,portadatain_unconnected_wire_4689,portadatain_unconnected_wire_4690,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[8] }), .portaaddr({portaaddr_unconnected_wire_4691,portaaddr_unconnected_wire_4692,portaaddr_unconnected_wire_4693,portaaddr_unconnected_wire_4694,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4695,portbaddr_unconnected_wire_4696,portbaddr_unconnected_wire_4697,portbaddr_unconnected_wire_4698, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[8] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8 .first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama8 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[17]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[8] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[17] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[17]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[17]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[17]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4699,portadatain_unconnected_wire_4700,portadatain_unconnected_wire_4701,portadatain_unconnected_wire_4702,portadatain_unconnected_wire_4703,portadatain_unconnected_wire_4704,portadatain_unconnected_wire_4705, portadatain_unconnected_wire_4706,portadatain_unconnected_wire_4707,portadatain_unconnected_wire_4708,portadatain_unconnected_wire_4709,portadatain_unconnected_wire_4710,portadatain_unconnected_wire_4711,portadatain_unconnected_wire_4712, portadatain_unconnected_wire_4713,portadatain_unconnected_wire_4714,portadatain_unconnected_wire_4715,portadatain_unconnected_wire_4716,portadatain_unconnected_wire_4717,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[7] }), .portaaddr({portaaddr_unconnected_wire_4718,portaaddr_unconnected_wire_4719,portaaddr_unconnected_wire_4720,portaaddr_unconnected_wire_4721,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4722,portbaddr_unconnected_wire_4723,portbaddr_unconnected_wire_4724,portbaddr_unconnected_wire_4725, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[7] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7 .first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama7 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[16]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[7] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[16] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[16]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[16]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[16]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4726,portadatain_unconnected_wire_4727,portadatain_unconnected_wire_4728,portadatain_unconnected_wire_4729,portadatain_unconnected_wire_4730,portadatain_unconnected_wire_4731,portadatain_unconnected_wire_4732, portadatain_unconnected_wire_4733,portadatain_unconnected_wire_4734,portadatain_unconnected_wire_4735,portadatain_unconnected_wire_4736,portadatain_unconnected_wire_4737,portadatain_unconnected_wire_4738,portadatain_unconnected_wire_4739, portadatain_unconnected_wire_4740,portadatain_unconnected_wire_4741,portadatain_unconnected_wire_4742,portadatain_unconnected_wire_4743,portadatain_unconnected_wire_4744,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[6] }), .portaaddr({portaaddr_unconnected_wire_4745,portaaddr_unconnected_wire_4746,portaaddr_unconnected_wire_4747,portaaddr_unconnected_wire_4748,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4749,portbaddr_unconnected_wire_4750,portbaddr_unconnected_wire_4751,portbaddr_unconnected_wire_4752, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[6] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6 .first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama6 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[15]~I ( .datae(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[6] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[15] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[15]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[15]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[15]~I .lut_mask = "0000FFFFFFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4753,portadatain_unconnected_wire_4754,portadatain_unconnected_wire_4755,portadatain_unconnected_wire_4756,portadatain_unconnected_wire_4757,portadatain_unconnected_wire_4758,portadatain_unconnected_wire_4759, portadatain_unconnected_wire_4760,portadatain_unconnected_wire_4761,portadatain_unconnected_wire_4762,portadatain_unconnected_wire_4763,portadatain_unconnected_wire_4764,portadatain_unconnected_wire_4765,portadatain_unconnected_wire_4766, portadatain_unconnected_wire_4767,portadatain_unconnected_wire_4768,portadatain_unconnected_wire_4769,portadatain_unconnected_wire_4770,portadatain_unconnected_wire_4771,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[5] }), .portaaddr({portaaddr_unconnected_wire_4772,portaaddr_unconnected_wire_4773,portaaddr_unconnected_wire_4774,portaaddr_unconnected_wire_4775,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4776,portbaddr_unconnected_wire_4777,portbaddr_unconnected_wire_4778,portbaddr_unconnected_wire_4779, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[5] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5 .first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama5 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[14]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[5] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[14] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[14]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[14]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[14]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[14] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4780,portadatain_unconnected_wire_4781,portadatain_unconnected_wire_4782,portadatain_unconnected_wire_4783,portadatain_unconnected_wire_4784,portadatain_unconnected_wire_4785,portadatain_unconnected_wire_4786, portadatain_unconnected_wire_4787,portadatain_unconnected_wire_4788,portadatain_unconnected_wire_4789,portadatain_unconnected_wire_4790,portadatain_unconnected_wire_4791,portadatain_unconnected_wire_4792,portadatain_unconnected_wire_4793, portadatain_unconnected_wire_4794,portadatain_unconnected_wire_4795,portadatain_unconnected_wire_4796,portadatain_unconnected_wire_4797,portadatain_unconnected_wire_4798,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[4] }), .portaaddr({portaaddr_unconnected_wire_4799,portaaddr_unconnected_wire_4800,portaaddr_unconnected_wire_4801,portaaddr_unconnected_wire_4802,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4803,portbaddr_unconnected_wire_4804,portbaddr_unconnected_wire_4805,portbaddr_unconnected_wire_4806, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[4] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4 .first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama4 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[13]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[4] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[13] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[13]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[13]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[13]~I .lut_mask = "3C3C3C3C3C3C3C3C"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4807,portadatain_unconnected_wire_4808,portadatain_unconnected_wire_4809,portadatain_unconnected_wire_4810,portadatain_unconnected_wire_4811,portadatain_unconnected_wire_4812,portadatain_unconnected_wire_4813, portadatain_unconnected_wire_4814,portadatain_unconnected_wire_4815,portadatain_unconnected_wire_4816,portadatain_unconnected_wire_4817,portadatain_unconnected_wire_4818,portadatain_unconnected_wire_4819,portadatain_unconnected_wire_4820, portadatain_unconnected_wire_4821,portadatain_unconnected_wire_4822,portadatain_unconnected_wire_4823,portadatain_unconnected_wire_4824,portadatain_unconnected_wire_4825,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[3] }), .portaaddr({portaaddr_unconnected_wire_4826,portaaddr_unconnected_wire_4827,portaaddr_unconnected_wire_4828,portaaddr_unconnected_wire_4829,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4830,portbaddr_unconnected_wire_4831,portbaddr_unconnected_wire_4832,portbaddr_unconnected_wire_4833, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[3] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3 .first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama3 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[12]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[3] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[12] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[12]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[12]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[12]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4834,portadatain_unconnected_wire_4835,portadatain_unconnected_wire_4836,portadatain_unconnected_wire_4837,portadatain_unconnected_wire_4838,portadatain_unconnected_wire_4839,portadatain_unconnected_wire_4840, portadatain_unconnected_wire_4841,portadatain_unconnected_wire_4842,portadatain_unconnected_wire_4843,portadatain_unconnected_wire_4844,portadatain_unconnected_wire_4845,portadatain_unconnected_wire_4846,portadatain_unconnected_wire_4847, portadatain_unconnected_wire_4848,portadatain_unconnected_wire_4849,portadatain_unconnected_wire_4850,portadatain_unconnected_wire_4851,portadatain_unconnected_wire_4852,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[2] }), .portaaddr({portaaddr_unconnected_wire_4853,portaaddr_unconnected_wire_4854,portaaddr_unconnected_wire_4855,portaaddr_unconnected_wire_4856,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4857,portbaddr_unconnected_wire_4858,portbaddr_unconnected_wire_4859,portbaddr_unconnected_wire_4860, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[2] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2 .first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama2 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[11]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[2] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[11] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[11]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[11]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[11]~I .lut_mask = "33CC33CC33CC33CC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4861,portadatain_unconnected_wire_4862,portadatain_unconnected_wire_4863,portadatain_unconnected_wire_4864,portadatain_unconnected_wire_4865,portadatain_unconnected_wire_4866,portadatain_unconnected_wire_4867, portadatain_unconnected_wire_4868,portadatain_unconnected_wire_4869,portadatain_unconnected_wire_4870,portadatain_unconnected_wire_4871,portadatain_unconnected_wire_4872,portadatain_unconnected_wire_4873,portadatain_unconnected_wire_4874, portadatain_unconnected_wire_4875,portadatain_unconnected_wire_4876,portadatain_unconnected_wire_4877,portadatain_unconnected_wire_4878,portadatain_unconnected_wire_4879,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[1] }), .portaaddr({portaaddr_unconnected_wire_4880,portaaddr_unconnected_wire_4881,portaaddr_unconnected_wire_4882,portaaddr_unconnected_wire_4883,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4884,portbaddr_unconnected_wire_4885,portbaddr_unconnected_wire_4886,portbaddr_unconnected_wire_4887, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[1] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1 .first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama1 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[10]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[1] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[10] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[10]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[10]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[10]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4888,portadatain_unconnected_wire_4889,portadatain_unconnected_wire_4890,portadatain_unconnected_wire_4891,portadatain_unconnected_wire_4892,portadatain_unconnected_wire_4893,portadatain_unconnected_wire_4894, portadatain_unconnected_wire_4895,portadatain_unconnected_wire_4896,portadatain_unconnected_wire_4897,portadatain_unconnected_wire_4898,portadatain_unconnected_wire_4899,portadatain_unconnected_wire_4900,portadatain_unconnected_wire_4901, portadatain_unconnected_wire_4902,portadatain_unconnected_wire_4903,portadatain_unconnected_wire_4904,portadatain_unconnected_wire_4905,portadatain_unconnected_wire_4906,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[0] }), .portaaddr({portaaddr_unconnected_wire_4907,portaaddr_unconnected_wire_4908,portaaddr_unconnected_wire_4909,portaaddr_unconnected_wire_4910,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4911,portbaddr_unconnected_wire_4912,portbaddr_unconnected_wire_4913,portbaddr_unconnected_wire_4914, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[9]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[9] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[9]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[9]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[9]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~121_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][9] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][43] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add40~121 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~122 )); defparam \fp_pow_0002:fp_pow_inst|Add40~121_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~121_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~121_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~133_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][10] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~122 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~133 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~134 )); defparam \fp_pow_0002:fp_pow_inst|Add40~133_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~133_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~133_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~129_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][11] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~134 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~129 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~130 )); defparam \fp_pow_0002:fp_pow_inst|Add40~129_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~129_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~129_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~137_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][12] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~130 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~137 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~138 )); defparam \fp_pow_0002:fp_pow_inst|Add40~137_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~137_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~137_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~125_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][13] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~138 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~125 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~126 )); defparam \fp_pow_0002:fp_pow_inst|Add40~125_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~125_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~125_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~117_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][14] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~126 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~117 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~118 )); defparam \fp_pow_0002:fp_pow_inst|Add40~117_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~117_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~117_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~113_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][15] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~118 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~113 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~114 )); defparam \fp_pow_0002:fp_pow_inst|Add40~113_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~113_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~113_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~109_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][16] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~114 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~109 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~110 )); defparam \fp_pow_0002:fp_pow_inst|Add40~109_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~109_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~109_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~105_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][17] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~110 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~105 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~106 )); defparam \fp_pow_0002:fp_pow_inst|Add40~105_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~105_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~105_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~101_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][18] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~106 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~101 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~102 )); defparam \fp_pow_0002:fp_pow_inst|Add40~101_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~101_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~101_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~97_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][19] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~102 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~97 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~98 )); defparam \fp_pow_0002:fp_pow_inst|Add40~97_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~97_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~97_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~93_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][20] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~98 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~93 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~94 )); defparam \fp_pow_0002:fp_pow_inst|Add40~93_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~93_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~93_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~89_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][21] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~94 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~89 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~90 )); defparam \fp_pow_0002:fp_pow_inst|Add40~89_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~89_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~89_I .lut_mask = "0000FFFF00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~89 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][21]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4915,portadatain_unconnected_wire_4916,portadatain_unconnected_wire_4917,portadatain_unconnected_wire_4918,portadatain_unconnected_wire_4919,portadatain_unconnected_wire_4920,portadatain_unconnected_wire_4921, portadatain_unconnected_wire_4922,portadatain_unconnected_wire_4923,portadatain_unconnected_wire_4924,portadatain_unconnected_wire_4925,portadatain_unconnected_wire_4926,portadatain_unconnected_wire_4927,portadatain_unconnected_wire_4928, portadatain_unconnected_wire_4929,portadatain_unconnected_wire_4930,portadatain_unconnected_wire_4931,portadatain_unconnected_wire_4932,portadatain_unconnected_wire_4933,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[28] }), .portaaddr({portaaddr_unconnected_wire_4934,portaaddr_unconnected_wire_4935,portaaddr_unconnected_wire_4936,portaaddr_unconnected_wire_4937,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4938,portbaddr_unconnected_wire_4939,portbaddr_unconnected_wire_4940,portbaddr_unconnected_wire_4941, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[28] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28 .first_bit_number = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama28 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[37]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[28] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[37] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[37]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[37]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[37]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[37] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][37] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][37]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4942,portadatain_unconnected_wire_4943,portadatain_unconnected_wire_4944,portadatain_unconnected_wire_4945,portadatain_unconnected_wire_4946,portadatain_unconnected_wire_4947,portadatain_unconnected_wire_4948, portadatain_unconnected_wire_4949,portadatain_unconnected_wire_4950,portadatain_unconnected_wire_4951,portadatain_unconnected_wire_4952,portadatain_unconnected_wire_4953,portadatain_unconnected_wire_4954,portadatain_unconnected_wire_4955, portadatain_unconnected_wire_4956,portadatain_unconnected_wire_4957,portadatain_unconnected_wire_4958,portadatain_unconnected_wire_4959,portadatain_unconnected_wire_4960,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[27] }), .portaaddr({portaaddr_unconnected_wire_4961,portaaddr_unconnected_wire_4962,portaaddr_unconnected_wire_4963,portaaddr_unconnected_wire_4964,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4965,portbaddr_unconnected_wire_4966,portbaddr_unconnected_wire_4967,portbaddr_unconnected_wire_4968, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[27] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27 .first_bit_number = 27; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama27 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[36]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[27] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[36] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[36]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[36]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[36]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][36]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[36] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][36] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][36]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4969,portadatain_unconnected_wire_4970,portadatain_unconnected_wire_4971,portadatain_unconnected_wire_4972,portadatain_unconnected_wire_4973,portadatain_unconnected_wire_4974,portadatain_unconnected_wire_4975, portadatain_unconnected_wire_4976,portadatain_unconnected_wire_4977,portadatain_unconnected_wire_4978,portadatain_unconnected_wire_4979,portadatain_unconnected_wire_4980,portadatain_unconnected_wire_4981,portadatain_unconnected_wire_4982, portadatain_unconnected_wire_4983,portadatain_unconnected_wire_4984,portadatain_unconnected_wire_4985,portadatain_unconnected_wire_4986,portadatain_unconnected_wire_4987,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[26] }), .portaaddr({portaaddr_unconnected_wire_4988,portaaddr_unconnected_wire_4989,portaaddr_unconnected_wire_4990,portaaddr_unconnected_wire_4991,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_4992,portbaddr_unconnected_wire_4993,portbaddr_unconnected_wire_4994,portbaddr_unconnected_wire_4995, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[26] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26 .first_bit_number = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama26 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[35]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[26] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[35] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[35]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[35]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[35]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[35] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][35]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_4996,portadatain_unconnected_wire_4997,portadatain_unconnected_wire_4998,portadatain_unconnected_wire_4999,portadatain_unconnected_wire_5000,portadatain_unconnected_wire_5001,portadatain_unconnected_wire_5002, portadatain_unconnected_wire_5003,portadatain_unconnected_wire_5004,portadatain_unconnected_wire_5005,portadatain_unconnected_wire_5006,portadatain_unconnected_wire_5007,portadatain_unconnected_wire_5008,portadatain_unconnected_wire_5009, portadatain_unconnected_wire_5010,portadatain_unconnected_wire_5011,portadatain_unconnected_wire_5012,portadatain_unconnected_wire_5013,portadatain_unconnected_wire_5014,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[25] }), .portaaddr({portaaddr_unconnected_wire_5015,portaaddr_unconnected_wire_5016,portaaddr_unconnected_wire_5017,portaaddr_unconnected_wire_5018,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5019,portbaddr_unconnected_wire_5020,portbaddr_unconnected_wire_5021,portbaddr_unconnected_wire_5022, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[25] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25 .first_bit_number = 25; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama25 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[34]~I ( .datae(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[25] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[34] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[34]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[34]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[34]~I .lut_mask = "0000FFFFFFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[34] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][34]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5023,portadatain_unconnected_wire_5024,portadatain_unconnected_wire_5025,portadatain_unconnected_wire_5026,portadatain_unconnected_wire_5027,portadatain_unconnected_wire_5028,portadatain_unconnected_wire_5029, portadatain_unconnected_wire_5030,portadatain_unconnected_wire_5031,portadatain_unconnected_wire_5032,portadatain_unconnected_wire_5033,portadatain_unconnected_wire_5034,portadatain_unconnected_wire_5035,portadatain_unconnected_wire_5036, portadatain_unconnected_wire_5037,portadatain_unconnected_wire_5038,portadatain_unconnected_wire_5039,portadatain_unconnected_wire_5040,portadatain_unconnected_wire_5041,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[24] }), .portaaddr({portaaddr_unconnected_wire_5042,portaaddr_unconnected_wire_5043,portaaddr_unconnected_wire_5044,portaaddr_unconnected_wire_5045,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5046,portbaddr_unconnected_wire_5047,portbaddr_unconnected_wire_5048,portbaddr_unconnected_wire_5049, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[24] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24 .first_bit_number = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama24 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[33]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[24] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[33] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[33]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[33]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[33]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[33] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][33]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5050,portadatain_unconnected_wire_5051,portadatain_unconnected_wire_5052,portadatain_unconnected_wire_5053,portadatain_unconnected_wire_5054,portadatain_unconnected_wire_5055,portadatain_unconnected_wire_5056, portadatain_unconnected_wire_5057,portadatain_unconnected_wire_5058,portadatain_unconnected_wire_5059,portadatain_unconnected_wire_5060,portadatain_unconnected_wire_5061,portadatain_unconnected_wire_5062,portadatain_unconnected_wire_5063, portadatain_unconnected_wire_5064,portadatain_unconnected_wire_5065,portadatain_unconnected_wire_5066,portadatain_unconnected_wire_5067,portadatain_unconnected_wire_5068,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[23] }), .portaaddr({portaaddr_unconnected_wire_5069,portaaddr_unconnected_wire_5070,portaaddr_unconnected_wire_5071,portaaddr_unconnected_wire_5072,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5073,portbaddr_unconnected_wire_5074,portbaddr_unconnected_wire_5075,portbaddr_unconnected_wire_5076, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[23] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23 .first_bit_number = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama23 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[32]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[23] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[32] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[32]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[32]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[32]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[32] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][32]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5077,portadatain_unconnected_wire_5078,portadatain_unconnected_wire_5079,portadatain_unconnected_wire_5080,portadatain_unconnected_wire_5081,portadatain_unconnected_wire_5082,portadatain_unconnected_wire_5083, portadatain_unconnected_wire_5084,portadatain_unconnected_wire_5085,portadatain_unconnected_wire_5086,portadatain_unconnected_wire_5087,portadatain_unconnected_wire_5088,portadatain_unconnected_wire_5089,portadatain_unconnected_wire_5090, portadatain_unconnected_wire_5091,portadatain_unconnected_wire_5092,portadatain_unconnected_wire_5093,portadatain_unconnected_wire_5094,portadatain_unconnected_wire_5095,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[22] }), .portaaddr({portaaddr_unconnected_wire_5096,portaaddr_unconnected_wire_5097,portaaddr_unconnected_wire_5098,portaaddr_unconnected_wire_5099,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5100,portbaddr_unconnected_wire_5101,portbaddr_unconnected_wire_5102,portbaddr_unconnected_wire_5103, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[22] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22 .first_bit_number = 22; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama22 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[31]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[22] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[31] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[31]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[31]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[31]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[31] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][31]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5104,portadatain_unconnected_wire_5105,portadatain_unconnected_wire_5106,portadatain_unconnected_wire_5107,portadatain_unconnected_wire_5108,portadatain_unconnected_wire_5109,portadatain_unconnected_wire_5110, portadatain_unconnected_wire_5111,portadatain_unconnected_wire_5112,portadatain_unconnected_wire_5113,portadatain_unconnected_wire_5114,portadatain_unconnected_wire_5115,portadatain_unconnected_wire_5116,portadatain_unconnected_wire_5117, portadatain_unconnected_wire_5118,portadatain_unconnected_wire_5119,portadatain_unconnected_wire_5120,portadatain_unconnected_wire_5121,portadatain_unconnected_wire_5122,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[21] }), .portaaddr({portaaddr_unconnected_wire_5123,portaaddr_unconnected_wire_5124,portaaddr_unconnected_wire_5125,portaaddr_unconnected_wire_5126,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5127,portbaddr_unconnected_wire_5128,portbaddr_unconnected_wire_5129,portbaddr_unconnected_wire_5130, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[21] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21 .first_bit_number = 21; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama21 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[30]~I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[21] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[30] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[30]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[30]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[30]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[30] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][30]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5131,portadatain_unconnected_wire_5132,portadatain_unconnected_wire_5133,portadatain_unconnected_wire_5134,portadatain_unconnected_wire_5135,portadatain_unconnected_wire_5136,portadatain_unconnected_wire_5137, portadatain_unconnected_wire_5138,portadatain_unconnected_wire_5139,portadatain_unconnected_wire_5140,portadatain_unconnected_wire_5141,portadatain_unconnected_wire_5142,portadatain_unconnected_wire_5143,portadatain_unconnected_wire_5144, portadatain_unconnected_wire_5145,portadatain_unconnected_wire_5146,portadatain_unconnected_wire_5147,portadatain_unconnected_wire_5148,portadatain_unconnected_wire_5149,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[20] }), .portaaddr({portaaddr_unconnected_wire_5150,portaaddr_unconnected_wire_5151,portaaddr_unconnected_wire_5152,portaaddr_unconnected_wire_5153,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5154,portbaddr_unconnected_wire_5155,portbaddr_unconnected_wire_5156,portbaddr_unconnected_wire_5157, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[20] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20 .first_bit_number = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama20 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[29]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[20] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[29] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[29]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[29]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[29]~I .lut_mask = "3C3C3C3C3C3C3C3C"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[29] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][29]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5158,portadatain_unconnected_wire_5159,portadatain_unconnected_wire_5160,portadatain_unconnected_wire_5161,portadatain_unconnected_wire_5162,portadatain_unconnected_wire_5163,portadatain_unconnected_wire_5164, portadatain_unconnected_wire_5165,portadatain_unconnected_wire_5166,portadatain_unconnected_wire_5167,portadatain_unconnected_wire_5168,portadatain_unconnected_wire_5169,portadatain_unconnected_wire_5170,portadatain_unconnected_wire_5171, portadatain_unconnected_wire_5172,portadatain_unconnected_wire_5173,portadatain_unconnected_wire_5174,portadatain_unconnected_wire_5175,portadatain_unconnected_wire_5176,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[19] }), .portaaddr({portaaddr_unconnected_wire_5177,portaaddr_unconnected_wire_5178,portaaddr_unconnected_wire_5179,portaaddr_unconnected_wire_5180,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5181,portbaddr_unconnected_wire_5182,portbaddr_unconnected_wire_5183,portbaddr_unconnected_wire_5184, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[19] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19 .first_bit_number = 19; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama19 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[28]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[19] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[28] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[28]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[28]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[28]~I .lut_mask = "33CC33CC33CC33CC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[28] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][28]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5185,portadatain_unconnected_wire_5186,portadatain_unconnected_wire_5187,portadatain_unconnected_wire_5188,portadatain_unconnected_wire_5189,portadatain_unconnected_wire_5190,portadatain_unconnected_wire_5191, portadatain_unconnected_wire_5192,portadatain_unconnected_wire_5193,portadatain_unconnected_wire_5194,portadatain_unconnected_wire_5195,portadatain_unconnected_wire_5196,portadatain_unconnected_wire_5197,portadatain_unconnected_wire_5198, portadatain_unconnected_wire_5199,portadatain_unconnected_wire_5200,portadatain_unconnected_wire_5201,portadatain_unconnected_wire_5202,portadatain_unconnected_wire_5203,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[18] }), .portaaddr({portaaddr_unconnected_wire_5204,portaaddr_unconnected_wire_5205,portaaddr_unconnected_wire_5206,portaaddr_unconnected_wire_5207,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5208,portbaddr_unconnected_wire_5209,portbaddr_unconnected_wire_5210,portbaddr_unconnected_wire_5211, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[18] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18 .first_bit_number = 18; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama18 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[27]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[18] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[27] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[27]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[27]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[27]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[27] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][27]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5212,portadatain_unconnected_wire_5213,portadatain_unconnected_wire_5214,portadatain_unconnected_wire_5215,portadatain_unconnected_wire_5216,portadatain_unconnected_wire_5217,portadatain_unconnected_wire_5218, portadatain_unconnected_wire_5219,portadatain_unconnected_wire_5220,portadatain_unconnected_wire_5221,portadatain_unconnected_wire_5222,portadatain_unconnected_wire_5223,portadatain_unconnected_wire_5224,portadatain_unconnected_wire_5225, portadatain_unconnected_wire_5226,portadatain_unconnected_wire_5227,portadatain_unconnected_wire_5228,portadatain_unconnected_wire_5229,portadatain_unconnected_wire_5230,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[17] }), .portaaddr({portaaddr_unconnected_wire_5231,portaaddr_unconnected_wire_5232,portaaddr_unconnected_wire_5233,portaaddr_unconnected_wire_5234,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5235,portbaddr_unconnected_wire_5236,portbaddr_unconnected_wire_5237,portbaddr_unconnected_wire_5238, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[17] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17 .first_bit_number = 17; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama17 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[26]~I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[17] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[26] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[26]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[26]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[26]~I .lut_mask = "0F0F0F0FF0F0F0F0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[26] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][26]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5239,portadatain_unconnected_wire_5240,portadatain_unconnected_wire_5241,portadatain_unconnected_wire_5242,portadatain_unconnected_wire_5243,portadatain_unconnected_wire_5244,portadatain_unconnected_wire_5245, portadatain_unconnected_wire_5246,portadatain_unconnected_wire_5247,portadatain_unconnected_wire_5248,portadatain_unconnected_wire_5249,portadatain_unconnected_wire_5250,portadatain_unconnected_wire_5251,portadatain_unconnected_wire_5252, portadatain_unconnected_wire_5253,portadatain_unconnected_wire_5254,portadatain_unconnected_wire_5255,portadatain_unconnected_wire_5256,portadatain_unconnected_wire_5257,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[16] }), .portaaddr({portaaddr_unconnected_wire_5258,portaaddr_unconnected_wire_5259,portaaddr_unconnected_wire_5260,portaaddr_unconnected_wire_5261,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5262,portbaddr_unconnected_wire_5263,portbaddr_unconnected_wire_5264,portbaddr_unconnected_wire_5265, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[16] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16 .first_bit_number = 16; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama16 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[25]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[16] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[25] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[25]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[25]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[25]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[25] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][25]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5266,portadatain_unconnected_wire_5267,portadatain_unconnected_wire_5268,portadatain_unconnected_wire_5269,portadatain_unconnected_wire_5270,portadatain_unconnected_wire_5271,portadatain_unconnected_wire_5272, portadatain_unconnected_wire_5273,portadatain_unconnected_wire_5274,portadatain_unconnected_wire_5275,portadatain_unconnected_wire_5276,portadatain_unconnected_wire_5277,portadatain_unconnected_wire_5278,portadatain_unconnected_wire_5279, portadatain_unconnected_wire_5280,portadatain_unconnected_wire_5281,portadatain_unconnected_wire_5282,portadatain_unconnected_wire_5283,portadatain_unconnected_wire_5284,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[15] }), .portaaddr({portaaddr_unconnected_wire_5285,portaaddr_unconnected_wire_5286,portaaddr_unconnected_wire_5287,portaaddr_unconnected_wire_5288,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5289,portbaddr_unconnected_wire_5290,portbaddr_unconnected_wire_5291,portbaddr_unconnected_wire_5292, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[15] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15 .first_bit_number = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama15 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[24]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[15] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[24] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[24]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[24]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[24]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[24] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5293,portadatain_unconnected_wire_5294,portadatain_unconnected_wire_5295,portadatain_unconnected_wire_5296,portadatain_unconnected_wire_5297,portadatain_unconnected_wire_5298,portadatain_unconnected_wire_5299, portadatain_unconnected_wire_5300,portadatain_unconnected_wire_5301,portadatain_unconnected_wire_5302,portadatain_unconnected_wire_5303,portadatain_unconnected_wire_5304,portadatain_unconnected_wire_5305,portadatain_unconnected_wire_5306, portadatain_unconnected_wire_5307,portadatain_unconnected_wire_5308,portadatain_unconnected_wire_5309,portadatain_unconnected_wire_5310,portadatain_unconnected_wire_5311,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[14] }), .portaaddr({portaaddr_unconnected_wire_5312,portaaddr_unconnected_wire_5313,portaaddr_unconnected_wire_5314,portaaddr_unconnected_wire_5315,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5316,portbaddr_unconnected_wire_5317,portbaddr_unconnected_wire_5318,portbaddr_unconnected_wire_5319, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[14] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14 .first_bit_number = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama14 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[23]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[14] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[23] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[23]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[23]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[23]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[23] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5320,portadatain_unconnected_wire_5321,portadatain_unconnected_wire_5322,portadatain_unconnected_wire_5323,portadatain_unconnected_wire_5324,portadatain_unconnected_wire_5325,portadatain_unconnected_wire_5326, portadatain_unconnected_wire_5327,portadatain_unconnected_wire_5328,portadatain_unconnected_wire_5329,portadatain_unconnected_wire_5330,portadatain_unconnected_wire_5331,portadatain_unconnected_wire_5332,portadatain_unconnected_wire_5333, portadatain_unconnected_wire_5334,portadatain_unconnected_wire_5335,portadatain_unconnected_wire_5336,portadatain_unconnected_wire_5337,portadatain_unconnected_wire_5338,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[13] }), .portaaddr({portaaddr_unconnected_wire_5339,portaaddr_unconnected_wire_5340,portaaddr_unconnected_wire_5341,portaaddr_unconnected_wire_5342,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5343,portbaddr_unconnected_wire_5344,portbaddr_unconnected_wire_5345,portbaddr_unconnected_wire_5346, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[13] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13 .first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama13 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[22]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[13] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[22] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[22]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[22]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[22]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[22] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~85_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][22] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~90 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~85 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~86 )); defparam \fp_pow_0002:fp_pow_inst|Add40~85_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~85_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~85_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~81_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][23] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~86 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~81 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~82 )); defparam \fp_pow_0002:fp_pow_inst|Add40~81_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~81_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~81_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~77_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~82 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~78 )); defparam \fp_pow_0002:fp_pow_inst|Add40~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~77_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~73_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][25] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~73 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~74 )); defparam \fp_pow_0002:fp_pow_inst|Add40~73_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~73_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~73_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~5_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][26] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~74 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~6 )); defparam \fp_pow_0002:fp_pow_inst|Add40~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~5_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~41_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][27] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~42 )); defparam \fp_pow_0002:fp_pow_inst|Add40~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~41_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~25_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][28] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~26 )); defparam \fp_pow_0002:fp_pow_inst|Add40~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~25_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~57_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][29] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~57 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~58 )); defparam \fp_pow_0002:fp_pow_inst|Add40~57_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~57_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~57_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~17_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][30] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~58 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~18 )); defparam \fp_pow_0002:fp_pow_inst|Add40~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~17_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~49_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][31] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~50 )); defparam \fp_pow_0002:fp_pow_inst|Add40~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~49_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~33_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][32] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~34 )); defparam \fp_pow_0002:fp_pow_inst|Add40~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~33_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~65_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][33] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~65 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~66 )); defparam \fp_pow_0002:fp_pow_inst|Add40~65_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~65_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~65_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~13_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][34] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~66 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~14 )); defparam \fp_pow_0002:fp_pow_inst|Add40~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~13_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~45_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][35] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~46 )); defparam \fp_pow_0002:fp_pow_inst|Add40~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~45_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~29_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][36] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~30 )); defparam \fp_pow_0002:fp_pow_inst|Add40~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~29_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~61_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][37] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~62 )); defparam \fp_pow_0002:fp_pow_inst|Add40~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~61_I .lut_mask = "0000FFFF00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~61 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][37] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][37]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5347,portadatain_unconnected_wire_5348,portadatain_unconnected_wire_5349,portadatain_unconnected_wire_5350,portadatain_unconnected_wire_5351,portadatain_unconnected_wire_5352,portadatain_unconnected_wire_5353, portadatain_unconnected_wire_5354,portadatain_unconnected_wire_5355,portadatain_unconnected_wire_5356,portadatain_unconnected_wire_5357,portadatain_unconnected_wire_5358,portadatain_unconnected_wire_5359,portadatain_unconnected_wire_5360, portadatain_unconnected_wire_5361,portadatain_unconnected_wire_5362,portadatain_unconnected_wire_5363,portadatain_unconnected_wire_5364,portadatain_unconnected_wire_5365,\vcc }), .portaaddr({portaaddr_unconnected_wire_5366,portaaddr_unconnected_wire_5367,portaaddr_unconnected_wire_5368,portaaddr_unconnected_wire_5369,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5370,portbaddr_unconnected_wire_5371,portbaddr_unconnected_wire_5372,portbaddr_unconnected_wire_5373, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[33] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33 .first_bit_number = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama33 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[42]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[33] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[42] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[42]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[42]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[42]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][42]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[42] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][42] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][42]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5374,portadatain_unconnected_wire_5375,portadatain_unconnected_wire_5376,portadatain_unconnected_wire_5377,portadatain_unconnected_wire_5378,portadatain_unconnected_wire_5379,portadatain_unconnected_wire_5380, portadatain_unconnected_wire_5381,portadatain_unconnected_wire_5382,portadatain_unconnected_wire_5383,portadatain_unconnected_wire_5384,portadatain_unconnected_wire_5385,portadatain_unconnected_wire_5386,portadatain_unconnected_wire_5387, portadatain_unconnected_wire_5388,portadatain_unconnected_wire_5389,portadatain_unconnected_wire_5390,portadatain_unconnected_wire_5391,portadatain_unconnected_wire_5392,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[32] }), .portaaddr({portaaddr_unconnected_wire_5393,portaaddr_unconnected_wire_5394,portaaddr_unconnected_wire_5395,portaaddr_unconnected_wire_5396,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5397,portbaddr_unconnected_wire_5398,portbaddr_unconnected_wire_5399,portbaddr_unconnected_wire_5400, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[32] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32 .first_bit_number = 32; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama32 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[41]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[32] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[41] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[41]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[41]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[41]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][41]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[41] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][41] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][41]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5401,portadatain_unconnected_wire_5402,portadatain_unconnected_wire_5403,portadatain_unconnected_wire_5404,portadatain_unconnected_wire_5405,portadatain_unconnected_wire_5406,portadatain_unconnected_wire_5407, portadatain_unconnected_wire_5408,portadatain_unconnected_wire_5409,portadatain_unconnected_wire_5410,portadatain_unconnected_wire_5411,portadatain_unconnected_wire_5412,portadatain_unconnected_wire_5413,portadatain_unconnected_wire_5414, portadatain_unconnected_wire_5415,portadatain_unconnected_wire_5416,portadatain_unconnected_wire_5417,portadatain_unconnected_wire_5418,portadatain_unconnected_wire_5419,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[31] }), .portaaddr({portaaddr_unconnected_wire_5420,portaaddr_unconnected_wire_5421,portaaddr_unconnected_wire_5422,portaaddr_unconnected_wire_5423,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5424,portbaddr_unconnected_wire_5425,portbaddr_unconnected_wire_5426,portbaddr_unconnected_wire_5427, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[31] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31 .first_bit_number = 31; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama31 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[40]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[31] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[40] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[40]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[40]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[40]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][40]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[40] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][40] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][40]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5428,portadatain_unconnected_wire_5429,portadatain_unconnected_wire_5430,portadatain_unconnected_wire_5431,portadatain_unconnected_wire_5432,portadatain_unconnected_wire_5433,portadatain_unconnected_wire_5434, portadatain_unconnected_wire_5435,portadatain_unconnected_wire_5436,portadatain_unconnected_wire_5437,portadatain_unconnected_wire_5438,portadatain_unconnected_wire_5439,portadatain_unconnected_wire_5440,portadatain_unconnected_wire_5441, portadatain_unconnected_wire_5442,portadatain_unconnected_wire_5443,portadatain_unconnected_wire_5444,portadatain_unconnected_wire_5445,portadatain_unconnected_wire_5446,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[30] }), .portaaddr({portaaddr_unconnected_wire_5447,portaaddr_unconnected_wire_5448,portaaddr_unconnected_wire_5449,portaaddr_unconnected_wire_5450,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5451,portbaddr_unconnected_wire_5452,portbaddr_unconnected_wire_5453,portbaddr_unconnected_wire_5454, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[30] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30 .first_bit_number = 30; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama30 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[39]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[30] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[39] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[39]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[39]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[39]~I .lut_mask = "33333333CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][39]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[39] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][39] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][39]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist102_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5455,portadatain_unconnected_wire_5456,portadatain_unconnected_wire_5457,portadatain_unconnected_wire_5458,portadatain_unconnected_wire_5459,portadatain_unconnected_wire_5460,portadatain_unconnected_wire_5461, portadatain_unconnected_wire_5462,portadatain_unconnected_wire_5463,portadatain_unconnected_wire_5464,portadatain_unconnected_wire_5465,portadatain_unconnected_wire_5466,portadatain_unconnected_wire_5467,portadatain_unconnected_wire_5468, portadatain_unconnected_wire_5469,portadatain_unconnected_wire_5470,portadatain_unconnected_wire_5471,portadatain_unconnected_wire_5472,portadatain_unconnected_wire_5473,\fp_pow_0002:fp_pow_inst|normProdYLogX_uid98_fpPowrTest_q[29] }), .portaaddr({portaaddr_unconnected_wire_5474,portaaddr_unconnected_wire_5475,portaaddr_unconnected_wire_5476,portaaddr_unconnected_wire_5477,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] ,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5478,portbaddr_unconnected_wire_5479,portbaddr_unconnected_wire_5480,portbaddr_unconnected_wire_5481, \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|dataout_reg[29] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29 .logical_ram_depth = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29 .logical_ram_width = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29 .address_width = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29 .first_bit_number = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29 .last_address = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|lutrama29 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[38]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist98|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist102_replace_mem_dmem|altera_syncram_0eg3:auto_generated|altsyncram_rmb4:altsyncram1|__ALT_INV__dataout_reg[29] ), .combout(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[38] )); defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[38]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[38]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[38]~I .lut_mask = "3C3C3C3C3C3C3C3C"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][38]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|onesCmpFxpInQ2_uid127_fpPowrTest_q_i[38] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][38] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|delay_signals[0][38]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~21_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][38] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~22 )); defparam \fp_pow_0002:fp_pow_inst|Add40~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~21_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~53_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][39] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~54 )); defparam \fp_pow_0002:fp_pow_inst|Add40~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~53_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~37_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][40] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~38 )); defparam \fp_pow_0002:fp_pow_inst|Add40~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~37_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~69_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][41] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~69 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~70 )); defparam \fp_pow_0002:fp_pow_inst|Add40~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~69_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][42] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~70 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~1 ), .cout(\fp_pow_0002:fp_pow_inst|Add40~2 )); defparam \fp_pow_0002:fp_pow_inst|Add40~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~1_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add40~9_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:onesCmpFxpInQ2_uid127_fpPowrTest_delay|__ALT_INV__delay_signals[0][43] ), .cin(\fp_pow_0002:fp_pow_inst|Add40~2 ), .sumout(\fp_pow_0002:fp_pow_inst|Add40~9 )); defparam \fp_pow_0002:fp_pow_inst|Add40~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add40~9_I .lut_mask = "0000FFFF00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][43]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][43] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][43]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][43]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[1][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist19|delay_signals[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[1][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[1][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[1][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[1][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist20|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux203~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][21] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][37] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Mux203~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux203~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux203~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux203~0_I .lut_mask = "2727272700FF00FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[1][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist17|delay_signals[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[1][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[1][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[1][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[1][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist18|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~125 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~57 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux211~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][13] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][29] ), .combout(\fp_pow_0002:fp_pow_inst|Mux211~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux211~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux211~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux211~0_I .lut_mask = "11B111B11BBB1BBB"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~73 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][41]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~69 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][41] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][41]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~121 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~82_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][25] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][41] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][9] ), .combout(\rtl~82 )); defparam \rtl~82_I .shared_arith = "off"; defparam \rtl~82_I .extended_lut = "off"; defparam \rtl~82_I .lut_mask = "050503F3F5F503F3"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~105 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~65 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux207~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][17] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][33] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Mux207~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux207~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux207~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux207~0_I .lut_mask = "2727272700FF00FF"; cyclonev_lcell_comb \rtl~83_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux203~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux211~0 ), .datae(\__ALT_INV__rtl~82 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux207~0 ), .combout(\rtl~83 )); defparam \rtl~83_I .shared_arith = "off"; defparam \rtl~83_I .extended_lut = "off"; defparam \rtl~83_I .lut_mask = "0151A1F10B5BABFB"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[1][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[1][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[1][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[1][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[1][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~97 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][35]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux205~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][19] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][35] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Mux205~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux205~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux205~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux205~0_I .lut_mask = "0C3F0C3F55555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][39]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][39] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][39]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~81 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux201~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][39] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][23] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .combout(\fp_pow_0002:fp_pow_inst|Mux201~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux201~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux201~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux201~0_I .lut_mask = "10B010B01FBF1FBF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~129 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux213~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][11] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][27] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Mux213~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux213~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux213~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux213~0_I .lut_mask = "0C3F0C3F55555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~113 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux209~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][15] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][31] ), .combout(\fp_pow_0002:fp_pow_inst|Mux209~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux209~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux209~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux209~0_I .lut_mask = "0C550C553F553F55"; cyclonev_lcell_comb \rtl~84_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux205~0 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux201~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux213~0 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux209~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~84 )); defparam \rtl~84_I .shared_arith = "off"; defparam \rtl~84_I .extended_lut = "off"; defparam \rtl~84_I .lut_mask = "0F000FFF55335533"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][40]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][40] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][40]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~77 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux200~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][40] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][24] ), .combout(\fp_pow_0002:fp_pow_inst|Mux200~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux200~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux200~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux200~0_I .lut_mask = "02570257A2F7A2F7"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][28]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~137 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux212~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][28] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][12] ), .combout(\fp_pow_0002:fp_pow_inst|Mux212~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux212~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux212~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux212~0_I .lut_mask = "05270527AF27AF27"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~109 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux208~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][16] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][32] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Mux208~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux208~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux208~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux208~0_I .lut_mask = "227722770F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][36]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][36] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][36]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~93 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux204~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][36] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][20] ), .combout(\fp_pow_0002:fp_pow_inst|Mux204~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux204~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux204~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux204~0_I .lut_mask = "03530353F353F353"; cyclonev_lcell_comb \rtl~87_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux200~0 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux212~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux208~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux204~0 ), .combout(\rtl~87 )); defparam \rtl~87_I .shared_arith = "off"; defparam \rtl~87_I .extended_lut = "off"; defparam \rtl~87_I .lut_mask = "01C131F10DCD3DFD"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist15|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist16|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][26]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][42]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][42] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][42]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~133 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~85_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][26] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][42] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][10] ), .combout(\rtl~85 )); defparam \rtl~85_I .shared_arith = "off"; defparam \rtl~85_I .extended_lut = "off"; defparam \rtl~85_I .lut_mask = "000F5533FF0F5533"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][30]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~117 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux210~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][30] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][14] ), .combout(\fp_pow_0002:fp_pow_inst|Mux210~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux210~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux210~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux210~0_I .lut_mask = "111B111BBB1BBB1B"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~101 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux206~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][18] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][34] ), .combout(\fp_pow_0002:fp_pow_inst|Mux206~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux206~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux206~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux206~0_I .lut_mask = "202F202F707F707F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][38]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][38] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][38]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add40~85 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux202~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][38] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][22] ), .combout(\fp_pow_0002:fp_pow_inst|Mux202~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux202~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux202~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux202~0_I .lut_mask = "03530353F353F353"; cyclonev_lcell_comb \rtl~86_I ( .dataa(\__ALT_INV__rtl~85 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux210~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux206~0 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux202~0 ), .combout(\rtl~86 )); defparam \rtl~86_I .shared_arith = "off"; defparam \rtl~86_I .extended_lut = "off"; defparam \rtl~86_I .lut_mask = "55330F0055330FFF"; cyclonev_lcell_comb \rtl~88_I ( .dataa(\__ALT_INV__rtl~83 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datac(\__ALT_INV__rtl~84 ), .datad(\__ALT_INV__rtl~87 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~86 ), .combout(\rtl~88 )); defparam \rtl~88_I .shared_arith = "off"; defparam \rtl~88_I .extended_lut = "off"; defparam \rtl~88_I .lut_mask = "474700334747CCFF"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[9]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~88 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[9] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~177 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~100_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][40] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][24] ), .combout(\rtl~100 )); defparam \rtl~100_I .shared_arith = "off"; defparam \rtl~100_I .extended_lut = "off"; defparam \rtl~100_I .lut_mask = "101510151A1F1A1F"; cyclonev_lcell_comb \rtl~135_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux208~0 ), .datab(\__ALT_INV__rtl~100 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux212~0 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux204~0 ), .combout(\rtl~135 )); defparam \rtl~135_I .shared_arith = "off"; defparam \rtl~135_I .extended_lut = "off"; defparam \rtl~135_I .lut_mask = "353500F035350FFF"; cyclonev_lcell_comb \rtl~139_I ( .dataa(\__ALT_INV__rtl~83 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datac(\__ALT_INV__rtl~84 ), .datad(\__ALT_INV__rtl~86 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~135 ), .combout(\rtl~139 )); defparam \rtl~139_I .shared_arith = "off"; defparam \rtl~139_I .extended_lut = "off"; defparam \rtl~139_I .lut_mask = "00334747CCFF4747"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[8]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~139 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[8] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~173 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~124_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][39] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][23] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .combout(\rtl~124 )); defparam \rtl~124_I .shared_arith = "off"; defparam \rtl~124_I .extended_lut = "off"; defparam \rtl~124_I .lut_mask = "0522052205770577"; cyclonev_lcell_comb \rtl~133_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux205~0 ), .datab(\__ALT_INV__rtl~124 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux213~0 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux209~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~133 )); defparam \rtl~133_I .shared_arith = "off"; defparam \rtl~133_I .extended_lut = "off"; defparam \rtl~133_I .lut_mask = "330F330F0055FF55"; cyclonev_lcell_comb \rtl~138_I ( .dataa(\__ALT_INV__rtl~83 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datac(\__ALT_INV__rtl~133 ), .datad(\__ALT_INV__rtl~135 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~86 ), .combout(\rtl~138 )); defparam \rtl~138_I .shared_arith = "off"; defparam \rtl~138_I .extended_lut = "off"; defparam \rtl~138_I .lut_mask = "1D1D00CC1D1D33FF"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[7]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~138 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[7] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~110_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][38] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][22] ), .combout(\rtl~110 )); defparam \rtl~110_I .shared_arith = "off"; defparam \rtl~110_I .extended_lut = "off"; defparam \rtl~110_I .lut_mask = "0503050305F305F3"; cyclonev_lcell_comb \rtl~131_I ( .dataa(\__ALT_INV__rtl~85 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux206~0 ), .datad(\__ALT_INV__rtl~110 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux210~0 ), .combout(\rtl~131 )); defparam \rtl~131_I .shared_arith = "off"; defparam \rtl~131_I .extended_lut = "off"; defparam \rtl~131_I .lut_mask = "11DD030311DDCFCF"; cyclonev_lcell_comb \rtl~137_I ( .dataa(\__ALT_INV__rtl~83 ), .datab(\__ALT_INV__rtl~135 ), .datac(\__ALT_INV__rtl~133 ), .datad(\__ALT_INV__rtl~131 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .combout(\rtl~137 )); defparam \rtl~137_I .shared_arith = "off"; defparam \rtl~137_I .extended_lut = "off"; defparam \rtl~137_I .lut_mask = "00FF33330F0F5555"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[6]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~137 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[6] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~169 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~165 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~117_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][21] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][37] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~117 )); defparam \rtl~117_I .shared_arith = "off"; defparam \rtl~117_I .extended_lut = "off"; defparam \rtl~117_I .lut_mask = "1111111105AF05AF"; cyclonev_lcell_comb \rtl~129_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux207~0 ), .datab(\__ALT_INV__rtl~117 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux211~0 ), .datae(\__ALT_INV__rtl~82 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~129 )); defparam \rtl~129_I .shared_arith = "off"; defparam \rtl~129_I .extended_lut = "off"; defparam \rtl~129_I .lut_mask = "30303F3F05F505F5"; cyclonev_lcell_comb \rtl~136_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datab(\__ALT_INV__rtl~129 ), .datac(\__ALT_INV__rtl~133 ), .datad(\__ALT_INV__rtl~131 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .dataf(\__ALT_INV__rtl~135 ), .combout(\rtl~136 )); defparam \rtl~136_I .shared_arith = "off"; defparam \rtl~136_I .extended_lut = "off"; defparam \rtl~136_I .lut_mask = "22770A0A22775F5F"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[5]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~136 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[5] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~161 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~103_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][36] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][20] ), .combout(\rtl~103 )); defparam \rtl~103_I .shared_arith = "off"; defparam \rtl~103_I .extended_lut = "off"; defparam \rtl~103_I .lut_mask = "005300530F530F53"; cyclonev_lcell_comb \rtl~127_I ( .dataa(\__ALT_INV__rtl~103 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .datad(\__ALT_INV__rtl~100 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux208~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux212~0 ), .combout(\rtl~127 )); defparam \rtl~127_I .shared_arith = "off"; defparam \rtl~127_I .extended_lut = "off"; defparam \rtl~127_I .lut_mask = "407043734C7C4F7F"; cyclonev_lcell_comb \rtl~134_I ( .dataa(\__ALT_INV__rtl~133 ), .datab(\__ALT_INV__rtl~129 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datae(\__ALT_INV__rtl~131 ), .dataf(\__ALT_INV__rtl~127 ), .combout(\rtl~134 )); defparam \rtl~134_I .shared_arith = "off"; defparam \rtl~134_I .extended_lut = "off"; defparam \rtl~134_I .lut_mask = "00350F35F035FF35"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[4]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~134 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[4] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~121_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][35] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][19] ), .combout(\rtl~121 )); defparam \rtl~121_I .shared_arith = "off"; defparam \rtl~121_I .extended_lut = "off"; defparam \rtl~121_I .lut_mask = "001D001D331D331D"; cyclonev_lcell_comb \rtl~125_I ( .dataa(\__ALT_INV__rtl~121 ), .datab(\__ALT_INV__rtl~124 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux213~0 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux209~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~125 )); defparam \rtl~125_I .shared_arith = "off"; defparam \rtl~125_I .extended_lut = "off"; defparam \rtl~125_I .lut_mask = "553355330F000FFF"; cyclonev_lcell_comb \rtl~132_I ( .dataa(\__ALT_INV__rtl~131 ), .datab(\__ALT_INV__rtl~125 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datad(\__ALT_INV__rtl~129 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~127 ), .combout(\rtl~132 )); defparam \rtl~132_I .shared_arith = "off"; defparam \rtl~132_I .extended_lut = "off"; defparam \rtl~132_I .lut_mask = "303F0505303FF5F5"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[3]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~132 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[3] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~157 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~107_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][18] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][34] ), .combout(\rtl~107 )); defparam \rtl~107_I .shared_arith = "off"; defparam \rtl~107_I .extended_lut = "off"; defparam \rtl~107_I .lut_mask = "1105110511AF11AF"; cyclonev_lcell_comb \rtl~111_I ( .dataa(\__ALT_INV__rtl~85 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux210~0 ), .datac(\__ALT_INV__rtl~107 ), .datad(\__ALT_INV__rtl~110 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .combout(\rtl~111 )); defparam \rtl~111_I .shared_arith = "off"; defparam \rtl~111_I .extended_lut = "off"; defparam \rtl~111_I .lut_mask = "0F0F555500FF3333"; cyclonev_lcell_comb \rtl~130_I ( .dataa(\__ALT_INV__rtl~111 ), .datab(\__ALT_INV__rtl~125 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datad(\__ALT_INV__rtl~129 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~127 ), .combout(\rtl~130 )); defparam \rtl~130_I .shared_arith = "off"; defparam \rtl~130_I .extended_lut = "off"; defparam \rtl~130_I .lut_mask = "5050303F5F5F303F"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[2]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~130 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[2] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~153 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~149 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~114_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][17] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][33] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~114 )); defparam \rtl~114_I .shared_arith = "off"; defparam \rtl~114_I .extended_lut = "off"; defparam \rtl~114_I .lut_mask = "111111110A5F0A5F"; cyclonev_lcell_comb \rtl~118_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .datab(\__ALT_INV__rtl~82 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux211~0 ), .datae(\__ALT_INV__rtl~114 ), .dataf(\__ALT_INV__rtl~117 ), .combout(\rtl~118 )); defparam \rtl~118_I .shared_arith = "off"; defparam \rtl~118_I .extended_lut = "off"; defparam \rtl~118_I .lut_mask = "1015B0B51A1FBABF"; cyclonev_lcell_comb \rtl~128_I ( .dataa(\__ALT_INV__rtl~111 ), .datab(\__ALT_INV__rtl~125 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datad(\__ALT_INV__rtl~118 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~127 ), .combout(\rtl~128 )); defparam \rtl~128_I .shared_arith = "off"; defparam \rtl~128_I .extended_lut = "off"; defparam \rtl~128_I .lut_mask = "03F3505003F35F5F"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[1]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~128 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[1] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~145 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~97_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][16] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][32] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~97 )); defparam \rtl~97_I .shared_arith = "off"; defparam \rtl~97_I .extended_lut = "off"; defparam \rtl~97_I .lut_mask = "111111110A5F0A5F"; cyclonev_lcell_comb \rtl~104_I ( .dataa(\__ALT_INV__rtl~103 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .datad(\__ALT_INV__rtl~100 ), .datae(\__ALT_INV__rtl~97 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux212~0 ), .combout(\rtl~104 )); defparam \rtl~104_I .shared_arith = "off"; defparam \rtl~104_I .extended_lut = "off"; defparam \rtl~104_I .lut_mask = "101CD0DC131FD3DF"; cyclonev_lcell_comb \rtl~126_I ( .dataa(\__ALT_INV__rtl~111 ), .datab(\__ALT_INV__rtl~125 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datad(\__ALT_INV__rtl~118 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~104 ), .combout(\rtl~126 )); defparam \rtl~126_I .shared_arith = "off"; defparam \rtl~126_I .extended_lut = "off"; defparam \rtl~126_I .lut_mask = "050503F3F5F503F3"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~126 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[0] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|Add38~181 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~186_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][0] ), .cin(gnd), .cout(\fp_pow_0002:fp_pow_inst|Add41~186 )); defparam \fp_pow_0002:fp_pow_inst|Add41~186_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~186_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~186_I .lut_mask = "000000000000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~149_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[0] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~186 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~149 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~150 )); defparam \fp_pow_0002:fp_pow_inst|Add41~149_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~149_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~149_I .lut_mask = "00000F0F000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~153_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[1] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~150 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~153 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~154 )); defparam \fp_pow_0002:fp_pow_inst|Add41~153_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~153_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~153_I .lut_mask = "00000F0F000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~157_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[2] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][3] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~154 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~157 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~158 )); defparam \fp_pow_0002:fp_pow_inst|Add41~157_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~157_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~157_I .lut_mask = "0000AAAA0000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~161_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][4] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~158 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~161 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~162 )); defparam \fp_pow_0002:fp_pow_inst|Add41~161_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~161_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~161_I .lut_mask = "0000F0F00000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~165_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[4] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~162 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~165 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~166 )); defparam \fp_pow_0002:fp_pow_inst|Add41~165_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~165_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~165_I .lut_mask = "0000F0F00000CCCC"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~169_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][6] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[5] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~166 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~169 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~170 )); defparam \fp_pow_0002:fp_pow_inst|Add41~169_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~169_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~169_I .lut_mask = "0000F0F00000CCCC"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~173_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[6] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~170 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~173 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~174 )); defparam \fp_pow_0002:fp_pow_inst|Add41~173_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~173_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~173_I .lut_mask = "0000F0F00000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~177_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][8] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[7] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~174 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~177 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~178 )); defparam \fp_pow_0002:fp_pow_inst|Add41~177_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~177_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~177_I .lut_mask = "00003333000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~181_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][9] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[8] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~178 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~181 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~182 )); defparam \fp_pow_0002:fp_pow_inst|Add41~181_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~181_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~181_I .lut_mask = "00005555000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~129_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][10] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[9] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~182 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~129 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~130 )); defparam \fp_pow_0002:fp_pow_inst|Add41~129_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~129_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~129_I .lut_mask = "0000F0F00000CCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~129 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[43]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|delay_signals[0][43] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[43] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[43]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[43]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[47]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .combout(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[47]~feeder )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[47]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[47]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[47]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[47]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[47]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[47] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[47]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[47]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~9_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~9 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~9_I .lut_mask = "03030303333F3F3F"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[46]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[46] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[46]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[46]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~11_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~11 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~11_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~11_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~11_I .lut_mask = "6639663967196719"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[45]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~11 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[45] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[45]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[45]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~13_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~13 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~13_I .lut_mask = "033F3F3CC0C3C303"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[44]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[44] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[44]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[44]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~15_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~15 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~15_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~15_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~15_I .lut_mask = "50A50F5A0F50F50F"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[43]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~15 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[43] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[43]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[43]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~17_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~17 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~17_I .lut_mask = "65A565A5A71AA71A"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[42]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[42] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[42]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~6_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~6 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~6_I .lut_mask = "5555555555575557"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][42]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~6 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][42] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][42]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~7_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~36 ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~7 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~7_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~7_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~7_I .lut_mask = "1A1A1A1A10101010"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][41]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~7 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][41] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][41]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~19_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~19 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~19_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~19_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~19_I .lut_mask = "3FC03FC002BF02BF"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[41]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~19 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[41] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[41]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~21_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~21 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~21_I .lut_mask = "3C3C3C3CC69CC69C"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[40]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[40] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[40]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~8_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~8 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~8_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~8_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~8_I .lut_mask = "30340D0D3C3CCFCB"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][40]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~8 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][40] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][40]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~33_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~33 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~33_I .lut_mask = "0C3338F3C71CCC38"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][39]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][39] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][39]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~23_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~23 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~23_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~23_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~23_I .lut_mask = "05FA05FA1FA01FA0"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[39]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~23 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[39] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[39]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~11_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~11 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~11_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~11_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~11_I .lut_mask = "63693C9C86C36379"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][38]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~11 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][38] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][38]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~31_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~31 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~31_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~31_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~31_I .lut_mask = "5A55A25A45AA5A65"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~31 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][37] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][37]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~24_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~24 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~24_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~24_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~24_I .lut_mask = "033333FCCC33C033"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~24 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[37] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[37]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~7_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~7 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~7_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~7_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~7_I .lut_mask = "34B234B24B4D4B4D"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[36]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~7 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[36] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[36]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~5 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~5_I .lut_mask = "55ABBD020AD550AF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][36]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][36] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][36]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~43_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~43 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~43_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~43_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~43_I .lut_mask = "1176C833EE8137CC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~43 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][35]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~6_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~6 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~6_I .lut_mask = "300FF33CF00FC330"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~6 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[35] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[35]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~5 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~5_I .lut_mask = "6AAA6AAA15571557"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[34] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~4_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~4 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~4_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~4_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~4_I .lut_mask = "269AD94526B2DB4D"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~4 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~44_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~44 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~44_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~44_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~44_I .lut_mask = "656969795A9E5A96"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~44 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~4_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~4 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~4_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~4_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~4_I .lut_mask = "6CC96CC96C6C6C6C"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~4 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[33] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~3_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~3 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~3_I .lut_mask = "15A515A5AA5AAA5A"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~3 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[32] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~3_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~3 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~3_I .lut_mask = "1939CCCC73673933"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~3 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~2 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~2_I .lut_mask = "65556555AAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[31] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~2_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~2 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~2_I .lut_mask = "2A4A54F5BDAB4A50"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~1_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~1 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~1_I .lut_mask = "00F00000FF0FFFFF"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[30] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~1 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~1_I .lut_mask = "2D52B46BA54AD62D"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~0 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~0_I .lut_mask = "66C61931CC9C7367"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~0_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~0 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~0_I .lut_mask = "0F000F00F0FFF0FF"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[29] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~42_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~42 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~42_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~42_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~42_I .lut_mask = "402FBF40F4030FF4"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~42 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~8_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~8 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~8_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~8_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~8_I .lut_mask = "0F0FF0F00F0FF0F0"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~8 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[28] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~10_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~10 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~10_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~10_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~10_I .lut_mask = "0505555F0555555F"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~10 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[27] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~41_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~41 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~41_I .lut_mask = "4BB4D23C0FF0C334"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~12_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~12 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~12_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~12_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~12_I .lut_mask = "6369636963396339"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~12 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[26] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~40_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~40 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~40_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~40_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~40_I .lut_mask = "6666998C3333CCC6"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~40 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~14_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~14 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~14_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~14_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~14_I .lut_mask = "15A515A55AA55AA5"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~14 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[25] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~39_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~39 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~39_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~39_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~39_I .lut_mask = "00FFFF0001EAFA15"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~39 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~16_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~16 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~16_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~16_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~16_I .lut_mask = "4F304F3000FF00FF"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~16 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[24] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~38_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~38 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~38_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~38_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~38_I .lut_mask = "00FF07E800FF17E0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~38 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~18_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~18 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~18_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~18_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~18_I .lut_mask = "43C343C3F0F0F0F0"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~18 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[23] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~37_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~37 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~37_I .lut_mask = "1137EEC81337EC88"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~20_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~20 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~20_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~20_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~20_I .lut_mask = "7F7F7F7F00000000"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~20 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|delay_signals[0][10] ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[22] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~35_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~35 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~35_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~35_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~35_I .lut_mask = "5959596969656D65"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~35 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~22_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~22 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~22_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~22_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~22_I .lut_mask = "4CCC4CCCCCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~22 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[21] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~34_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~34 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~34_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~34_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~34_I .lut_mask = "343C3C0F0FC34BC3"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~34 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~32_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~32 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~32_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~32_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~32_I .lut_mask = "193333CCCC339933"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~32 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~12_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~12 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~12_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~12_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~12_I .lut_mask = "CCCCCCCC00000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~14_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~12 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~13 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~14 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~14_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~14_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~14_I .lut_mask = "CDDE0112EDED2121"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~14 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~25_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~25 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~25_I .lut_mask = "6CCC6CCCCCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[18] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~16_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~15 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~12 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~16 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~16_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~16_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~16_I .lut_mask = "CC05CCA5CCA5CCA5"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|Ram7~16 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~26_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~26 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~26_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~26_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~26_I .lut_mask = "1AAA1AAAAAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~26 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[17] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~17_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~12 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~17 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~17_I .lut_mask = "AA2AAA2AAAAAAAAA"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~23_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~12 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~23 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~23_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~23_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~23_I .lut_mask = "F700F700FF00FF00"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~23 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram8~28_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][9] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][10] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][7] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][8] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|Ram8~28 )); defparam \fp_pow_0002:fp_pow_inst|Ram8~28_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~28_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram8~28_I .lut_mask = "4F304F30FF00FF00"; dffeas \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram8~28 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[16] )); defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|p1_uid385_eRndXlog2_uid125_fpPowrTest_q[16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~22_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~12 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~22 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~22_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~22_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~22_I .lut_mask = "F7FFF7FFFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~22 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~21_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~18 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~36 ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~21 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~21_I .lut_mask = "FF77FF77EE66EE66"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Ram7~20_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][4] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist95|__ALT_INV__delay_signals[0][5] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~18 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Ram7~36 ), .combout(\fp_pow_0002:fp_pow_inst|Ram7~20 )); defparam \fp_pow_0002:fp_pow_inst|Ram7~20_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~20_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Ram7~20_I .lut_mask = "C4C4C4C4D5D5D5D5"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Ram7~20 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist39|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~129_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[21] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][13] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~126 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~129 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~130 )); defparam \fp_pow_0002:fp_pow_inst|Add38~129_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~129_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~129_I .lut_mask = "0000FF0000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~133_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[22] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][14] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~130 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~133 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~134 )); defparam \fp_pow_0002:fp_pow_inst|Add38~133_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~133_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~133_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~137_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[23] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][15] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~134 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~137 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~138 )); defparam \fp_pow_0002:fp_pow_inst|Add38~137_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~137_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~137_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~141_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][16] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[16] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~138 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~141 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~142 )); defparam \fp_pow_0002:fp_pow_inst|Add38~141_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~141_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~141_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~121_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[17] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][17] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~142 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~121 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~122 )); defparam \fp_pow_0002:fp_pow_inst|Add38~121_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~121_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~121_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~117_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[18] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][18] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~122 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~117 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~118 )); defparam \fp_pow_0002:fp_pow_inst|Add38~117_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~117_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~117_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~109_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[21] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][19] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~118 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~109 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~110 )); defparam \fp_pow_0002:fp_pow_inst|Add38~109_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~109_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~109_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~101_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[21] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][20] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~110 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~101 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~102 )); defparam \fp_pow_0002:fp_pow_inst|Add38~101_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~101_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~101_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~93_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[21] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][21] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~102 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~93 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~94 )); defparam \fp_pow_0002:fp_pow_inst|Add38~93_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~93_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~93_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~85_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[22] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][22] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~94 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~85 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~86 )); defparam \fp_pow_0002:fp_pow_inst|Add38~85_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~85_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~85_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~77_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[23] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][23] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~86 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~78 )); defparam \fp_pow_0002:fp_pow_inst|Add38~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~77_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~69_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[24] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~69 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~70 )); defparam \fp_pow_0002:fp_pow_inst|Add38~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~69_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~61_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[25] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][25] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~70 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~62 )); defparam \fp_pow_0002:fp_pow_inst|Add38~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~61_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~53_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[26] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][26] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~54 )); defparam \fp_pow_0002:fp_pow_inst|Add38~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~53_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~45_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[27] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][27] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~46 )); defparam \fp_pow_0002:fp_pow_inst|Add38~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~45_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~37_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][28] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[28] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~38 )); defparam \fp_pow_0002:fp_pow_inst|Add38~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~37_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][29] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[29] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~1 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~2 )); defparam \fp_pow_0002:fp_pow_inst|Add38~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~1_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~9_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[30] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][30] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~2 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~10 )); defparam \fp_pow_0002:fp_pow_inst|Add38~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~9_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~13_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[31] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][31] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~14 )); defparam \fp_pow_0002:fp_pow_inst|Add38~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~13_I .lut_mask = "0000FF0000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~17_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[32] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][32] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~18 )); defparam \fp_pow_0002:fp_pow_inst|Add38~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~17_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~21_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][33] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[33] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~22 )); defparam \fp_pow_0002:fp_pow_inst|Add38~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~21_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~25_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[34] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][34] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~26 )); defparam \fp_pow_0002:fp_pow_inst|Add38~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~25_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~29_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][35] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[35] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~30 )); defparam \fp_pow_0002:fp_pow_inst|Add38~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~29_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~33_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[36] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][36] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~34 )); defparam \fp_pow_0002:fp_pow_inst|Add38~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~33_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~113_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][37] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[37] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~113 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~114 )); defparam \fp_pow_0002:fp_pow_inst|Add38~113_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~113_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~113_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~105_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[45] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][38] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~114 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~105 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~106 )); defparam \fp_pow_0002:fp_pow_inst|Add38~105_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~105_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~105_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~97_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][39] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[39] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~106 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~97 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~98 )); defparam \fp_pow_0002:fp_pow_inst|Add38~97_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~97_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~97_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~89_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[40] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][40] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~98 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~89 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~90 )); defparam \fp_pow_0002:fp_pow_inst|Add38~89_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~89_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~89_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~81_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][41] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[41] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~90 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~81 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~82 )); defparam \fp_pow_0002:fp_pow_inst|Add38~81_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~81_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~81_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~73_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[42] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist39|__ALT_INV__delay_signals[0][42] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~82 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~73 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~74 )); defparam \fp_pow_0002:fp_pow_inst|Add38~73_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~73_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~73_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~65_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[43] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~74 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~65 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~66 )); defparam \fp_pow_0002:fp_pow_inst|Add38~65_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~65_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~65_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~57_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[44] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~66 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~57 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~58 )); defparam \fp_pow_0002:fp_pow_inst|Add38~57_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~57_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~57_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~49_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[45] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~58 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~50 )); defparam \fp_pow_0002:fp_pow_inst|Add38~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~49_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~41_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[46] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add38~42 )); defparam \fp_pow_0002:fp_pow_inst|Add38~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~41_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add38~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__p1_uid385_eRndXlog2_uid125_fpPowrTest_q[47] ), .cin(\fp_pow_0002:fp_pow_inst|Add38~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add38~5 )); defparam \fp_pow_0002:fp_pow_inst|Add38~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add38~5_I .lut_mask = "0000FFFF00005555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][45]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][45] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][45]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][45]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][44]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][44] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][44]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][44]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][43]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][43] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][43]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][43]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~277_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~277 )); defparam \rtl~277_I .shared_arith = "off"; defparam \rtl~277_I .extended_lut = "off"; defparam \rtl~277_I .lut_mask = "AA00AA0000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux228~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~277 ), .combout(\fp_pow_0002:fp_pow_inst|Mux228~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux228~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux228~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux228~0_I .lut_mask = "00000000AAAAAAAA"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux268~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][42] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux228~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux268~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux268~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux268~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux268~0_I .lut_mask = "3333333313B313B3"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[42]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Mux268~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[42] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[42]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~283_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][41] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][42] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux228~0 ), .combout(\rtl~283 )); defparam \rtl~283_I .shared_arith = "off"; defparam \rtl~283_I .extended_lut = "off"; defparam \rtl~283_I .lut_mask = "00FF00FF404F707F"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[41]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~283 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[41] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[41]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][42]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~57 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][42] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][42]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][42]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux227~0_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][40] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux228~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux227~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux227~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux227~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux227~0_I .lut_mask = "333333330F0F0F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux225~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux228~0 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][42] ), .combout(\fp_pow_0002:fp_pow_inst|Mux225~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux225~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux225~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux225~0_I .lut_mask = "2222222277777777"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux226~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux228~0 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][41] ), .combout(\fp_pow_0002:fp_pow_inst|Mux226~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux226~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux226~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux226~0_I .lut_mask = "2727272727272727"; cyclonev_lcell_comb \rtl~57_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux227~0 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux225~0 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux226~0 ), .combout(\rtl~57 )); defparam \rtl~57_I .shared_arith = "off"; defparam \rtl~57_I .extended_lut = "off"; defparam \rtl~57_I .lut_mask = "505F0303505FF3F3"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[40]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~57 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[40] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[40]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][41]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~65 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][41] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][41]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][41]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux228~1_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][39] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux228~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux228~1 )); defparam \fp_pow_0002:fp_pow_inst|Mux228~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux228~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux228~1_I .lut_mask = "333333330F0F0F0F"; cyclonev_lcell_comb \rtl~60_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux227~0 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux226~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux228~1 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux225~0 ), .combout(\rtl~60 )); defparam \rtl~60_I .shared_arith = "off"; defparam \rtl~60_I .extended_lut = "off"; defparam \rtl~60_I .lut_mask = "101CD0DC131FD3DF"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[39]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~60 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[39] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[39]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][40]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~73 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][40] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][40]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][39]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~81 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][39] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][39]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~284_I ( .dataa(\__ALT_INV__rtl~277 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][42] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][38] ), .combout(\rtl~284 )); defparam \rtl~284_I .shared_arith = "off"; defparam \rtl~284_I .extended_lut = "off"; defparam \rtl~284_I .lut_mask = "2227222777277727"; cyclonev_lcell_comb \rtl~65_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux227~0 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux226~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux228~1 ), .dataf(\__ALT_INV__rtl~284 ), .combout(\rtl~65 )); defparam \rtl~65_I .shared_arith = "off"; defparam \rtl~65_I .extended_lut = "off"; defparam \rtl~65_I .lut_mask = "050305F3F503F5F3"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[38]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~65 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[38] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[38]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][38]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~89 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][38] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][38]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~285_I ( .dataa(\__ALT_INV__rtl~277 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][37] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][41] ), .combout(\rtl~285 )); defparam \rtl~285_I .shared_arith = "off"; defparam \rtl~285_I .extended_lut = "off"; defparam \rtl~285_I .lut_mask = "2272227227772777"; cyclonev_lcell_comb \rtl~70_I ( .dataa(\__ALT_INV__rtl~284 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux227~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux228~1 ), .dataf(\__ALT_INV__rtl~285 ), .combout(\rtl~70 )); defparam \rtl~70_I .shared_arith = "off"; defparam \rtl~70_I .extended_lut = "off"; defparam \rtl~70_I .lut_mask = "10131C1FD0D3DCDF"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[37]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~70 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[37] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[37]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~97 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][37] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][37]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~279_I ( .dataa(\__ALT_INV__rtl~277 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][36] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][40] ), .combout(\rtl~279 )); defparam \rtl~279_I .shared_arith = "off"; defparam \rtl~279_I .extended_lut = "off"; defparam \rtl~279_I .lut_mask = "05AF00AA05AF55FF"; cyclonev_lcell_comb \rtl~73_I ( .dataa(\__ALT_INV__rtl~284 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux228~1 ), .datad(\__ALT_INV__rtl~279 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~285 ), .combout(\rtl~73 )); defparam \rtl~73_I .shared_arith = "off"; defparam \rtl~73_I .extended_lut = "off"; defparam \rtl~73_I .lut_mask = "11DD030311DDCFCF"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[36]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~73 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[36] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[36]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][36]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~105 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][36] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][36]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~278_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][35] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][39] ), .dataf(\__ALT_INV__rtl~277 ), .combout(\rtl~278 )); defparam \rtl~278_I .shared_arith = "off"; defparam \rtl~278_I .extended_lut = "off"; defparam \rtl~278_I .lut_mask = "5555555500CC33FF"; cyclonev_lcell_comb \rtl~76_I ( .dataa(\__ALT_INV__rtl~285 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datac(\__ALT_INV__rtl~284 ), .datad(\__ALT_INV__rtl~278 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~279 ), .combout(\rtl~76 )); defparam \rtl~76_I .shared_arith = "off"; defparam \rtl~76_I .extended_lut = "off"; defparam \rtl~76_I .lut_mask = "11DD030311DDCFCF"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[35]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~76 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[35] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[35]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~113 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][35]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux186~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][38] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .combout(\fp_pow_0002:fp_pow_inst|Mux186~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux186~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux186~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux186~0_I .lut_mask = "087F087F087F087F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux190~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][34] ), .combout(\fp_pow_0002:fp_pow_inst|Mux190~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux190~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux190~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux190~0_I .lut_mask = "005F005FA0FFA0FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux182~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][42] ), .combout(\fp_pow_0002:fp_pow_inst|Mux182~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux182~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux182~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux182~0_I .lut_mask = "13131313B3B3B3B3"; cyclonev_lcell_comb \rtl~23_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux186~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux190~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux182~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~23 )); defparam \rtl~23_I .shared_arith = "off"; defparam \rtl~23_I .extended_lut = "off"; defparam \rtl~23_I .lut_mask = "05AF05AF1111BBBB"; cyclonev_lcell_comb \rtl~79_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datab(\__ALT_INV__rtl~279 ), .datac(\__ALT_INV__rtl~285 ), .datad(\__ALT_INV__rtl~278 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .dataf(\__ALT_INV__rtl~23 ), .combout(\rtl~79 )); defparam \rtl~79_I .shared_arith = "off"; defparam \rtl~79_I .extended_lut = "off"; defparam \rtl~79_I .lut_mask = "00552727AAFF2727"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[34]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~79 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[34] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux187~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][37] ), .combout(\fp_pow_0002:fp_pow_inst|Mux187~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux187~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux187~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux187~0_I .lut_mask = "15151515D5D5D5D5"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux191~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][33] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Mux191~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux191~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux191~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux191~0_I .lut_mask = "1B1B1B1B33333333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux183~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][41] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Mux183~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux183~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux183~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux183~0_I .lut_mask = "1B1B1B1B33333333"; cyclonev_lcell_comb \rtl~21_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux187~0 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux191~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux183~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~21 )); defparam \rtl~21_I .shared_arith = "off"; defparam \rtl~21_I .extended_lut = "off"; defparam \rtl~21_I .lut_mask = "33553355000FFF0F"; cyclonev_lcell_comb \rtl~31_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datab(\__ALT_INV__rtl~279 ), .datac(\__ALT_INV__rtl~21 ), .datad(\__ALT_INV__rtl~278 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .dataf(\__ALT_INV__rtl~23 ), .combout(\rtl~31 )); defparam \rtl~31_I .shared_arith = "off"; defparam \rtl~31_I .extended_lut = "off"; defparam \rtl~31_I .lut_mask = "0A0A11BB5F5F11BB"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[33]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~31 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[33] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[33]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux184~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][40] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Mux184~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux184~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux184~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux184~0_I .lut_mask = "0A5F0A5F00FF00FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux188~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][36] ), .combout(\fp_pow_0002:fp_pow_inst|Mux188~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux188~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux188~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux188~0_I .lut_mask = "11331133BB33BB33"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux192~0_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][32] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Mux192~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux192~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux192~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux192~0_I .lut_mask = "0F330F3333333333"; cyclonev_lcell_comb \rtl~19_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux184~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux188~0 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux192~0 ), .combout(\rtl~19 )); defparam \rtl~19_I .shared_arith = "off"; defparam \rtl~19_I .extended_lut = "off"; defparam \rtl~19_I .lut_mask = "030305F5F3F305F5"; cyclonev_lcell_comb \rtl~28_I ( .dataa(\__ALT_INV__rtl~23 ), .datab(\__ALT_INV__rtl~278 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datad(\__ALT_INV__rtl~21 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .dataf(\__ALT_INV__rtl~19 ), .combout(\rtl~28 )); defparam \rtl~28_I .shared_arith = "off"; defparam \rtl~28_I .extended_lut = "off"; defparam \rtl~28_I .lut_mask = "000F5353F0FF5353"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[32]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~28 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[32] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[32]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][33]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux185~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][39] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Mux185~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux185~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux185~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux185~0_I .lut_mask = "11DD11DD55555555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux189~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][35] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Mux189~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux189~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux189~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux189~0_I .lut_mask = "05F505F555555555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux193~0_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][31] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Mux193~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux193~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux193~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux193~0_I .lut_mask = "330F330F0F0F0F0F"; cyclonev_lcell_comb \rtl~17_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux185~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux189~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux193~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~17 )); defparam \rtl~17_I .shared_arith = "off"; defparam \rtl~17_I .extended_lut = "off"; defparam \rtl~17_I .lut_mask = "0033CCFF1D1D1D1D"; cyclonev_lcell_comb \rtl~24_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datab(\__ALT_INV__rtl~21 ), .datac(\__ALT_INV__rtl~23 ), .datad(\__ALT_INV__rtl~17 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .dataf(\__ALT_INV__rtl~19 ), .combout(\rtl~24 )); defparam \rtl~24_I .shared_arith = "off"; defparam \rtl~24_I .extended_lut = "off"; defparam \rtl~24_I .lut_mask = "00AA272755FF2727"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[31]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~24 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[31] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux194~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][30] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Mux194~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux194~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux194~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux194~0_I .lut_mask = "11BB11BB33333333"; cyclonev_lcell_comb \rtl~15_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux194~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux186~0 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux182~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux190~0 ), .combout(\rtl~15 )); defparam \rtl~15_I .shared_arith = "off"; defparam \rtl~15_I .extended_lut = "off"; defparam \rtl~15_I .lut_mask = "2700275527AA27FF"; cyclonev_lcell_comb \rtl~22_I ( .dataa(\__ALT_INV__rtl~21 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datac(\__ALT_INV__rtl~17 ), .datad(\__ALT_INV__rtl~15 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~19 ), .combout(\rtl~22 )); defparam \rtl~22_I .shared_arith = "off"; defparam \rtl~22_I .extended_lut = "off"; defparam \rtl~22_I .lut_mask = "00CC1D1D33FF1D1D"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[30]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~22 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[30] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[30]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][31]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux195~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][29] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Mux195~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux195~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux195~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux195~0_I .lut_mask = "1D1D1D1D55555555"; cyclonev_lcell_comb \rtl~13_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux195~0 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux191~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux187~0 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux183~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~13 )); defparam \rtl~13_I .shared_arith = "off"; defparam \rtl~13_I .extended_lut = "off"; defparam \rtl~13_I .lut_mask = "553355330F000FFF"; cyclonev_lcell_comb \rtl~20_I ( .dataa(\__ALT_INV__rtl~13 ), .datab(\__ALT_INV__rtl~19 ), .datac(\__ALT_INV__rtl~17 ), .datad(\__ALT_INV__rtl~15 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .combout(\rtl~20 )); defparam \rtl~20_I .shared_arith = "off"; defparam \rtl~20_I .extended_lut = "off"; defparam \rtl~20_I .lut_mask = "55550F0F00FF3333"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[29]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~20 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[29] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux196~0_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][28] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Mux196~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux196~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux196~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux196~0_I .lut_mask = "303F303F00FF00FF"; cyclonev_lcell_comb \rtl~11_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux184~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux192~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux188~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux196~0 ), .combout(\rtl~11 )); defparam \rtl~11_I .shared_arith = "off"; defparam \rtl~11_I .extended_lut = "off"; defparam \rtl~11_I .lut_mask = "01510B5BA1F1ABFB"; cyclonev_lcell_comb \rtl~18_I ( .dataa(\__ALT_INV__rtl~13 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datac(\__ALT_INV__rtl~17 ), .datad(\__ALT_INV__rtl~15 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~11 ), .combout(\rtl~18 )); defparam \rtl~18_I .shared_arith = "off"; defparam \rtl~18_I .extended_lut = "off"; defparam \rtl~18_I .lut_mask = "00334747CCFF4747"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[28]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~18 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[28] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[28]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][29]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux197~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][27] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|Mux197~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux197~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux197~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux197~0_I .lut_mask = "1D1D1D1D55555555"; cyclonev_lcell_comb \rtl~12_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux185~0 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux197~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux189~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux193~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~12 )); defparam \rtl~12_I .shared_arith = "off"; defparam \rtl~12_I .extended_lut = "off"; defparam \rtl~12_I .lut_mask = "0C0C3F3F11DD11DD"; cyclonev_lcell_comb \rtl~16_I ( .dataa(\__ALT_INV__rtl~13 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datac(\__ALT_INV__rtl~12 ), .datad(\__ALT_INV__rtl~15 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~11 ), .combout(\rtl~16 )); defparam \rtl~16_I .shared_arith = "off"; defparam \rtl~16_I .extended_lut = "off"; defparam \rtl~16_I .lut_mask = "1D1D00331D1DCCFF"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[27]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~16 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[27] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[27]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux198~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][42] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][26] ), .combout(\fp_pow_0002:fp_pow_inst|Mux198~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux198~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux198~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux198~0_I .lut_mask = "043704378CBF8CBF"; cyclonev_lcell_comb \rtl~10_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux186~0 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux194~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux190~0 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux198~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~10 )); defparam \rtl~10_I .shared_arith = "off"; defparam \rtl~10_I .extended_lut = "off"; defparam \rtl~10_I .lut_mask = "0033FF330F550F55"; cyclonev_lcell_comb \rtl~14_I ( .dataa(\__ALT_INV__rtl~13 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datac(\__ALT_INV__rtl~12 ), .datad(\__ALT_INV__rtl~11 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~10 ), .combout(\rtl~14 )); defparam \rtl~14_I .shared_arith = "off"; defparam \rtl~14_I .extended_lut = "off"; defparam \rtl~14_I .lut_mask = "00331D1DCCFF1D1D"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[26]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~14 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[26] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[26]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux199~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][41] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist20|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist94|__ALT_INV__delay_signals[0][25] ), .combout(\fp_pow_0002:fp_pow_inst|Mux199~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux199~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux199~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux199~0_I .lut_mask = "111B111BBB1BBB1B"; cyclonev_lcell_comb \rtl~41_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux187~0 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux191~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux199~0 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux195~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~41 )); defparam \rtl~41_I .shared_arith = "off"; defparam \rtl~41_I .extended_lut = "off"; defparam \rtl~41_I .lut_mask = "0F000FFF33553355"; cyclonev_lcell_comb \rtl~42_I ( .dataa(\__ALT_INV__rtl~10 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datac(\__ALT_INV__rtl~12 ), .datad(\__ALT_INV__rtl~41 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~11 ), .combout(\rtl~42 )); defparam \rtl~42_I .shared_arith = "off"; defparam \rtl~42_I .extended_lut = "off"; defparam \rtl~42_I .lut_mask = "03CF444403CF7777"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[25]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~42 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[25] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~43_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux188~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux200~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux196~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux192~0 ), .combout(\rtl~43 )); defparam \rtl~43_I .shared_arith = "off"; defparam \rtl~43_I .extended_lut = "off"; defparam \rtl~43_I .lut_mask = "01A10BAB51F15BFB"; cyclonev_lcell_comb \rtl~44_I ( .dataa(\__ALT_INV__rtl~10 ), .datab(\__ALT_INV__rtl~12 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datad(\__ALT_INV__rtl~43 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .dataf(\__ALT_INV__rtl~41 ), .combout(\rtl~44 )); defparam \rtl~44_I .shared_arith = "off"; defparam \rtl~44_I .extended_lut = "off"; defparam \rtl~44_I .lut_mask = "00F053530FFF5353"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[24]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~44 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[24] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~45_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux193~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux197~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux189~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux201~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .combout(\rtl~45 )); defparam \rtl~45_I .shared_arith = "off"; defparam \rtl~45_I .extended_lut = "off"; defparam \rtl~45_I .lut_mask = "1111BBBB0A5F0A5F"; cyclonev_lcell_comb \rtl~46_I ( .dataa(\__ALT_INV__rtl~45 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datac(\__ALT_INV__rtl~10 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datae(\__ALT_INV__rtl~43 ), .dataf(\__ALT_INV__rtl~41 ), .combout(\rtl~46 )); defparam \rtl~46_I .shared_arith = "off"; defparam \rtl~46_I .extended_lut = "off"; defparam \rtl~46_I .lut_mask = "440344CF770377CF"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[23]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~46 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[23] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[23]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~50_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux194~0 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux202~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux198~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux190~0 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~50 )); defparam \rtl~50_I .shared_arith = "off"; defparam \rtl~50_I .extended_lut = "off"; defparam \rtl~50_I .lut_mask = "33330F0F555500FF"; cyclonev_lcell_comb \rtl~51_I ( .dataa(\__ALT_INV__rtl~45 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datad(\__ALT_INV__rtl~50 ), .datae(\__ALT_INV__rtl~43 ), .dataf(\__ALT_INV__rtl~41 ), .combout(\rtl~51 )); defparam \rtl~51_I .shared_arith = "off"; defparam \rtl~51_I .extended_lut = "off"; defparam \rtl~51_I .lut_mask = "04C434F407C737F7"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[22]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~51 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[22] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~61 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][23]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~69 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~55_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux199~0 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux191~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux195~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux203~0 ), .combout(\rtl~55 )); defparam \rtl~55_I .shared_arith = "off"; defparam \rtl~55_I .extended_lut = "off"; defparam \rtl~55_I .lut_mask = "00530F53F053FF53"; cyclonev_lcell_comb \rtl~56_I ( .dataa(\__ALT_INV__rtl~45 ), .datab(\__ALT_INV__rtl~55 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datae(\__ALT_INV__rtl~43 ), .dataf(\__ALT_INV__rtl~50 ), .combout(\rtl~56 )); defparam \rtl~56_I .shared_arith = "off"; defparam \rtl~56_I .extended_lut = "off"; defparam \rtl~56_I .lut_mask = "3050305F3F503F5F"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[21]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~56 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[21] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~58_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux204~0 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux200~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux192~0 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux196~0 ), .combout(\rtl~58 )); defparam \rtl~58_I .shared_arith = "off"; defparam \rtl~58_I .extended_lut = "off"; defparam \rtl~58_I .lut_mask = "5050303F5F5F303F"; cyclonev_lcell_comb \rtl~59_I ( .dataa(\__ALT_INV__rtl~45 ), .datab(\__ALT_INV__rtl~50 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datad(\__ALT_INV__rtl~55 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .dataf(\__ALT_INV__rtl~58 ), .combout(\rtl~59 )); defparam \rtl~59_I .shared_arith = "off"; defparam \rtl~59_I .extended_lut = "off"; defparam \rtl~59_I .lut_mask = "000F3535F0FF3535"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[20]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~59 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[20] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~77 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~85 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~61_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux197~0 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux193~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux201~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux205~0 ), .combout(\rtl~61 )); defparam \rtl~61_I .shared_arith = "off"; defparam \rtl~61_I .extended_lut = "off"; defparam \rtl~61_I .lut_mask = "04073437C4C7F4F7"; cyclonev_lcell_comb \rtl~62_I ( .dataa(\__ALT_INV__rtl~58 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datad(\__ALT_INV__rtl~50 ), .datae(\__ALT_INV__rtl~55 ), .dataf(\__ALT_INV__rtl~61 ), .combout(\rtl~62 )); defparam \rtl~62_I .shared_arith = "off"; defparam \rtl~62_I .extended_lut = "off"; defparam \rtl~62_I .lut_mask = "04073437C4C7F4F7"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[19]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~62 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[19] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~66_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux194~0 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux202~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux198~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux206~0 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~66 )); defparam \rtl~66_I .shared_arith = "off"; defparam \rtl~66_I .extended_lut = "off"; defparam \rtl~66_I .lut_mask = "00FF33330F0F5555"; cyclonev_lcell_comb \rtl~67_I ( .dataa(\__ALT_INV__rtl~58 ), .datab(\__ALT_INV__rtl~61 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datad(\__ALT_INV__rtl~55 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .dataf(\__ALT_INV__rtl~66 ), .combout(\rtl~67 )); defparam \rtl~67_I .shared_arith = "off"; defparam \rtl~67_I .extended_lut = "off"; defparam \rtl~67_I .lut_mask = "0303505FF3F3505F"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[18]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~67 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[18] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~93 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~101 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~71_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux207~0 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux195~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux203~0 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux199~0 ), .combout(\rtl~71 )); defparam \rtl~71_I .shared_arith = "off"; defparam \rtl~71_I .extended_lut = "off"; defparam \rtl~71_I .lut_mask = "505003F35F5F03F3"; cyclonev_lcell_comb \rtl~72_I ( .dataa(\__ALT_INV__rtl~71 ), .datab(\__ALT_INV__rtl~61 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datad(\__ALT_INV__rtl~66 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .dataf(\__ALT_INV__rtl~58 ), .combout(\rtl~72 )); defparam \rtl~72_I .shared_arith = "off"; defparam \rtl~72_I .extended_lut = "off"; defparam \rtl~72_I .lut_mask = "505F3030505F3F3F"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[17]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~72 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[17] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~74_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux200~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux204~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux196~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux208~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~74 )); defparam \rtl~74_I .shared_arith = "off"; defparam \rtl~74_I .extended_lut = "off"; defparam \rtl~74_I .lut_mask = "0505AFAF22772277"; cyclonev_lcell_comb \rtl~75_I ( .dataa(\__ALT_INV__rtl~71 ), .datab(\__ALT_INV__rtl~61 ), .datac(\__ALT_INV__rtl~74 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .dataf(\__ALT_INV__rtl~66 ), .combout(\rtl~75 )); defparam \rtl~75_I .shared_arith = "off"; defparam \rtl~75_I .extended_lut = "off"; defparam \rtl~75_I .lut_mask = "0F5500330F55FF33"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[16]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~75 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[16] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~109 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~117 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~77_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux197~0 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux201~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux205~0 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux209~0 ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .combout(\rtl~77 )); defparam \rtl~77_I .shared_arith = "off"; defparam \rtl~77_I .extended_lut = "off"; defparam \rtl~77_I .lut_mask = "000FFF0F33553355"; cyclonev_lcell_comb \rtl~78_I ( .dataa(\__ALT_INV__rtl~71 ), .datab(\__ALT_INV__rtl~77 ), .datac(\__ALT_INV__rtl~74 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .dataf(\__ALT_INV__rtl~66 ), .combout(\rtl~78 )); defparam \rtl~78_I .shared_arith = "off"; defparam \rtl~78_I .extended_lut = "off"; defparam \rtl~78_I .lut_mask = "330F5500330F55FF"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[15]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~78 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[15] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~121 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~80_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux202~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux210~0 ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux198~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux206~0 ), .combout(\rtl~80 )); defparam \rtl~80_I .shared_arith = "off"; defparam \rtl~80_I .extended_lut = "off"; defparam \rtl~80_I .lut_mask = "048C159D26AE37BF"; cyclonev_lcell_comb \rtl~81_I ( .dataa(\__ALT_INV__rtl~71 ), .datab(\__ALT_INV__rtl~74 ), .datac(\__ALT_INV__rtl~77 ), .datad(\__ALT_INV__rtl~80 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .combout(\rtl~81 )); defparam \rtl~81_I .shared_arith = "off"; defparam \rtl~81_I .extended_lut = "off"; defparam \rtl~81_I .lut_mask = "00FF33330F0F5555"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[14]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~81 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[14] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~141 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~89_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux207~0 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux211~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux203~0 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist18|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__Mux199~0 ), .combout(\rtl~89 )); defparam \rtl~89_I .shared_arith = "off"; defparam \rtl~89_I .extended_lut = "off"; defparam \rtl~89_I .lut_mask = "303F5050303F5F5F"; cyclonev_lcell_comb \rtl~93_I ( .dataa(\__ALT_INV__rtl~89 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datac(\__ALT_INV__rtl~77 ), .datad(\__ALT_INV__rtl~74 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .dataf(\__ALT_INV__rtl~80 ), .combout(\rtl~93 )); defparam \rtl~93_I .shared_arith = "off"; defparam \rtl~93_I .extended_lut = "off"; defparam \rtl~93_I .lut_mask = "44440C3F77770C3F"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[13]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~93 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[13] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~92_I ( .dataa(\__ALT_INV__rtl~89 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .datac(\__ALT_INV__rtl~77 ), .datad(\__ALT_INV__rtl~80 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .dataf(\__ALT_INV__rtl~87 ), .combout(\rtl~92 )); defparam \rtl~92_I .shared_arith = "off"; defparam \rtl~92_I .extended_lut = "off"; defparam \rtl~92_I .lut_mask = "111103CFDDDD03CF"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[12]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~92 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[12] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~137 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~133 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~91_I ( .dataa(\__ALT_INV__rtl~89 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datac(\__ALT_INV__rtl~84 ), .datad(\__ALT_INV__rtl~87 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~80 ), .combout(\rtl~91 )); defparam \rtl~91_I .shared_arith = "off"; defparam \rtl~91_I .extended_lut = "off"; defparam \rtl~91_I .lut_mask = "1D1D00CC1D1D33FF"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[11]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~91 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[11] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \rtl~90_I ( .dataa(\__ALT_INV__rtl~89 ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][1] ), .datac(\__ALT_INV__rtl~84 ), .datad(\__ALT_INV__rtl~86 ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist16|__ALT_INV__delay_signals[0][0] ), .dataf(\__ALT_INV__rtl~87 ), .combout(\rtl~90 )); defparam \rtl~90_I .shared_arith = "off"; defparam \rtl~90_I .extended_lut = "off"; defparam \rtl~90_I .lut_mask = "00CC1D1D33FF1D1D"; dffeas \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[10]~I ( .clk(\clk~CLKENA0 ), .d(\rtl~90 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[10] )); defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add38~129 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist38|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~133_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[10] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][11] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~130 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~133 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~134 )); defparam \fp_pow_0002:fp_pow_inst|Add41~133_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~133_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~133_I .lut_mask = "0000AAAA0000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~137_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][12] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[11] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~134 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~137 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~138 )); defparam \fp_pow_0002:fp_pow_inst|Add41~137_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~137_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~137_I .lut_mask = "00000F0F000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~141_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[12] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][13] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~138 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~141 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~142 )); defparam \fp_pow_0002:fp_pow_inst|Add41~141_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~141_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~141_I .lut_mask = "0000AAAA0000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~145_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][14] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[13] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~142 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~145 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~146 )); defparam \fp_pow_0002:fp_pow_inst|Add41~145_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~145_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~145_I .lut_mask = "00000F0F000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~125_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][15] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[14] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~146 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~125 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~126 )); defparam \fp_pow_0002:fp_pow_inst|Add41~125_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~125_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~125_I .lut_mask = "00000F0F000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~117_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][16] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[15] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~126 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~117 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~118 )); defparam \fp_pow_0002:fp_pow_inst|Add41~117_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~117_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~117_I .lut_mask = "0000F0F00000CCCC"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~109_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[16] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][17] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~118 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~109 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~110 )); defparam \fp_pow_0002:fp_pow_inst|Add41~109_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~109_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~109_I .lut_mask = "0000AAAA0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~101_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][18] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[17] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~110 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~101 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~102 )); defparam \fp_pow_0002:fp_pow_inst|Add41~101_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~101_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~101_I .lut_mask = "00003333000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~93_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[18] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][19] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~102 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~93 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~94 )); defparam \fp_pow_0002:fp_pow_inst|Add41~93_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~93_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~93_I .lut_mask = "0000AAAA0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~85_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][20] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[19] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~94 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~85 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~86 )); defparam \fp_pow_0002:fp_pow_inst|Add41~85_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~85_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~85_I .lut_mask = "00000F0F000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~77_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[20] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][21] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~86 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~78 )); defparam \fp_pow_0002:fp_pow_inst|Add41~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~77_I .lut_mask = "0000AAAA0000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~69_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][22] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[21] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~69 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~70 )); defparam \fp_pow_0002:fp_pow_inst|Add41~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~69_I .lut_mask = "00000F0F000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~61_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[22] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][23] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~70 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~62 )); defparam \fp_pow_0002:fp_pow_inst|Add41~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~61_I .lut_mask = "000000FF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~53_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[23] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~54 )); defparam \fp_pow_0002:fp_pow_inst|Add41~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~53_I .lut_mask = "000000FF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~45_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][25] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[24] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~46 )); defparam \fp_pow_0002:fp_pow_inst|Add41~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~45_I .lut_mask = "0000F0F00000AAAA"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~37_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][26] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[25] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~38 )); defparam \fp_pow_0002:fp_pow_inst|Add41~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~37_I .lut_mask = "0000FF000000CCCC"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][27] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[26] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~1 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~2 )); defparam \fp_pow_0002:fp_pow_inst|Add41~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~1_I .lut_mask = "0000F0F00000AAAA"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~9_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][28] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[27] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~2 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~10 )); defparam \fp_pow_0002:fp_pow_inst|Add41~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~9_I .lut_mask = "0000F0F00000AAAA"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~13_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[28] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][29] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~14 )); defparam \fp_pow_0002:fp_pow_inst|Add41~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~13_I .lut_mask = "0000CCCC0000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~17_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][30] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[29] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~18 )); defparam \fp_pow_0002:fp_pow_inst|Add41~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~17_I .lut_mask = "0000FF000000CCCC"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~21_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[30] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][31] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~22 )); defparam \fp_pow_0002:fp_pow_inst|Add41~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~21_I .lut_mask = "0000AAAA0000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~25_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][32] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[31] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~26 )); defparam \fp_pow_0002:fp_pow_inst|Add41~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~25_I .lut_mask = "0000F0F00000CCCC"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~29_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[32] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][33] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~30 )); defparam \fp_pow_0002:fp_pow_inst|Add41~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~29_I .lut_mask = "0000AAAA0000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~33_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[33] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][34] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~34 )); defparam \fp_pow_0002:fp_pow_inst|Add41~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~33_I .lut_mask = "0000AAAA0000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~122_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][35] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[34] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~34 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~122 )); defparam \fp_pow_0002:fp_pow_inst|Add41~122_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~122_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~122_I .lut_mask = "00000F0F000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~114_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][36] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[35] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~122 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~114 )); defparam \fp_pow_0002:fp_pow_inst|Add41~114_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~114_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~114_I .lut_mask = "0000F0F00000CCCC"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~106_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][37] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[36] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~114 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~106 )); defparam \fp_pow_0002:fp_pow_inst|Add41~106_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~106_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~106_I .lut_mask = "0000F0F00000AAAA"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~98_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][38] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[37] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~106 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~98 )); defparam \fp_pow_0002:fp_pow_inst|Add41~98_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~98_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~98_I .lut_mask = "00003333000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~90_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][39] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[38] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~98 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~90 )); defparam \fp_pow_0002:fp_pow_inst|Add41~90_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~90_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~90_I .lut_mask = "0000F0F00000AAAA"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~82_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[39] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][40] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~90 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~82 )); defparam \fp_pow_0002:fp_pow_inst|Add41~82_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~82_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~82_I .lut_mask = "0000CCCC0000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~74_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[40] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][41] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~82 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~74 )); defparam \fp_pow_0002:fp_pow_inst|Add41~74_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~74_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~74_I .lut_mask = "0000AAAA0000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~66_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[41] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][42] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~74 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~66 )); defparam \fp_pow_0002:fp_pow_inst|Add41~66_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~66_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~66_I .lut_mask = "0000CCCC0000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~58_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][43] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[42] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~66 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~58 )); defparam \fp_pow_0002:fp_pow_inst|Add41~58_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~58_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~58_I .lut_mask = "00005555000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~50_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][44] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[43] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~58 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~50 )); defparam \fp_pow_0002:fp_pow_inst|Add41~50_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~50_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~50_I .lut_mask = "00003333000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~42_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][45] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[43] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~50 ), .cout(\fp_pow_0002:fp_pow_inst|Add41~42 )); defparam \fp_pow_0002:fp_pow_inst|Add41~42_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~42_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~42_I .lut_mask = "0000F0F00000AAAA"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add41~5_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__rightShiftStage2_uid673_fxpInPostAlign_X_uid134_fpPowrTest_q[43] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist38|__ALT_INV__delay_signals[0][45] ), .cin(\fp_pow_0002:fp_pow_inst|Add41~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add41~5 )); defparam \fp_pow_0002:fp_pow_inst|Add41~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add41~5_I .lut_mask = "0000CCCC0000F0F0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0]~0_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "FFFFFFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5482,portadatain_unconnected_wire_5483,portadatain_unconnected_wire_5484,portadatain_unconnected_wire_5485,portadatain_unconnected_wire_5486,portadatain_unconnected_wire_5487,portadatain_unconnected_wire_5488, portadatain_unconnected_wire_5489,portadatain_unconnected_wire_5490,portadatain_unconnected_wire_5491,portadatain_unconnected_wire_5492,portadatain_unconnected_wire_5493,portadatain_unconnected_wire_5494,portadatain_unconnected_wire_5495, portadatain_unconnected_wire_5496,portadatain_unconnected_wire_5497,portadatain_unconnected_wire_5498,portadatain_unconnected_wire_5499,portadatain_unconnected_wire_5500,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][9] }), .portaaddr({portaaddr_unconnected_wire_5501,portaaddr_unconnected_wire_5502,portaaddr_unconnected_wire_5503,portaaddr_unconnected_wire_5504,portaaddr_unconnected_wire_5505,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5506,portbaddr_unconnected_wire_5507,portbaddr_unconnected_wire_5508,portbaddr_unconnected_wire_5509,portbaddr_unconnected_wire_5510, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[9] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9 .first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama9 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~133 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][10]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[0][10] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][10]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][10]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][10]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][10]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][10]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5511,portadatain_unconnected_wire_5512,portadatain_unconnected_wire_5513,portadatain_unconnected_wire_5514,portadatain_unconnected_wire_5515,portadatain_unconnected_wire_5516,portadatain_unconnected_wire_5517, portadatain_unconnected_wire_5518,portadatain_unconnected_wire_5519,portadatain_unconnected_wire_5520,portadatain_unconnected_wire_5521,portadatain_unconnected_wire_5522,portadatain_unconnected_wire_5523,portadatain_unconnected_wire_5524, portadatain_unconnected_wire_5525,portadatain_unconnected_wire_5526,portadatain_unconnected_wire_5527,portadatain_unconnected_wire_5528,portadatain_unconnected_wire_5529,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][10] }), .portaaddr({portaaddr_unconnected_wire_5530,portaaddr_unconnected_wire_5531,portaaddr_unconnected_wire_5532,portaaddr_unconnected_wire_5533,portaaddr_unconnected_wire_5534,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5535,portbaddr_unconnected_wire_5536,portbaddr_unconnected_wire_5537,portbaddr_unconnected_wire_5538,portbaddr_unconnected_wire_5539, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[10] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10 .first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama10 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~137 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][11]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][11] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][11]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][11]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][11]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][11]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][11]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][11]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[1][11] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][11]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][11]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][11]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][11]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][11]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5540,portadatain_unconnected_wire_5541,portadatain_unconnected_wire_5542,portadatain_unconnected_wire_5543,portadatain_unconnected_wire_5544,portadatain_unconnected_wire_5545,portadatain_unconnected_wire_5546, portadatain_unconnected_wire_5547,portadatain_unconnected_wire_5548,portadatain_unconnected_wire_5549,portadatain_unconnected_wire_5550,portadatain_unconnected_wire_5551,portadatain_unconnected_wire_5552,portadatain_unconnected_wire_5553, portadatain_unconnected_wire_5554,portadatain_unconnected_wire_5555,portadatain_unconnected_wire_5556,portadatain_unconnected_wire_5557,portadatain_unconnected_wire_5558,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][11] }), .portaaddr({portaaddr_unconnected_wire_5559,portaaddr_unconnected_wire_5560,portaaddr_unconnected_wire_5561,portaaddr_unconnected_wire_5562,portaaddr_unconnected_wire_5563,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5564,portbaddr_unconnected_wire_5565,portbaddr_unconnected_wire_5566,portbaddr_unconnected_wire_5567,portbaddr_unconnected_wire_5568, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[11] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11 .first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama11 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~141 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5569,portadatain_unconnected_wire_5570,portadatain_unconnected_wire_5571,portadatain_unconnected_wire_5572,portadatain_unconnected_wire_5573,portadatain_unconnected_wire_5574,portadatain_unconnected_wire_5575, portadatain_unconnected_wire_5576,portadatain_unconnected_wire_5577,portadatain_unconnected_wire_5578,portadatain_unconnected_wire_5579,portadatain_unconnected_wire_5580,portadatain_unconnected_wire_5581,portadatain_unconnected_wire_5582, portadatain_unconnected_wire_5583,portadatain_unconnected_wire_5584,portadatain_unconnected_wire_5585,portadatain_unconnected_wire_5586,portadatain_unconnected_wire_5587,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][12] }), .portaaddr({portaaddr_unconnected_wire_5588,portaaddr_unconnected_wire_5589,portaaddr_unconnected_wire_5590,portaaddr_unconnected_wire_5591,portaaddr_unconnected_wire_5592,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5593,portbaddr_unconnected_wire_5594,portbaddr_unconnected_wire_5595,portbaddr_unconnected_wire_5596,portbaddr_unconnected_wire_5597, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[12] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12 .first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama12 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~145 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][13]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][13] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][13]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][13]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][13]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][13]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][13]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][13]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[1][13] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][13]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][13]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][13]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][13]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][13]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][13]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[0][13] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][13]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][13]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][13]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][13]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][13]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][13]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][13]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[1][13] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][13]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][13]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][13]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][13]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][13]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][13]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[0][13] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][13]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][13]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][13]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][13]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][13]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5598,portadatain_unconnected_wire_5599,portadatain_unconnected_wire_5600,portadatain_unconnected_wire_5601,portadatain_unconnected_wire_5602,portadatain_unconnected_wire_5603,portadatain_unconnected_wire_5604, portadatain_unconnected_wire_5605,portadatain_unconnected_wire_5606,portadatain_unconnected_wire_5607,portadatain_unconnected_wire_5608,portadatain_unconnected_wire_5609,portadatain_unconnected_wire_5610,portadatain_unconnected_wire_5611, portadatain_unconnected_wire_5612,portadatain_unconnected_wire_5613,portadatain_unconnected_wire_5614,portadatain_unconnected_wire_5615,portadatain_unconnected_wire_5616,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][13] }), .portaaddr({portaaddr_unconnected_wire_5617,portaaddr_unconnected_wire_5618,portaaddr_unconnected_wire_5619,portaaddr_unconnected_wire_5620,portaaddr_unconnected_wire_5621,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5622,portbaddr_unconnected_wire_5623,portbaddr_unconnected_wire_5624,portbaddr_unconnected_wire_5625,portbaddr_unconnected_wire_5626, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[13] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13 .first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama13 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~125 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][14]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][14] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][14]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][14]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][14]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][14]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][14]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][14]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[1][14] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][14]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][14]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][14]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][14]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][14]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][14] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][14]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|__ALT_INV__delay_signals[0][14] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][14]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][14]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][14]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][14]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][14]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][14]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[1][14] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][14]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][14]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][14]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][14]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][14]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][14] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5627,portadatain_unconnected_wire_5628,portadatain_unconnected_wire_5629,portadatain_unconnected_wire_5630,portadatain_unconnected_wire_5631,portadatain_unconnected_wire_5632,portadatain_unconnected_wire_5633, portadatain_unconnected_wire_5634,portadatain_unconnected_wire_5635,portadatain_unconnected_wire_5636,portadatain_unconnected_wire_5637,portadatain_unconnected_wire_5638,portadatain_unconnected_wire_5639,portadatain_unconnected_wire_5640, portadatain_unconnected_wire_5641,portadatain_unconnected_wire_5642,portadatain_unconnected_wire_5643,portadatain_unconnected_wire_5644,portadatain_unconnected_wire_5645,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][14] }), .portaaddr({portaaddr_unconnected_wire_5646,portaaddr_unconnected_wire_5647,portaaddr_unconnected_wire_5648,portaaddr_unconnected_wire_5649,portaaddr_unconnected_wire_5650,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5651,portbaddr_unconnected_wire_5652,portbaddr_unconnected_wire_5653,portbaddr_unconnected_wire_5654,portbaddr_unconnected_wire_5655, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[14] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14 .first_bit_number = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama14 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~117 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][15]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][15] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][15]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][15]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][15]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][15]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][15]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][15]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][15]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[1][15] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][15]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][15]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][15]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][15]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][15]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5656,portadatain_unconnected_wire_5657,portadatain_unconnected_wire_5658,portadatain_unconnected_wire_5659,portadatain_unconnected_wire_5660,portadatain_unconnected_wire_5661,portadatain_unconnected_wire_5662, portadatain_unconnected_wire_5663,portadatain_unconnected_wire_5664,portadatain_unconnected_wire_5665,portadatain_unconnected_wire_5666,portadatain_unconnected_wire_5667,portadatain_unconnected_wire_5668,portadatain_unconnected_wire_5669, portadatain_unconnected_wire_5670,portadatain_unconnected_wire_5671,portadatain_unconnected_wire_5672,portadatain_unconnected_wire_5673,portadatain_unconnected_wire_5674,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][15] }), .portaaddr({portaaddr_unconnected_wire_5675,portaaddr_unconnected_wire_5676,portaaddr_unconnected_wire_5677,portaaddr_unconnected_wire_5678,portaaddr_unconnected_wire_5679,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5680,portbaddr_unconnected_wire_5681,portbaddr_unconnected_wire_5682,portbaddr_unconnected_wire_5683,portbaddr_unconnected_wire_5684, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[15] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15 .first_bit_number = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama15 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~109 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][16]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][16] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][16]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][16]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][16]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][16]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][16]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][16]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][16]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[1][16] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][16]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][16]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][16]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][16]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][16]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5685,portadatain_unconnected_wire_5686,portadatain_unconnected_wire_5687,portadatain_unconnected_wire_5688,portadatain_unconnected_wire_5689,portadatain_unconnected_wire_5690,portadatain_unconnected_wire_5691, portadatain_unconnected_wire_5692,portadatain_unconnected_wire_5693,portadatain_unconnected_wire_5694,portadatain_unconnected_wire_5695,portadatain_unconnected_wire_5696,portadatain_unconnected_wire_5697,portadatain_unconnected_wire_5698, portadatain_unconnected_wire_5699,portadatain_unconnected_wire_5700,portadatain_unconnected_wire_5701,portadatain_unconnected_wire_5702,portadatain_unconnected_wire_5703,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][16] }), .portaaddr({portaaddr_unconnected_wire_5704,portaaddr_unconnected_wire_5705,portaaddr_unconnected_wire_5706,portaaddr_unconnected_wire_5707,portaaddr_unconnected_wire_5708,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5709,portbaddr_unconnected_wire_5710,portbaddr_unconnected_wire_5711,portbaddr_unconnected_wire_5712,portbaddr_unconnected_wire_5713, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[16] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16 .first_bit_number = 16; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama16 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~101 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][17]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][17] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][17]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][17]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][17]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][17]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][17]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][17]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[1][17] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][17]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][17]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][17]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][17]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][17]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][17]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5714,portadatain_unconnected_wire_5715,portadatain_unconnected_wire_5716,portadatain_unconnected_wire_5717,portadatain_unconnected_wire_5718,portadatain_unconnected_wire_5719,portadatain_unconnected_wire_5720, portadatain_unconnected_wire_5721,portadatain_unconnected_wire_5722,portadatain_unconnected_wire_5723,portadatain_unconnected_wire_5724,portadatain_unconnected_wire_5725,portadatain_unconnected_wire_5726,portadatain_unconnected_wire_5727, portadatain_unconnected_wire_5728,portadatain_unconnected_wire_5729,portadatain_unconnected_wire_5730,portadatain_unconnected_wire_5731,portadatain_unconnected_wire_5732,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][17] }), .portaaddr({portaaddr_unconnected_wire_5733,portaaddr_unconnected_wire_5734,portaaddr_unconnected_wire_5735,portaaddr_unconnected_wire_5736,portaaddr_unconnected_wire_5737,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5738,portbaddr_unconnected_wire_5739,portbaddr_unconnected_wire_5740,portbaddr_unconnected_wire_5741,portbaddr_unconnected_wire_5742, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[17] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17 .first_bit_number = 17; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama17 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~93 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][18]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][18] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][18]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][18]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][18]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][18]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][18]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][18]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[1][18] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][18]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][18]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][18]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][18]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][18]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5743,portadatain_unconnected_wire_5744,portadatain_unconnected_wire_5745,portadatain_unconnected_wire_5746,portadatain_unconnected_wire_5747,portadatain_unconnected_wire_5748,portadatain_unconnected_wire_5749, portadatain_unconnected_wire_5750,portadatain_unconnected_wire_5751,portadatain_unconnected_wire_5752,portadatain_unconnected_wire_5753,portadatain_unconnected_wire_5754,portadatain_unconnected_wire_5755,portadatain_unconnected_wire_5756, portadatain_unconnected_wire_5757,portadatain_unconnected_wire_5758,portadatain_unconnected_wire_5759,portadatain_unconnected_wire_5760,portadatain_unconnected_wire_5761,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][18] }), .portaaddr({portaaddr_unconnected_wire_5762,portaaddr_unconnected_wire_5763,portaaddr_unconnected_wire_5764,portaaddr_unconnected_wire_5765,portaaddr_unconnected_wire_5766,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5767,portbaddr_unconnected_wire_5768,portbaddr_unconnected_wire_5769,portbaddr_unconnected_wire_5770,portbaddr_unconnected_wire_5771, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[18] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18 .first_bit_number = 18; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama18 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~85 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][19]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][19]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[0][19] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][19]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][19]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][19]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][19]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][19]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][19]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][19]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[1][19] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][19]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][19]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][19]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][19]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][19]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][19]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5772,portadatain_unconnected_wire_5773,portadatain_unconnected_wire_5774,portadatain_unconnected_wire_5775,portadatain_unconnected_wire_5776,portadatain_unconnected_wire_5777,portadatain_unconnected_wire_5778, portadatain_unconnected_wire_5779,portadatain_unconnected_wire_5780,portadatain_unconnected_wire_5781,portadatain_unconnected_wire_5782,portadatain_unconnected_wire_5783,portadatain_unconnected_wire_5784,portadatain_unconnected_wire_5785, portadatain_unconnected_wire_5786,portadatain_unconnected_wire_5787,portadatain_unconnected_wire_5788,portadatain_unconnected_wire_5789,portadatain_unconnected_wire_5790,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][19] }), .portaaddr({portaaddr_unconnected_wire_5791,portaaddr_unconnected_wire_5792,portaaddr_unconnected_wire_5793,portaaddr_unconnected_wire_5794,portaaddr_unconnected_wire_5795,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5796,portbaddr_unconnected_wire_5797,portbaddr_unconnected_wire_5798,portbaddr_unconnected_wire_5799,portbaddr_unconnected_wire_5800, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[19] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19 .first_bit_number = 19; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama19 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~77 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][20]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][20] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][20] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][20] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][20]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][20] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][20] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][20] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5801,portadatain_unconnected_wire_5802,portadatain_unconnected_wire_5803,portadatain_unconnected_wire_5804,portadatain_unconnected_wire_5805,portadatain_unconnected_wire_5806,portadatain_unconnected_wire_5807, portadatain_unconnected_wire_5808,portadatain_unconnected_wire_5809,portadatain_unconnected_wire_5810,portadatain_unconnected_wire_5811,portadatain_unconnected_wire_5812,portadatain_unconnected_wire_5813,portadatain_unconnected_wire_5814, portadatain_unconnected_wire_5815,portadatain_unconnected_wire_5816,portadatain_unconnected_wire_5817,portadatain_unconnected_wire_5818,portadatain_unconnected_wire_5819,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][20] }), .portaaddr({portaaddr_unconnected_wire_5820,portaaddr_unconnected_wire_5821,portaaddr_unconnected_wire_5822,portaaddr_unconnected_wire_5823,portaaddr_unconnected_wire_5824,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5825,portbaddr_unconnected_wire_5826,portbaddr_unconnected_wire_5827,portbaddr_unconnected_wire_5828,portbaddr_unconnected_wire_5829, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[20] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20 .first_bit_number = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama20 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~69 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][21]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][21] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][21]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][21]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][21]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][21]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][21]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][21]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][21]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5830,portadatain_unconnected_wire_5831,portadatain_unconnected_wire_5832,portadatain_unconnected_wire_5833,portadatain_unconnected_wire_5834,portadatain_unconnected_wire_5835,portadatain_unconnected_wire_5836, portadatain_unconnected_wire_5837,portadatain_unconnected_wire_5838,portadatain_unconnected_wire_5839,portadatain_unconnected_wire_5840,portadatain_unconnected_wire_5841,portadatain_unconnected_wire_5842,portadatain_unconnected_wire_5843, portadatain_unconnected_wire_5844,portadatain_unconnected_wire_5845,portadatain_unconnected_wire_5846,portadatain_unconnected_wire_5847,portadatain_unconnected_wire_5848,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][21] }), .portaaddr({portaaddr_unconnected_wire_5849,portaaddr_unconnected_wire_5850,portaaddr_unconnected_wire_5851,portaaddr_unconnected_wire_5852,portaaddr_unconnected_wire_5853,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5854,portbaddr_unconnected_wire_5855,portbaddr_unconnected_wire_5856,portbaddr_unconnected_wire_5857,portbaddr_unconnected_wire_5858, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[21] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21 .first_bit_number = 21; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama21 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~61 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][22]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][22] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][22] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][22]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[0][22] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][22]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][22]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][22]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][22]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][22]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][22]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|__ALT_INV__delay_signals[0][22] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][22]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][22]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][22]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][22]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][22]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][22] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][22] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5859,portadatain_unconnected_wire_5860,portadatain_unconnected_wire_5861,portadatain_unconnected_wire_5862,portadatain_unconnected_wire_5863,portadatain_unconnected_wire_5864,portadatain_unconnected_wire_5865, portadatain_unconnected_wire_5866,portadatain_unconnected_wire_5867,portadatain_unconnected_wire_5868,portadatain_unconnected_wire_5869,portadatain_unconnected_wire_5870,portadatain_unconnected_wire_5871,portadatain_unconnected_wire_5872, portadatain_unconnected_wire_5873,portadatain_unconnected_wire_5874,portadatain_unconnected_wire_5875,portadatain_unconnected_wire_5876,portadatain_unconnected_wire_5877,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][22] }), .portaaddr({portaaddr_unconnected_wire_5878,portaaddr_unconnected_wire_5879,portaaddr_unconnected_wire_5880,portaaddr_unconnected_wire_5881,portaaddr_unconnected_wire_5882,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5883,portbaddr_unconnected_wire_5884,portbaddr_unconnected_wire_5885,portbaddr_unconnected_wire_5886,portbaddr_unconnected_wire_5887, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[22] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22 .first_bit_number = 22; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama22 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][23]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][23] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][23]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][23]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][23]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][23]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][23]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][23]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[1][23] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][23]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][23]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][23]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][23]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][23]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][23]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[0][23] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][23]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][23]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][23]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][23]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][23]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][23]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|__ALT_INV__delay_signals[0][23] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][23]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][23]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][23]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][23]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][23]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][23]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][23] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][23]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][23] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5888,portadatain_unconnected_wire_5889,portadatain_unconnected_wire_5890,portadatain_unconnected_wire_5891,portadatain_unconnected_wire_5892,portadatain_unconnected_wire_5893,portadatain_unconnected_wire_5894, portadatain_unconnected_wire_5895,portadatain_unconnected_wire_5896,portadatain_unconnected_wire_5897,portadatain_unconnected_wire_5898,portadatain_unconnected_wire_5899,portadatain_unconnected_wire_5900,portadatain_unconnected_wire_5901, portadatain_unconnected_wire_5902,portadatain_unconnected_wire_5903,portadatain_unconnected_wire_5904,portadatain_unconnected_wire_5905,portadatain_unconnected_wire_5906,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][23] }), .portaaddr({portaaddr_unconnected_wire_5907,portaaddr_unconnected_wire_5908,portaaddr_unconnected_wire_5909,portaaddr_unconnected_wire_5910,portaaddr_unconnected_wire_5911,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5912,portbaddr_unconnected_wire_5913,portbaddr_unconnected_wire_5914,portbaddr_unconnected_wire_5915,portbaddr_unconnected_wire_5916, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[23] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23 .first_bit_number = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama23 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][24]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][24]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][24] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][24]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][24] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][24]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][24] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][24]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][24]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][24] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][24]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][24] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][24]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][24] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5917,portadatain_unconnected_wire_5918,portadatain_unconnected_wire_5919,portadatain_unconnected_wire_5920,portadatain_unconnected_wire_5921,portadatain_unconnected_wire_5922,portadatain_unconnected_wire_5923, portadatain_unconnected_wire_5924,portadatain_unconnected_wire_5925,portadatain_unconnected_wire_5926,portadatain_unconnected_wire_5927,portadatain_unconnected_wire_5928,portadatain_unconnected_wire_5929,portadatain_unconnected_wire_5930, portadatain_unconnected_wire_5931,portadatain_unconnected_wire_5932,portadatain_unconnected_wire_5933,portadatain_unconnected_wire_5934,portadatain_unconnected_wire_5935,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][24] }), .portaaddr({portaaddr_unconnected_wire_5936,portaaddr_unconnected_wire_5937,portaaddr_unconnected_wire_5938,portaaddr_unconnected_wire_5939,portaaddr_unconnected_wire_5940,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5941,portbaddr_unconnected_wire_5942,portbaddr_unconnected_wire_5943,portbaddr_unconnected_wire_5944,portbaddr_unconnected_wire_5945, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[24] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24 .first_bit_number = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama24 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][25]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][25] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][25] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][25]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|__ALT_INV__delay_signals[0][25] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][25]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][25]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][25]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][25]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][25]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][25]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|__ALT_INV__delay_signals[0][25] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][25]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][25]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][25]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][25]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][25]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][25]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[1][25] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][25]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][25]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][25]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][25]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][25]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][25] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][25]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_5946,portadatain_unconnected_wire_5947,portadatain_unconnected_wire_5948,portadatain_unconnected_wire_5949,portadatain_unconnected_wire_5950,portadatain_unconnected_wire_5951,portadatain_unconnected_wire_5952, portadatain_unconnected_wire_5953,portadatain_unconnected_wire_5954,portadatain_unconnected_wire_5955,portadatain_unconnected_wire_5956,portadatain_unconnected_wire_5957,portadatain_unconnected_wire_5958,portadatain_unconnected_wire_5959, portadatain_unconnected_wire_5960,portadatain_unconnected_wire_5961,portadatain_unconnected_wire_5962,portadatain_unconnected_wire_5963,portadatain_unconnected_wire_5964,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][25] }), .portaaddr({portaaddr_unconnected_wire_5965,portaaddr_unconnected_wire_5966,portaaddr_unconnected_wire_5967,portaaddr_unconnected_wire_5968,portaaddr_unconnected_wire_5969,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_5970,portbaddr_unconnected_wire_5971,portbaddr_unconnected_wire_5972,portbaddr_unconnected_wire_5973,portbaddr_unconnected_wire_5974, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[25] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25 .first_bit_number = 25; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama25 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_c0[1][17]~0_I ( .combout(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_c0[1][17]~0 )); defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_c0[1][17]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_c0[1][17]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_c0[1][17]~0_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[1][0]~0_I ( .combout(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[1][0]~0 )); defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[1][0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[1][0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[1][0]~0_I .lut_mask = "0000000000000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][26] ), .combout(\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0_I .lut_mask = "00000000CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][27] ), .combout(\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 )); defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1_I .lut_mask = "00000000CCCCCCCC"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][28] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 )); defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2_I .lut_mask = "3333000033330000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3_I ( .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][29] ), .combout(\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 )); defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3_I .lut_mask = "00000000FFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][30] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 )); defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4_I .lut_mask = "00FF00FF00000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5_I ( .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][31] ), .combout(\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 )); defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5_I .lut_mask = "00000000FFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][32] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 )); defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6_I .lut_mask = "00FF00FF00000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7_I ( .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][33] ), .combout(\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 )); defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7_I .lut_mask = "00000000FFFF0000"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .init_file = "fp_pow_0002_memoryC3_uid426_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_a_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_a_first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_b_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_b_first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a0 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[1] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .init_file = "fp_pow_0002_memoryC3_uid426_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_a_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_a_first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_b_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_b_first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a1 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[2] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .init_file = "fp_pow_0002_memoryC3_uid426_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_a_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_a_first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_b_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_b_first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a2 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[3] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .init_file = "fp_pow_0002_memoryC3_uid426_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_a_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_a_first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_b_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_b_first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a3 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[4] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .init_file = "fp_pow_0002_memoryC3_uid426_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_a_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_a_first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_b_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_b_first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a4 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[5] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .init_file = "fp_pow_0002_memoryC3_uid426_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_a_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_a_first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_b_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_b_first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a5 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[6] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .init_file = "fp_pow_0002_memoryC3_uid426_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_a_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_a_first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_b_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_b_first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a6 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[7] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .init_file = "fp_pow_0002_memoryC3_uid426_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_a_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_a_first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_b_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_b_first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a7 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[8] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .init_file = "fp_pow_0002_memoryC3_uid426_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_a_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_a_first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_b_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_b_first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a8 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[9] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .init_file = "fp_pow_0002_memoryC3_uid426_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_a_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_a_first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_b_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_b_first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a9 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[10] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .init_file = "fp_pow_0002_memoryC3_uid426_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_a_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_a_first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_b_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_b_first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a10 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[11] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .init_file = "fp_pow_0002_memoryC3_uid426_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_a_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_a_first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_b_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_b_first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a11 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[12] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .init_file = "fp_pow_0002_memoryC3_uid426_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_a_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_a_first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_b_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_b_first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a12 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[13] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .init_file = "fp_pow_0002_memoryC3_uid426_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_a_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_a_first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_b_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_b_first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a13 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[14] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .init_file = "fp_pow_0002_memoryC3_uid426_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_a_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_a_first_bit_number = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_b_logical_ram_width = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_b_first_bit_number = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|ram_block2a14 .port_b_read_during_write_mode = "new_data_no_nbe_read"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][14]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][14]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][14]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][14]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][14]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][14]~DUPLICATE_I .created_from = "Q(delay_signals[0][14])"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][17]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][17]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][17]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][17]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][17]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][17]~DUPLICATE_I .created_from = "Q(delay_signals[0][17])"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][20]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][20] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][20]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][20]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][20]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][20]~DUPLICATE_I .created_from = "Q(delay_signals[0][20])"; cyclonev_mac \fp_pow_0002:fp_pow_inst|Mult12~8_I ( .sub(gnd), .negate(gnd), .ax({ax_unconnected_wire_5975,ax_unconnected_wire_5976,ax_unconnected_wire_5977,ax_unconnected_wire_5978,ax_unconnected_wire_5979,ax_unconnected_wire_5980,ax_unconnected_wire_5981,ax_unconnected_wire_5982,ax_unconnected_wire_5983, \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[14] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[14] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[14] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[14] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[13] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[12] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[11] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[10] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[9] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[8] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[7] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[6] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[5] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC3_uid426_expTabGen_lutmem_dmem|altera_syncram_csl3:auto_generated|altsyncram_hme4:altsyncram1|q_b[0] }), .ay({ay_unconnected_wire_5984,ay_unconnected_wire_5985,ay_unconnected_wire_5986,ay_unconnected_wire_5987,ay_unconnected_wire_5988,ay_unconnected_wire_5989,ay_unconnected_wire_5990,ay_unconnected_wire_5991,ay_unconnected_wire_5992,ay_unconnected_wire_5993, ay_unconnected_wire_5994,ay_unconnected_wire_5995,\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][25] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][24] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][23] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][22] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][21] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][20]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][19] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][18] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][17]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][16] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][15] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][14]~DUPLICATE , \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][13] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][12] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][11] }), .clk({clk_unconnected_wire_5996,clk_unconnected_wire_5997,\clk~CLKENA0 }), .aclr({\areset~CLKENA0 ,\areset~CLKENA0 }), .ena({ena_unconnected_wire_5998,ena_unconnected_wire_5999,\vcc }), .resulta({\fp_pow_0002:fp_pow_inst|Mult12~56 ,\fp_pow_0002:fp_pow_inst|Mult12~55 ,\fp_pow_0002:fp_pow_inst|Mult12~54 ,\fp_pow_0002:fp_pow_inst|Mult12~53 ,\fp_pow_0002:fp_pow_inst|Mult12~52 ,\fp_pow_0002:fp_pow_inst|Mult12~51 ,\fp_pow_0002:fp_pow_inst|Mult12~50 , \fp_pow_0002:fp_pow_inst|Mult12~49 ,\fp_pow_0002:fp_pow_inst|Mult12~48 ,\fp_pow_0002:fp_pow_inst|Mult12~47 ,\fp_pow_0002:fp_pow_inst|Mult12~46 ,\fp_pow_0002:fp_pow_inst|Mult12~45 ,\fp_pow_0002:fp_pow_inst|Mult12~44 ,\fp_pow_0002:fp_pow_inst|Mult12~43 , \fp_pow_0002:fp_pow_inst|Mult12~42 ,\fp_pow_0002:fp_pow_inst|Mult12~41 ,\fp_pow_0002:fp_pow_inst|Mult12~40 ,\fp_pow_0002:fp_pow_inst|Mult12~39 ,\fp_pow_0002:fp_pow_inst|Mult12~38 ,\fp_pow_0002:fp_pow_inst|Mult12~37 ,\fp_pow_0002:fp_pow_inst|Mult12~36 , \fp_pow_0002:fp_pow_inst|Mult12~35 ,\fp_pow_0002:fp_pow_inst|Mult12~34 ,\fp_pow_0002:fp_pow_inst|Mult12~33 ,\fp_pow_0002:fp_pow_inst|Mult12~32 ,\fp_pow_0002:fp_pow_inst|Mult12~31 ,\fp_pow_0002:fp_pow_inst|Mult12~30 ,\fp_pow_0002:fp_pow_inst|Mult12~29 , \fp_pow_0002:fp_pow_inst|Mult12~28 ,\fp_pow_0002:fp_pow_inst|Mult12~27 ,\fp_pow_0002:fp_pow_inst|Mult12~26 ,\fp_pow_0002:fp_pow_inst|Mult12~25 ,\fp_pow_0002:fp_pow_inst|Mult12~24 ,\fp_pow_0002:fp_pow_inst|Mult12~23 , \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][29] ,\fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][28] ,\fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][27] , \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][26] ,\fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][25] ,\fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][24] , \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][23] ,\fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][22] ,\fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][21] , \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][20] ,\fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][19] ,\fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][18] , \fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][17] ,\fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][16] ,\fp_pow_0002:fp_pow_inst|prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][15] , \fp_pow_0002:fp_pow_inst|Mult12~22 ,\fp_pow_0002:fp_pow_inst|Mult12~21 ,\fp_pow_0002:fp_pow_inst|Mult12~20 ,\fp_pow_0002:fp_pow_inst|Mult12~19 ,\fp_pow_0002:fp_pow_inst|Mult12~18 ,\fp_pow_0002:fp_pow_inst|Mult12~17 ,\fp_pow_0002:fp_pow_inst|Mult12~16 , \fp_pow_0002:fp_pow_inst|Mult12~15 ,\fp_pow_0002:fp_pow_inst|Mult12~14 ,\fp_pow_0002:fp_pow_inst|Mult12~13 ,\fp_pow_0002:fp_pow_inst|Mult12~12 ,\fp_pow_0002:fp_pow_inst|Mult12~11 ,\fp_pow_0002:fp_pow_inst|Mult12~10 ,\fp_pow_0002:fp_pow_inst|Mult12~9 , \fp_pow_0002:fp_pow_inst|Mult12~8 })); defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .signed_max = "true"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .signed_may = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .signed_mbx = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .signed_mby = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .preadder_subtract_a = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .preadder_subtract_b = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .ay_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .by_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .delay_scan_out_ay = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .delay_scan_out_by = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .use_chainadder = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .enable_double_accum = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .operation_mode = "M18X18_FULL"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .operand_source_max = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .operand_source_may = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .operand_source_mbx = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .operand_source_mby = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .ax_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .ay_scan_in_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .az_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .bx_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .by_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .bz_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .coef_sel_a_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .coef_sel_b_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .sub_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .negate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .accumulate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .load_const_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .output_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .coef_a_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .coef_a_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .coef_a_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .coef_a_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .coef_a_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .coef_a_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .coef_a_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .coef_a_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .coef_b_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .coef_b_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .coef_b_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .coef_b_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .coef_b_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .coef_b_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .coef_b_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .coef_b_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .ax_width = 18; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .ay_scan_in_width = 15; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .mode_sub_location = 0; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .load_const_value = 0; defparam \fp_pow_0002:fp_pow_inst|Mult12~8_I .result_a_width = 64; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][15] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__addrExp_uid142_fpPowrTest_b[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[1][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__addrExp_uid142_fpPowrTest_b[3]~3 ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[1][3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[1][4] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[1][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_a_first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_b_first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a0 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[1] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_a_first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_b_first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a1 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[2] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_a_first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_b_first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a2 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[3] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_a_first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_b_first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a3 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[4] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_a_first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_b_first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a4 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[5] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_a_first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_b_first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a5 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[6] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_a_first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_b_first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a6 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[7] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_a_first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_b_first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a7 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[8] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_a_first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_b_first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a8 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[9] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_a_first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_b_first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a9 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[10] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_a_first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_b_first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a10 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[11] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_a_first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_b_first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a11 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[12] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_a_first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_b_first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a12 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[13] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_a_first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_b_first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a13 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[14] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_a_first_bit_number = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_b_first_bit_number = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a14 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[15] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_a_first_bit_number = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_b_first_bit_number = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a15 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[16] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_a_first_bit_number = 16; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_b_first_bit_number = 16; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a16 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[17] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_a_first_bit_number = 17; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_b_first_bit_number = 17; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a17 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[18] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_a_first_bit_number = 18; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_b_first_bit_number = 18; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a18 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[19] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_a_first_bit_number = 19; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_b_first_bit_number = 19; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a19 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[20] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_a_first_bit_number = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_b_first_bit_number = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a20 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[21] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_a_first_bit_number = 21; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_b_first_bit_number = 21; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a21 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[22] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_a_first_bit_number = 22; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_b_first_bit_number = 22; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a22 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|q_b[23] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .init_file = "fp_pow_0002_memoryC2_uid424_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_a_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_a_first_bit_number = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_b_logical_ram_width = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_b_first_bit_number = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|ram_block2a23 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~1_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][16] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[0] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add42~1 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~2 )); defparam \fp_pow_0002:fp_pow_inst|Add42~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~1_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][17] ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[1] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~2 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~6 )); defparam \fp_pow_0002:fp_pow_inst|Add42~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~5_I .lut_mask = "0000AAAA00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~9_I ( .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[2] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][18] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~10 )); defparam \fp_pow_0002:fp_pow_inst|Add42~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~9_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~13_I ( .dataa(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[3] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][19] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~14 )); defparam \fp_pow_0002:fp_pow_inst|Add42~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~13_I .lut_mask = "0000F0F000005555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~17_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][20] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[4] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~18 )); defparam \fp_pow_0002:fp_pow_inst|Add42~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~17_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~21_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][21] ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[5] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~22 )); defparam \fp_pow_0002:fp_pow_inst|Add42~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~21_I .lut_mask = "0000AAAA00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~25_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][22] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[6] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~26 )); defparam \fp_pow_0002:fp_pow_inst|Add42~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~25_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~29_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][23] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[7] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~30 )); defparam \fp_pow_0002:fp_pow_inst|Add42~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~29_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~33_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][24] ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[8] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~34 )); defparam \fp_pow_0002:fp_pow_inst|Add42~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~33_I .lut_mask = "0000CCCC00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~37_I ( .dataa(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[9] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][25] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~38 )); defparam \fp_pow_0002:fp_pow_inst|Add42~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~37_I .lut_mask = "0000F0F000005555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~41_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][26] ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[10] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~42 )); defparam \fp_pow_0002:fp_pow_inst|Add42~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~41_I .lut_mask = "0000CCCC00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~45_I ( .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[11] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][27] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~46 )); defparam \fp_pow_0002:fp_pow_inst|Add42~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~45_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~49_I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[12] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][28] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~50 )); defparam \fp_pow_0002:fp_pow_inst|Add42~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~49_I .lut_mask = "0000F0F000003333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~53_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][29] ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[13] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~54 )); defparam \fp_pow_0002:fp_pow_inst|Add42~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~53_I .lut_mask = "0000FF0000005555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~57_I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[14] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][29] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~57 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~58 )); defparam \fp_pow_0002:fp_pow_inst|Add42~57_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~57_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~57_I .lut_mask = "0000F0F000003333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~57 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~61_I ( .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[15] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][29] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~58 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~62 )); defparam \fp_pow_0002:fp_pow_inst|Add42~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~61_I .lut_mask = "0000FF0000000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~61 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~65_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][29] ), .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[16] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~65 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~66 )); defparam \fp_pow_0002:fp_pow_inst|Add42~65_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~65_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~65_I .lut_mask = "0000AAAA00003333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~65 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~69_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][29] ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[17] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~66 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~69 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~70 )); defparam \fp_pow_0002:fp_pow_inst|Add42~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~69_I .lut_mask = "0000AAAA00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~69 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~73_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][29] ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[18] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~70 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~73 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~74 )); defparam \fp_pow_0002:fp_pow_inst|Add42~73_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~73_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~73_I .lut_mask = "0000AAAA00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~73 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~77_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][29] ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[19] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~74 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~78 )); defparam \fp_pow_0002:fp_pow_inst|Add42~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~77_I .lut_mask = "0000FF0000005555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~77 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~81_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][29] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[20] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~81 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~82 )); defparam \fp_pow_0002:fp_pow_inst|Add42~81_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~81_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~81_I .lut_mask = "0000AAAA000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~81 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~85_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][29] ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[21] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~82 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~85 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~86 )); defparam \fp_pow_0002:fp_pow_inst|Add42~85_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~85_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~85_I .lut_mask = "0000AAAA00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~85 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~89_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][29] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[22] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~86 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~89 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~90 )); defparam \fp_pow_0002:fp_pow_inst|Add42~89_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~89_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~89_I .lut_mask = "0000AAAA000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~89 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~93_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][29] ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[23] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~90 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~93 ), .cout(\fp_pow_0002:fp_pow_inst|Add42~94 )); defparam \fp_pow_0002:fp_pow_inst|Add42~93_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~93_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~93_I .lut_mask = "0000AAAA00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~93 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add42~97_I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC2_uid424_expTabGen_lutmem_dmem|altera_syncram_9sl3:auto_generated|altsyncram_eme4:altsyncram1|__ALT_INV__q_b[23] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid493_pT1_uid429_expPolyEval_cma_s[0][29] ), .cin(\fp_pow_0002:fp_pow_inst|Add42~94 ), .sumout(\fp_pow_0002:fp_pow_inst|Add42~97 )); defparam \fp_pow_0002:fp_pow_inst|Add42~97_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~97_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add42~97_I .lut_mask = "0000F0F000003333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add42~97 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~157 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][2]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][2]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][2]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][2]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][2]~DUPLICATE_I .created_from = "Q(delay_signals[0][2])"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~161 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~165 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~169 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~173 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~177 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][7]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|__ALT_INV__delay_signals[0][7] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][7]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][7]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[1][7] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][7]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~181 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][8]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][8]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][8]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][8]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][8]~DUPLICATE_I .created_from = "Q(delay_signals[0][8])"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][14]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][14]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][14]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][14]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][14]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][14]~DUPLICATE_I .created_from = "Q(delay_signals[0][14])"; cyclonev_mac \fp_pow_0002:fp_pow_inst|Mult13~8_I ( .sub(gnd), .negate(gnd), .ax({\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][25] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][25] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][24] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][23] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][22] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][21] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][20] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][19] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][18] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][17] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][16] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][15] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][14] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][13] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][12] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][11] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][10] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][9] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][8] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][2] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist37|delay_signals[0][0] }), .ay({ay_unconnected_wire_6000,ay_unconnected_wire_6001,ay_unconnected_wire_6002,\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][25] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][24] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][23] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][22] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][21] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][20] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][19] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][18] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][17] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][16] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][15] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][14]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][13] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][12] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][11] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][10] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][9] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][8]~DUPLICATE ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][6] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][5] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][3] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][2]~DUPLICATE }), .clk({clk_unconnected_wire_6003,clk_unconnected_wire_6004,\clk~CLKENA0 }), .aclr({\areset~CLKENA0 ,\areset~CLKENA0 }), .ena({ena_unconnected_wire_6005,ena_unconnected_wire_6006,\vcc }), .resulta({\fp_pow_0002:fp_pow_inst|Mult13~45 ,\fp_pow_0002:fp_pow_inst|Mult13~44 ,\fp_pow_0002:fp_pow_inst|Mult13~43 ,\fp_pow_0002:fp_pow_inst|Mult13~42 ,\fp_pow_0002:fp_pow_inst|Mult13~41 ,\fp_pow_0002:fp_pow_inst|Mult13~40 ,\fp_pow_0002:fp_pow_inst|Mult13~39 , \fp_pow_0002:fp_pow_inst|Mult13~38 ,\fp_pow_0002:fp_pow_inst|Mult13~37 ,\fp_pow_0002:fp_pow_inst|Mult13~36 ,\fp_pow_0002:fp_pow_inst|Mult13~35 ,\fp_pow_0002:fp_pow_inst|Mult13~34 ,\fp_pow_0002:fp_pow_inst|Mult13~33 ,\fp_pow_0002:fp_pow_inst|Mult13~32 , \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][49] ,\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][48] ,\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][47] , \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][46] ,\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][45] ,\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][44] , \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][43] ,\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][42] ,\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][41] , \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][40] ,\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][39] ,\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][38] , \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][37] ,\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][36] ,\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][35] , \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][34] ,\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][33] ,\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][32] , \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][31] ,\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][30] ,\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][29] , \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][28] ,\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][27] ,\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][26] , \fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][25] ,\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][24] ,\fp_pow_0002:fp_pow_inst|Mult13~31 ,\fp_pow_0002:fp_pow_inst|Mult13~30 ,\fp_pow_0002:fp_pow_inst|Mult13~29 , \fp_pow_0002:fp_pow_inst|Mult13~28 ,\fp_pow_0002:fp_pow_inst|Mult13~27 ,\fp_pow_0002:fp_pow_inst|Mult13~26 ,\fp_pow_0002:fp_pow_inst|Mult13~25 ,\fp_pow_0002:fp_pow_inst|Mult13~24 ,\fp_pow_0002:fp_pow_inst|Mult13~23 ,\fp_pow_0002:fp_pow_inst|Mult13~22 , \fp_pow_0002:fp_pow_inst|Mult13~21 ,\fp_pow_0002:fp_pow_inst|Mult13~20 ,\fp_pow_0002:fp_pow_inst|Mult13~19 ,\fp_pow_0002:fp_pow_inst|Mult13~18 ,\fp_pow_0002:fp_pow_inst|Mult13~17 ,\fp_pow_0002:fp_pow_inst|Mult13~16 ,\fp_pow_0002:fp_pow_inst|Mult13~15 , \fp_pow_0002:fp_pow_inst|Mult13~14 ,\fp_pow_0002:fp_pow_inst|Mult13~13 ,\fp_pow_0002:fp_pow_inst|Mult13~12 ,\fp_pow_0002:fp_pow_inst|Mult13~11 ,\fp_pow_0002:fp_pow_inst|Mult13~10 ,\fp_pow_0002:fp_pow_inst|Mult13~9 ,\fp_pow_0002:fp_pow_inst|Mult13~8 })); defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .signed_max = "true"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .signed_may = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .signed_mbx = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .signed_mby = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .preadder_subtract_a = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .preadder_subtract_b = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .ay_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .by_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .delay_scan_out_ay = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .delay_scan_out_by = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .use_chainadder = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .enable_double_accum = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .operation_mode = "M27X27"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .operand_source_max = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .operand_source_may = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .operand_source_mbx = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .operand_source_mby = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .ax_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .ay_scan_in_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .az_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .bx_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .by_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .bz_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .coef_sel_a_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .coef_sel_b_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .sub_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .negate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .accumulate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .load_const_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .output_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .coef_a_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .coef_a_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .coef_a_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .coef_a_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .coef_a_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .coef_a_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .coef_a_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .coef_a_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .coef_b_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .coef_b_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .coef_b_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .coef_b_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .coef_b_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .coef_b_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .coef_b_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .coef_b_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .ax_width = 27; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .ay_scan_in_width = 24; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .mode_sub_location = 0; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .load_const_value = 0; defparam \fp_pow_0002:fp_pow_inst|Mult13~8_I .result_a_width = 64; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist36|delay_signals[0][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][24] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist36|delay_signals[0][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist36|delay_signals[0][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist36|delay_signals[0][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist36|delay_signals[0][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist36|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist36|delay_signals[0][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist36|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist36|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist36|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist36|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][25] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[2][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][1]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[2][1] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][1]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][2]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][2]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[1][2] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[1][5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|delay_signals[0][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[1][6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][7]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist89|__ALT_INV__delay_signals[0][7] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][7]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[2][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[1][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[1][7] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_a_first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_b_first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a0 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[1] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_a_first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_b_first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a1 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[2] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_a_first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_b_first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a2 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[3] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_a_first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_b_first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a3 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[4] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_a_first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_b_first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a4 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[5] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_a_first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_b_first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a5 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[6] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_a_first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_b_first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a6 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[7] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_a_first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_b_first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a7 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[8] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_a_first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_b_first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a8 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[9] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_a_first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_b_first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a9 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[10] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_a_first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_b_first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a10 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[11] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_a_first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_b_first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a11 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[12] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_a_first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_b_first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a12 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[13] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_a_first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_b_first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a13 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[14] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_a_first_bit_number = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_b_first_bit_number = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a14 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[15] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_a_first_bit_number = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_b_first_bit_number = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a15 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[16] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_a_first_bit_number = 16; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_b_first_bit_number = 16; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a16 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[17] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_a_first_bit_number = 17; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_b_first_bit_number = 17; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a17 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[18] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_a_first_bit_number = 18; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_b_first_bit_number = 18; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a18 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[19] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_a_first_bit_number = 19; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_b_first_bit_number = 19; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a19 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[20] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_a_first_bit_number = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_b_first_bit_number = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a20 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[21] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_a_first_bit_number = 21; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_b_first_bit_number = 21; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a21 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[22] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_a_first_bit_number = 22; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_b_first_bit_number = 22; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a22 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[23] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_a_first_bit_number = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_b_first_bit_number = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a23 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[24] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_a_first_bit_number = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_b_first_bit_number = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a24 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[25] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_a_first_bit_number = 25; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_b_first_bit_number = 25; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a25 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[26] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_a_first_bit_number = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_b_first_bit_number = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a26 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[27] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_a_first_bit_number = 27; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_b_first_bit_number = 27; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a27 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[28] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_a_first_bit_number = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_b_first_bit_number = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a28 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[29] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_a_first_bit_number = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_b_first_bit_number = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a29 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[30] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_a_first_bit_number = 30; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_b_first_bit_number = 30; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a30 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[31] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_a_first_bit_number = 31; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_b_first_bit_number = 31; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a31 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[32] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .init_file = "fp_pow_0002_memoryC1_uid422_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_a_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_a_first_bit_number = 32; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_b_logical_ram_width = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_b_first_bit_number = 32; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|ram_block2a32 .port_b_read_during_write_mode = "new_data_no_nbe_read"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~73_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][0] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add43~73 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~74 )); defparam \fp_pow_0002:fp_pow_inst|Add43~73_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~73_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~73_I .lut_mask = "0000CCCC00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~73 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[1] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][26] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~77_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][1] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~74 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~78 )); defparam \fp_pow_0002:fp_pow_inst|Add43~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~77_I .lut_mask = "0000AAAA000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~77 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][2]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[2] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][2]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][2]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][27] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][2]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~81_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][2] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~81 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~82 )); defparam \fp_pow_0002:fp_pow_inst|Add43~81_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~81_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~81_I .lut_mask = "0000CCCC000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~81 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][28] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~85_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][3] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~82 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~85 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~86 )); defparam \fp_pow_0002:fp_pow_inst|Add43~85_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~85_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~85_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~85 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][4]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[4] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][4]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][4]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][4]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][29] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][4]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][4]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~89_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][4] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~86 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~89 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~90 )); defparam \fp_pow_0002:fp_pow_inst|Add43~89_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~89_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~89_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~89 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][5]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][30] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][5]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][5]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][5]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~93_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~90 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~93 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~94 )); defparam \fp_pow_0002:fp_pow_inst|Add43~93_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~93_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~93_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~93 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][6]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][31] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][6]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~97_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][6] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][6] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~94 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~97 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~98 )); defparam \fp_pow_0002:fp_pow_inst|Add43~97_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~97_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~97_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~97 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][32] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][7]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[7] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][7]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~101_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][7] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~98 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~101 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~102 )); defparam \fp_pow_0002:fp_pow_inst|Add43~101_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~101_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~101_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~101 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][8]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[8] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][8]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][8]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][8]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][8]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][8]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][8]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][33] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][8]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][8]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][8]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][8]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][8]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~105_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][8] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][8] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~102 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~105 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~106 )); defparam \fp_pow_0002:fp_pow_inst|Add43~105_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~105_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~105_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~105 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][9]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[9] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][9]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][9]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][9]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][9]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][9]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][9]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][34] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][9]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][9]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][9]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][9]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][9]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~109_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][9] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][9] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~106 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~109 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~110 )); defparam \fp_pow_0002:fp_pow_inst|Add43~109_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~109_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~109_I .lut_mask = "0000F0F000005555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~109 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][35] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][10]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[10] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][10]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][10]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][10]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][10]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][10]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~113_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][10] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][10] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~110 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~113 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~114 )); defparam \fp_pow_0002:fp_pow_inst|Add43~113_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~113_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~113_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~113 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][36] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][11]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[11] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][11]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][11]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][11]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][11]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][11]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~117_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][11] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][11] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~114 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~117 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~118 )); defparam \fp_pow_0002:fp_pow_inst|Add43~117_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~117_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~117_I .lut_mask = "0000AAAA000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~117 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][12]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[12] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][12]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][12]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][12]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][12]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][12]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][37] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~121_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][12] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][12] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~118 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~121 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~122 )); defparam \fp_pow_0002:fp_pow_inst|Add43~121_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~121_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~121_I .lut_mask = "0000F0F000003333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~121 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][13]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[13] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][13]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][13]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][13]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][13]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][13]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][13]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][38] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][13]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][13]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][13]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][13]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][13]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~125_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][13] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][13] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~122 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~125 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~126 )); defparam \fp_pow_0002:fp_pow_inst|Add43~125_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~125_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~125_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~125 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][14]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[14] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][14]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][14]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][14]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][14]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][14]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][39] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~129_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][14] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][14] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~126 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~129 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~130 )); defparam \fp_pow_0002:fp_pow_inst|Add43~129_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~129_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~129_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~129 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][15]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[15] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][15]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][15]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][15]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][15]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][15]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][15]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][40] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][15]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][15]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][15]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][15]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][15]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~133_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][15] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][15] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~130 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~133 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~134 )); defparam \fp_pow_0002:fp_pow_inst|Add43~133_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~133_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~133_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~133 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][41] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][16]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[16] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][16]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][16]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][16]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][16]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][16]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~1_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][16] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][16] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~134 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~1 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~2 )); defparam \fp_pow_0002:fp_pow_inst|Add43~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~1_I .lut_mask = "0000FF0000000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][17]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][42] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][17]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][17]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][17]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][17]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][17]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][17] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][17] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~2 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~6 )); defparam \fp_pow_0002:fp_pow_inst|Add43~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~5_I .lut_mask = "0000AAAA00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][18]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[18] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][18]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][18]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][18]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][18]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][18]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][18]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][43] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][18]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][18]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][18]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][18]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][18]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~9_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][18] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][18] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~10 )); defparam \fp_pow_0002:fp_pow_inst|Add43~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~9_I .lut_mask = "0000F0F000003333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][19]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[19] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][19]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][19]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][19]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][19]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][19]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][44] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~13_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][19] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][19] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~14 )); defparam \fp_pow_0002:fp_pow_inst|Add43~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~13_I .lut_mask = "0000AAAA000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][20]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][45] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][20]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][20]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][20]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][20]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][20]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][20]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[20] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][20]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][20]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][20]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][20]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][20]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~17_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][20] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][20] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~18 )); defparam \fp_pow_0002:fp_pow_inst|Add43~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~17_I .lut_mask = "0000CCCC00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][21]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][46] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][21]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][21]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][21]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][21]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][21]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~21_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][21] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][21] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~22 )); defparam \fp_pow_0002:fp_pow_inst|Add43~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~21_I .lut_mask = "0000F0F000005555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][22]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[22] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][22]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][22]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][22]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][22]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][22]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][47] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~25_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][22] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][22] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~26 )); defparam \fp_pow_0002:fp_pow_inst|Add43~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~25_I .lut_mask = "0000CCCC000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][23]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[23] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][23]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][48] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][23]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][23]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][23]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][23]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][23]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~29_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][23] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][23] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~30 )); defparam \fp_pow_0002:fp_pow_inst|Add43~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~29_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][24]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[24] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][24]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][24]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][24]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][24]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][24]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][24]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__prodXY_uid496_pT2_uid435_expPolyEval_cma_s[0][49] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][24]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][24]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][24]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][24]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][24]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist35|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~33_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][24] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~34 )); defparam \fp_pow_0002:fp_pow_inst|Add43~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~33_I .lut_mask = "0000CCCC000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[25] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][25]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~37_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][25] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~38 )); defparam \fp_pow_0002:fp_pow_inst|Add43~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~37_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][26]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[26] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~41_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][26] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~42 )); defparam \fp_pow_0002:fp_pow_inst|Add43~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~41_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][27]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[27] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][27]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][27]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][27]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][27]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][27]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~45_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][27] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~46 )); defparam \fp_pow_0002:fp_pow_inst|Add43~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~45_I .lut_mask = "0000AAAA000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][28]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[28] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][28]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][28]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][28]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][28]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][28]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~49_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][28] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~50 )); defparam \fp_pow_0002:fp_pow_inst|Add43~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~49_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][29]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[29] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~53_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][29] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~54 )); defparam \fp_pow_0002:fp_pow_inst|Add43~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~53_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][30]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[30] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][30]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][30]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][30]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][30]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][30]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~57_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][30] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~57 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~58 )); defparam \fp_pow_0002:fp_pow_inst|Add43~57_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~57_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~57_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~57 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][31]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|q_b[31] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][31]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~61_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][31] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~58 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~62 )); defparam \fp_pow_0002:fp_pow_inst|Add43~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~61_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~61 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][32]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC1_uid422_expTabGen_lutmem_dmem|altera_syncram_6sl3:auto_generated|altsyncram_bme4:altsyncram1|__ALT_INV__q_b[32] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][32]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][32]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][32]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][32]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][32]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist13|delay_signals[0][32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~65_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][32] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~65 ), .cout(\fp_pow_0002:fp_pow_inst|Add43~66 )); defparam \fp_pow_0002:fp_pow_inst|Add43~65_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~65_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~65_I .lut_mask = "0000CCCC000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~65 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add43~69_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist13|__ALT_INV__delay_signals[0][32] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist35|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add43~66 ), .sumout(\fp_pow_0002:fp_pow_inst|Add43~69 )); defparam \fp_pow_0002:fp_pow_inst|Add43~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add43~69_I .lut_mask = "0000F0F0000000FF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add43~69 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][0]~1_I ( .combout(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][0]~1 )); defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][0]~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][0]~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][0]~1_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][1]~2_I ( .combout(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][1]~2 )); defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][1]~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][1]~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][1]~2_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][2]~3_I ( .combout(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][2]~3 )); defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][2]~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][2]~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][2]~3_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][3]~4_I ( .combout(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][3]~4 )); defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][3]~4_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][3]~4_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][3]~4_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][4]~5_I ( .combout(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][4]~5 )); defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][4]~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][4]~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][4]~5_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][5]~6_I ( .combout(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][5]~6 )); defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][5]~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][5]~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][5]~6_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][6]~7_I ( .combout(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][6]~7 )); defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][6]~7_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][6]~7_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][6]~7_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][7]~8_I ( .combout(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][7]~8 )); defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][7]~8_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][7]~8_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][7]~8_I .lut_mask = "0000000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][8]~9_I ( .combout(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][8]~9 )); defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][8]~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][8]~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][8]~9_I .lut_mask = "0000000000000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~149 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_6007,portadatain_unconnected_wire_6008,portadatain_unconnected_wire_6009,portadatain_unconnected_wire_6010,portadatain_unconnected_wire_6011,portadatain_unconnected_wire_6012,portadatain_unconnected_wire_6013, portadatain_unconnected_wire_6014,portadatain_unconnected_wire_6015,portadatain_unconnected_wire_6016,portadatain_unconnected_wire_6017,portadatain_unconnected_wire_6018,portadatain_unconnected_wire_6019,portadatain_unconnected_wire_6020, portadatain_unconnected_wire_6021,portadatain_unconnected_wire_6022,portadatain_unconnected_wire_6023,portadatain_unconnected_wire_6024,portadatain_unconnected_wire_6025,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][0] }), .portaaddr({portaaddr_unconnected_wire_6026,portaaddr_unconnected_wire_6027,portaaddr_unconnected_wire_6028,portaaddr_unconnected_wire_6029,portaaddr_unconnected_wire_6030,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_6031,portbaddr_unconnected_wire_6032,portbaddr_unconnected_wire_6033,portbaddr_unconnected_wire_6034,portbaddr_unconnected_wire_6035, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add41~153 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist92|delay_signals[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist93|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[1][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist86|delay_signals[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87_inputreg|delay_signals[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_6036,portadatain_unconnected_wire_6037,portadatain_unconnected_wire_6038,portadatain_unconnected_wire_6039,portadatain_unconnected_wire_6040,portadatain_unconnected_wire_6041,portadatain_unconnected_wire_6042, portadatain_unconnected_wire_6043,portadatain_unconnected_wire_6044,portadatain_unconnected_wire_6045,portadatain_unconnected_wire_6046,portadatain_unconnected_wire_6047,portadatain_unconnected_wire_6048,portadatain_unconnected_wire_6049, portadatain_unconnected_wire_6050,portadatain_unconnected_wire_6051,portadatain_unconnected_wire_6052,portadatain_unconnected_wire_6053,portadatain_unconnected_wire_6054,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][1] }), .portaaddr({portaaddr_unconnected_wire_6055,portaaddr_unconnected_wire_6056,portaaddr_unconnected_wire_6057,portaaddr_unconnected_wire_6058,portaaddr_unconnected_wire_6059,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_6060,portbaddr_unconnected_wire_6061,portbaddr_unconnected_wire_6062,portbaddr_unconnected_wire_6063,portbaddr_unconnected_wire_6064, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[1] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1 .first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama1 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_6065,portadatain_unconnected_wire_6066,portadatain_unconnected_wire_6067,portadatain_unconnected_wire_6068,portadatain_unconnected_wire_6069,portadatain_unconnected_wire_6070,portadatain_unconnected_wire_6071, portadatain_unconnected_wire_6072,portadatain_unconnected_wire_6073,portadatain_unconnected_wire_6074,portadatain_unconnected_wire_6075,portadatain_unconnected_wire_6076,portadatain_unconnected_wire_6077,portadatain_unconnected_wire_6078, portadatain_unconnected_wire_6079,portadatain_unconnected_wire_6080,portadatain_unconnected_wire_6081,portadatain_unconnected_wire_6082,portadatain_unconnected_wire_6083,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][2] }), .portaaddr({portaaddr_unconnected_wire_6084,portaaddr_unconnected_wire_6085,portaaddr_unconnected_wire_6086,portaaddr_unconnected_wire_6087,portaaddr_unconnected_wire_6088,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_6089,portbaddr_unconnected_wire_6090,portbaddr_unconnected_wire_6091,portbaddr_unconnected_wire_6092,portbaddr_unconnected_wire_6093, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[2] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2 .first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama2 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_6094,portadatain_unconnected_wire_6095,portadatain_unconnected_wire_6096,portadatain_unconnected_wire_6097,portadatain_unconnected_wire_6098,portadatain_unconnected_wire_6099,portadatain_unconnected_wire_6100, portadatain_unconnected_wire_6101,portadatain_unconnected_wire_6102,portadatain_unconnected_wire_6103,portadatain_unconnected_wire_6104,portadatain_unconnected_wire_6105,portadatain_unconnected_wire_6106,portadatain_unconnected_wire_6107, portadatain_unconnected_wire_6108,portadatain_unconnected_wire_6109,portadatain_unconnected_wire_6110,portadatain_unconnected_wire_6111,portadatain_unconnected_wire_6112,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][3] }), .portaaddr({portaaddr_unconnected_wire_6113,portaaddr_unconnected_wire_6114,portaaddr_unconnected_wire_6115,portaaddr_unconnected_wire_6116,portaaddr_unconnected_wire_6117,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_6118,portbaddr_unconnected_wire_6119,portbaddr_unconnected_wire_6120,portbaddr_unconnected_wire_6121,portbaddr_unconnected_wire_6122, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[3] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3 .first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama3 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_6123,portadatain_unconnected_wire_6124,portadatain_unconnected_wire_6125,portadatain_unconnected_wire_6126,portadatain_unconnected_wire_6127,portadatain_unconnected_wire_6128,portadatain_unconnected_wire_6129, portadatain_unconnected_wire_6130,portadatain_unconnected_wire_6131,portadatain_unconnected_wire_6132,portadatain_unconnected_wire_6133,portadatain_unconnected_wire_6134,portadatain_unconnected_wire_6135,portadatain_unconnected_wire_6136, portadatain_unconnected_wire_6137,portadatain_unconnected_wire_6138,portadatain_unconnected_wire_6139,portadatain_unconnected_wire_6140,portadatain_unconnected_wire_6141,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][4] }), .portaaddr({portaaddr_unconnected_wire_6142,portaaddr_unconnected_wire_6143,portaaddr_unconnected_wire_6144,portaaddr_unconnected_wire_6145,portaaddr_unconnected_wire_6146,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_6147,portbaddr_unconnected_wire_6148,portbaddr_unconnected_wire_6149,portbaddr_unconnected_wire_6150,portbaddr_unconnected_wire_6151, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[4] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4 .first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama4 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_6152,portadatain_unconnected_wire_6153,portadatain_unconnected_wire_6154,portadatain_unconnected_wire_6155,portadatain_unconnected_wire_6156,portadatain_unconnected_wire_6157,portadatain_unconnected_wire_6158, portadatain_unconnected_wire_6159,portadatain_unconnected_wire_6160,portadatain_unconnected_wire_6161,portadatain_unconnected_wire_6162,portadatain_unconnected_wire_6163,portadatain_unconnected_wire_6164,portadatain_unconnected_wire_6165, portadatain_unconnected_wire_6166,portadatain_unconnected_wire_6167,portadatain_unconnected_wire_6168,portadatain_unconnected_wire_6169,portadatain_unconnected_wire_6170,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][5] }), .portaaddr({portaaddr_unconnected_wire_6171,portaaddr_unconnected_wire_6172,portaaddr_unconnected_wire_6173,portaaddr_unconnected_wire_6174,portaaddr_unconnected_wire_6175,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_6176,portbaddr_unconnected_wire_6177,portbaddr_unconnected_wire_6178,portbaddr_unconnected_wire_6179,portbaddr_unconnected_wire_6180, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[5] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5 .first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama5 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][6]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][6]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_6181,portadatain_unconnected_wire_6182,portadatain_unconnected_wire_6183,portadatain_unconnected_wire_6184,portadatain_unconnected_wire_6185,portadatain_unconnected_wire_6186,portadatain_unconnected_wire_6187, portadatain_unconnected_wire_6188,portadatain_unconnected_wire_6189,portadatain_unconnected_wire_6190,portadatain_unconnected_wire_6191,portadatain_unconnected_wire_6192,portadatain_unconnected_wire_6193,portadatain_unconnected_wire_6194, portadatain_unconnected_wire_6195,portadatain_unconnected_wire_6196,portadatain_unconnected_wire_6197,portadatain_unconnected_wire_6198,portadatain_unconnected_wire_6199,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][6] }), .portaaddr({portaaddr_unconnected_wire_6200,portaaddr_unconnected_wire_6201,portaaddr_unconnected_wire_6202,portaaddr_unconnected_wire_6203,portaaddr_unconnected_wire_6204,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_6205,portbaddr_unconnected_wire_6206,portbaddr_unconnected_wire_6207,portbaddr_unconnected_wire_6208,portbaddr_unconnected_wire_6209, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[6] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6 .first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama6 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_6210,portadatain_unconnected_wire_6211,portadatain_unconnected_wire_6212,portadatain_unconnected_wire_6213,portadatain_unconnected_wire_6214,portadatain_unconnected_wire_6215,portadatain_unconnected_wire_6216, portadatain_unconnected_wire_6217,portadatain_unconnected_wire_6218,portadatain_unconnected_wire_6219,portadatain_unconnected_wire_6220,portadatain_unconnected_wire_6221,portadatain_unconnected_wire_6222,portadatain_unconnected_wire_6223, portadatain_unconnected_wire_6224,portadatain_unconnected_wire_6225,portadatain_unconnected_wire_6226,portadatain_unconnected_wire_6227,portadatain_unconnected_wire_6228,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][7] }), .portaaddr({portaaddr_unconnected_wire_6229,portaaddr_unconnected_wire_6230,portaaddr_unconnected_wire_6231,portaaddr_unconnected_wire_6232,portaaddr_unconnected_wire_6233,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_6234,portbaddr_unconnected_wire_6235,portbaddr_unconnected_wire_6236,portbaddr_unconnected_wire_6237,portbaddr_unconnected_wire_6238, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[7] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7 .first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama7 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[1][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist87|delay_signals[0][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist88_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_6239,portadatain_unconnected_wire_6240,portadatain_unconnected_wire_6241,portadatain_unconnected_wire_6242,portadatain_unconnected_wire_6243,portadatain_unconnected_wire_6244,portadatain_unconnected_wire_6245, portadatain_unconnected_wire_6246,portadatain_unconnected_wire_6247,portadatain_unconnected_wire_6248,portadatain_unconnected_wire_6249,portadatain_unconnected_wire_6250,portadatain_unconnected_wire_6251,portadatain_unconnected_wire_6252, portadatain_unconnected_wire_6253,portadatain_unconnected_wire_6254,portadatain_unconnected_wire_6255,portadatain_unconnected_wire_6256,portadatain_unconnected_wire_6257,\fp_pow_0002:fp_pow_inst|dspba_delay:redist88_inputreg|delay_signals[0][8] }), .portaaddr({portaaddr_unconnected_wire_6258,portaaddr_unconnected_wire_6259,portaaddr_unconnected_wire_6260,portaaddr_unconnected_wire_6261,portaaddr_unconnected_wire_6262,\fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_6263,portbaddr_unconnected_wire_6264,portbaddr_unconnected_wire_6265,portbaddr_unconnected_wire_6266,portbaddr_unconnected_wire_6267, \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[8] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8 .logical_ram_depth = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8 .logical_ram_width = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8 .address_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8 .first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8 .last_address = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|lutrama8 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_mac \fp_pow_0002:fp_pow_inst|Add44~8_I ( .sub(gnd), .negate(gnd), .ax({ax_unconnected_wire_6268,ax_unconnected_wire_6269,ax_unconnected_wire_6270,ax_unconnected_wire_6271,ax_unconnected_wire_6272,ax_unconnected_wire_6273,ax_unconnected_wire_6274,ax_unconnected_wire_6275,ax_unconnected_wire_6276, \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_c0[1][17]~0 ,\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[25] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[24] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[23] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[22] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[21] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[20] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[19] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[18] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[17] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[16] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[15] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[14] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[13] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[12] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[11] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[10] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[9] }), .ay({ay_unconnected_wire_6277,ay_unconnected_wire_6278,ay_unconnected_wire_6279,ay_unconnected_wire_6280,ay_unconnected_wire_6281,ay_unconnected_wire_6282,ay_unconnected_wire_6283,ay_unconnected_wire_6284,ay_unconnected_wire_6285, \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][16] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][15] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][14] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][13] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][12] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][11] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][10] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][9] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][8] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][0] ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[1][0]~0 }), .bx({\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][34] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][33] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][32] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][31] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][30] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][29] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][28] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][27] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][26] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][25] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][24] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][23] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][22] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][21] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][20] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][19] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][18] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][17] }), .by({by_unconnected_wire_6286,\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[8] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[7] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[6] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[5] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[0] ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][8]~9 , \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][7]~8 ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][6]~7 ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][5]~6 , \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][4]~5 ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][3]~4 ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][2]~3 , \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][1]~2 ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_a0[0][0]~1 }), .clk({clk_unconnected_wire_6287,clk_unconnected_wire_6288,\clk~CLKENA0 }), .aclr({\areset~CLKENA0 ,\areset~CLKENA0 }), .ena({ena_unconnected_wire_6289,ena_unconnected_wire_6290,\vcc }), .resulta({\fp_pow_0002:fp_pow_inst|Add44~46 ,\fp_pow_0002:fp_pow_inst|Add44~45 ,\fp_pow_0002:fp_pow_inst|Add44~44 ,\fp_pow_0002:fp_pow_inst|Add44~43 ,\fp_pow_0002:fp_pow_inst|Add44~42 ,\fp_pow_0002:fp_pow_inst|Add44~41 ,\fp_pow_0002:fp_pow_inst|Add44~40 , \fp_pow_0002:fp_pow_inst|Add44~39 ,\fp_pow_0002:fp_pow_inst|Add44~38 ,\fp_pow_0002:fp_pow_inst|Add44~37 ,\fp_pow_0002:fp_pow_inst|Add44~36 ,\fp_pow_0002:fp_pow_inst|Add44~35 ,\fp_pow_0002:fp_pow_inst|Add44~34 ,\fp_pow_0002:fp_pow_inst|Add44~33 , \fp_pow_0002:fp_pow_inst|Add44~32 ,\fp_pow_0002:fp_pow_inst|Add44~31 ,\fp_pow_0002:fp_pow_inst|Add44~30 ,\fp_pow_0002:fp_pow_inst|Add44~29 ,\fp_pow_0002:fp_pow_inst|Add44~28 ,\fp_pow_0002:fp_pow_inst|Add44~27 ,\fp_pow_0002:fp_pow_inst|Add44~26 , \fp_pow_0002:fp_pow_inst|Add44~25 ,\fp_pow_0002:fp_pow_inst|Add44~24 ,\fp_pow_0002:fp_pow_inst|Add44~23 ,\fp_pow_0002:fp_pow_inst|Add44~22 ,\fp_pow_0002:fp_pow_inst|Add44~21 ,\fp_pow_0002:fp_pow_inst|Add44~20 , \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][36] ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][35] ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][34] , \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][33] ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][32] ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][31] , \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][30] ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][29] ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][28] , \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][27] ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][26] ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][25] , \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][24] ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][23] ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][22] , \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][21] ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][20] ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][19] , \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][18] ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][17] ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][16] , \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][15] ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][14] ,\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][13] , \fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][12] ,\fp_pow_0002:fp_pow_inst|Add44~19 ,\fp_pow_0002:fp_pow_inst|Add44~18 ,\fp_pow_0002:fp_pow_inst|Add44~17 ,\fp_pow_0002:fp_pow_inst|Add44~16 ,\fp_pow_0002:fp_pow_inst|Add44~15 , \fp_pow_0002:fp_pow_inst|Add44~14 ,\fp_pow_0002:fp_pow_inst|Add44~13 ,\fp_pow_0002:fp_pow_inst|Add44~12 ,\fp_pow_0002:fp_pow_inst|Add44~11 ,\fp_pow_0002:fp_pow_inst|Add44~10 ,\fp_pow_0002:fp_pow_inst|Add44~9 ,\fp_pow_0002:fp_pow_inst|Add44~8 })); defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .signed_max = "true"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .signed_may = "false"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .signed_mbx = "true"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .signed_mby = "false"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .preadder_subtract_a = "false"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .preadder_subtract_b = "false"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .ay_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .by_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .delay_scan_out_ay = "false"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .delay_scan_out_by = "false"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .use_chainadder = "false"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .enable_double_accum = "false"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .operation_mode = "M18X18_SUMOF2"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .operand_source_max = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .operand_source_may = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .operand_source_mbx = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .operand_source_mby = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .ax_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .ay_scan_in_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .az_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .bx_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .by_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .bz_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .coef_sel_a_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .coef_sel_b_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .sub_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .negate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .accumulate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .load_const_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .output_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .coef_a_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .coef_a_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .coef_a_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .coef_a_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .coef_a_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .coef_a_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .coef_a_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .coef_a_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .coef_b_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .coef_b_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .coef_b_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .coef_b_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .coef_b_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .coef_b_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .coef_b_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .coef_b_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .ax_width = 18; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .ay_scan_in_width = 18; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .bx_width = 18; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .by_width = 18; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .mode_sub_location = 0; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .load_const_value = 0; defparam \fp_pow_0002:fp_pow_inst|Add44~8_I .result_a_width = 64; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][24]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][36] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][24]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][24]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][24]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][24]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][24]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_a0[0][17]~0_I ( .combout(\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_a0[0][17]~0 )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_a0[0][17]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_a0[0][17]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_a0[0][17]~0_I .lut_mask = "0000000000000000"; cyclonev_mac \fp_pow_0002:fp_pow_inst|Mult16~mac ( .sub(gnd), .negate(gnd), .ax({ax_unconnected_wire_6291,ax_unconnected_wire_6292,ax_unconnected_wire_6293,ax_unconnected_wire_6294,ax_unconnected_wire_6295,ax_unconnected_wire_6296,ax_unconnected_wire_6297,ax_unconnected_wire_6298,ax_unconnected_wire_6299, \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][34] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][33] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][32] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][31] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][30] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][29] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][28] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][27] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][26] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][25] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][24] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][23] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][22] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][21] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][20] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][19] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][18] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][17] }), .ay({ay_unconnected_wire_6300,ay_unconnected_wire_6301,ay_unconnected_wire_6302,ay_unconnected_wire_6303,ay_unconnected_wire_6304,ay_unconnected_wire_6305,ay_unconnected_wire_6306,ay_unconnected_wire_6307, \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_a0[0][17]~0 ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_a0[0][17]~0 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[25] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[24] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[23] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[22] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[21] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[20] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[19] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[18] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[17] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[16] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[15] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[14] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[13] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[12] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[11] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[10] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[9] }), .clk({clk_unconnected_wire_6308,clk_unconnected_wire_6309,\clk~CLKENA0 }), .aclr({\areset~CLKENA0 ,\areset~CLKENA0 }), .ena({ena_unconnected_wire_6310,ena_unconnected_wire_6311,\vcc }), .resulta({\fp_pow_0002:fp_pow_inst|Mult16~35 ,\fp_pow_0002:fp_pow_inst|Mult16~34 ,\fp_pow_0002:fp_pow_inst|Mult16~33 ,\fp_pow_0002:fp_pow_inst|Mult16~32 ,\fp_pow_0002:fp_pow_inst|Mult16~31 ,\fp_pow_0002:fp_pow_inst|Mult16~30 ,\fp_pow_0002:fp_pow_inst|Mult16~29 , \fp_pow_0002:fp_pow_inst|Mult16~28 ,\fp_pow_0002:fp_pow_inst|Mult16~27 ,\fp_pow_0002:fp_pow_inst|Mult16~26 ,\fp_pow_0002:fp_pow_inst|Mult16~25 ,\fp_pow_0002:fp_pow_inst|Mult16~24 ,\fp_pow_0002:fp_pow_inst|Mult16~23 ,\fp_pow_0002:fp_pow_inst|Mult16~22 , \fp_pow_0002:fp_pow_inst|Mult16~21 ,\fp_pow_0002:fp_pow_inst|Mult16~20 ,\fp_pow_0002:fp_pow_inst|Mult16~19 ,\fp_pow_0002:fp_pow_inst|Mult16~18 ,\fp_pow_0002:fp_pow_inst|Mult16~17 ,\fp_pow_0002:fp_pow_inst|Mult16~16 ,\fp_pow_0002:fp_pow_inst|Mult16~15 , \fp_pow_0002:fp_pow_inst|Mult16~14 ,\fp_pow_0002:fp_pow_inst|Mult16~13 ,\fp_pow_0002:fp_pow_inst|Mult16~12 ,\fp_pow_0002:fp_pow_inst|Mult16~11 ,\fp_pow_0002:fp_pow_inst|Mult16~10 ,\fp_pow_0002:fp_pow_inst|Mult16~9 ,\fp_pow_0002:fp_pow_inst|Mult16~8 , \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_p[0][35] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][34] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][33] , \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][32] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][31] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][30] , \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][29] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][28] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][27] , \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][26] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][25] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][24] , \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][23] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][22] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][21] , \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][20] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][19] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][18] , \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][17] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][16] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][15] , \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][14] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][13] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][12] , \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][11] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][10] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][9] , \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][8] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][7] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][6] , \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][5] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][4] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][3] , \fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][2] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][1] ,\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][0] })); defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .signed_max = "true"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .signed_may = "true"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .signed_mbx = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .signed_mby = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .preadder_subtract_a = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .preadder_subtract_b = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .ay_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .by_use_scan_in = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .delay_scan_out_ay = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .delay_scan_out_by = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .use_chainadder = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .enable_double_accum = "false"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .operation_mode = "M18X18_FULL"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .operand_source_max = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .operand_source_may = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .operand_source_mbx = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .operand_source_mby = "INPUT"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .ax_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .ay_scan_in_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .az_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .bx_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .by_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .bz_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .coef_sel_a_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .coef_sel_b_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .sub_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .negate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .accumulate_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .load_const_clock = "NONE"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .output_clock = "0"; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .coef_a_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .coef_a_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .coef_a_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .coef_a_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .coef_a_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .coef_a_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .coef_a_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .coef_a_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .coef_b_0 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .coef_b_1 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .coef_b_2 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .coef_b_3 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .coef_b_4 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .coef_b_5 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .coef_b_6 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .coef_b_7 = 0; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .ax_width = 18; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .ay_scan_in_width = 19; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .mode_sub_location = 0; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .load_const_value = 0; defparam \fp_pow_0002:fp_pow_inst|Mult16~mac .result_a_width = 64; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][40]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][34] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][40]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][40]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][40]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][40]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][40]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][40]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][40] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][40]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][40]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][39]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][33] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][39]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][39]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][39]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][39]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][39]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][39]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][39] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][39]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][38]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][32] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][38]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][38]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][38]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][38]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][38]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][38]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][38] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][38]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][37]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][31] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][37]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][37]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][37]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][37]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][37]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][37]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][37] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][37]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][36]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][30] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][36] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][36]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][35]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][29] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][35]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][35]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][35]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][35]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][35]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][35]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][34]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][28] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][34]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][34]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][34]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][34]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][34]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][33]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][27] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][33]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][33]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][33]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][33]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][33]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][33]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][26] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][32]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][31]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][25] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][31]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][31]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][31]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][31]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][31]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][31]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][24] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][30]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][23] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][29]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][28]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][22] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][28]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][28]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][28]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][28]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][28]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][28]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][27]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][26]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][20] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][26]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][26]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][26]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][26]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][26]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][25]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][19] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][25]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][25]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][25]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][25]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][25]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][24]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][23]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][35] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][23]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][23]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][23]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][23]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][23]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][23]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][17] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][23]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][23]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][23]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][23]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][23]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][22]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][34] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][22]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][22]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][22]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][22]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][22]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][21]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][15] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][21]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][21]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][21]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][21]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][21]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][33] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][20]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][32] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][20]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][20]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][20]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][20]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][20]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][20]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][14] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][20]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][20]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][20]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][20]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][20]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][19]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][31] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][19]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][19]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][19]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][19]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][19]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][30] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][17]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][11] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][17]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][17]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][17]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][17]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][17]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][17]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][29] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][17]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][17]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][17]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][17]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][17]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][16]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][10] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][16]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][16]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][16]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][16]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][16]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][28] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][27] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][26] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][13]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][7] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][13]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][13]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][13]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][13]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][13]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][25] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][12]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][24] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][12]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][12]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][12]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][12]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][12]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][11]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][11]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][11]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][11]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][11]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][11]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][23] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][22] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][9]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][21] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][9]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][9]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][9]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][9]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][9]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][9]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][9]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][9]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][9]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][9]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][9]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][8]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][20] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][8]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][8]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][8]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][8]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][8]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][8]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][8]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][8]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][8]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][8]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][8]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][7]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][19] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][7]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][7]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][7]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid527_pT3_uid441_expPolyEval_cma_s[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_b0[1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_b0[1] )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_b0[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_b0[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_a0[2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_a0[2] )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_a0[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_a0[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[1][2]~I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_b0[1] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_a0[2] ), .combout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[1][2] )); defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[1][2]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[1][2]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[1][2]~I .lut_mask = "0000000055555555"; dffeas \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_b0[0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][14] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_b0[0] )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_b0[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_b0[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[0][2]~I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_b0[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_a0[2] ), .combout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[0][2] )); defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[0][2]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[0][2]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[0][2]~I .lut_mask = "0033003300330033"; dffeas \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_a0[1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_a0[1] )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_a0[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_a0[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[1][1]~I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_b0[1] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_a0[1] ), .combout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[1][1] )); defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[1][1]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[1][1]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[1][1]~I .lut_mask = "0000000000FF00FF"; dffeas \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_a0[0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist88_replace_mem_dmem|altera_syncram_sdg3:auto_generated|altsyncram_nmb4:altsyncram1|dataout_reg[6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_a0[0] )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_a0[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_a0[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[1][0]~I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_b0[1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_a0[0] ), .combout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[1][0] )); defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[1][0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[1][0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[1][0]~I .lut_mask = "000F000F000F000F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[0][1]~I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_b0[0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_a0[1] ), .combout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[0][1] )); defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[0][1]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[0][1]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[0][1]~I .lut_mask = "0000000000FF00FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~13_I ( .datab(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[1][0] ), .datac(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[0][1] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~13 ), .cout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~14 )); defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~13_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~9_I ( .datac(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[1][1] ), .cin(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~14 ), .sumout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~9 ), .cout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~10 )); defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~9_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~5_I ( .datac(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[1][2] ), .cin(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~10 ), .sumout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~5 ), .cout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~6 )); defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~5_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~1_I ( .cin(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~6 ), .sumout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~1 )); defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~1_I .lut_mask = "0000FFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_b0[2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist34|delay_signals[0][16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_b0[2] )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_b0[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_b0[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[2][2]~I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_a0[2] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_b0[2] ), .combout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[2][2] )); defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[2][2]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[2][2]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[2][2]~I .lut_mask = "000000000F0F0F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[2][1]~I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_a0[1] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_b0[2] ), .combout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[2][1] )); defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[2][1]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[2][1]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[2][1]~I .lut_mask = "0000000000FF00FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[2][0]~I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_a0[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_b0[2] ), .combout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[2][0] )); defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[2][0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[2][0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[2][0]~I .lut_mask = "000F000F000F000F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~13_I ( .dataa(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[2][0] ), .datac(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|__ALT_INV__op_1~9 ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~13 ), .cout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~14 )); defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~13_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~9_I ( .datac(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|__ALT_INV__op_1~5 ), .dataf(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[2][1] ), .cin(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~14 ), .sumout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~9 ), .cout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~10 )); defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~9_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~5_I ( .datab(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|__ALT_INV__op_1~1 ), .datac(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|__ALT_INV__decoder_node[2][2] ), .cin(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~10 ), .sumout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~5 ), .cout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~6 )); defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~5_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~1_I ( .cin(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~6 ), .sumout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~1 )); defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~1_I .lut_mask = "0000FFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[5] )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][5]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_s1[5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][5]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[4] )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[3] )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_s1[3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_54h:auto_generated|op_1~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[2] )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][2]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_s1[2] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][2]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][14] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_44h:auto_generated|op_1~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[1] )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[0][0]~I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_b0[0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_a0[0] ), .combout(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[0][0] )); defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[0][0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[0][0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[0][0]~I .lut_mask = "0303030303030303"; dffeas \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|lpm_mult:Mult17|multcore:mult_core|decoder_node[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[0] )); defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|sm0_uid530_pT3_uid441_expPolyEval_s1[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__sm0_uid530_pT3_uid441_expPolyEval_s1[0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][0]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist28|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|multSumOfTwoTS_uid528_pT3_uid441_expPolyEval_cma_s[0][12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist26|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~162_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][0] ), .cin(gnd), .cout(\fp_pow_0002:fp_pow_inst|Add45~162 )); defparam \fp_pow_0002:fp_pow_inst|Add45~162_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~162_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~162_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~158_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][1] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][1] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~162 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~158 )); defparam \fp_pow_0002:fp_pow_inst|Add45~158_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~158_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~158_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~154_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][2] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~158 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~154 )); defparam \fp_pow_0002:fp_pow_inst|Add45~154_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~154_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~154_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~150_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][3] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~154 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~150 )); defparam \fp_pow_0002:fp_pow_inst|Add45~150_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~150_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~150_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~146_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][4] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~150 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~146 )); defparam \fp_pow_0002:fp_pow_inst|Add45~146_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~146_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~146_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~142_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~146 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~142 )); defparam \fp_pow_0002:fp_pow_inst|Add45~142_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~142_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~142_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~138_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][6] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][6] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~142 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~138 )); defparam \fp_pow_0002:fp_pow_inst|Add45~138_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~138_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~138_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~133_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][7] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~138 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~133 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~134 )); defparam \fp_pow_0002:fp_pow_inst|Add45~133_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~133_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~133_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~129_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][8] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][8] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~134 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~129 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~130 )); defparam \fp_pow_0002:fp_pow_inst|Add45~129_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~129_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~129_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~125_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][9] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][9] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~130 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~125 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~126 )); defparam \fp_pow_0002:fp_pow_inst|Add45~125_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~125_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~125_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~121_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][10] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][10] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~126 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~121 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~122 )); defparam \fp_pow_0002:fp_pow_inst|Add45~121_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~121_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~121_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~117_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][11] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][11] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~122 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~117 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~118 )); defparam \fp_pow_0002:fp_pow_inst|Add45~117_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~117_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~117_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~113_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][12] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][12] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~118 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~113 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~114 )); defparam \fp_pow_0002:fp_pow_inst|Add45~113_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~113_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~113_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~109_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][13] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][13] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~114 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~109 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~110 )); defparam \fp_pow_0002:fp_pow_inst|Add45~109_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~109_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~109_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~105_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][14] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][14] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~110 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~105 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~106 )); defparam \fp_pow_0002:fp_pow_inst|Add45~105_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~105_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~105_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~101_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][15] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][15] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~106 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~101 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~102 )); defparam \fp_pow_0002:fp_pow_inst|Add45~101_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~101_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~101_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~97_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][16] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][16] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~102 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~97 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~98 )); defparam \fp_pow_0002:fp_pow_inst|Add45~97_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~97_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~97_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~93_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][17] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][17] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~98 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~93 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~94 )); defparam \fp_pow_0002:fp_pow_inst|Add45~93_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~93_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~93_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~89_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][18] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][18] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~94 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~89 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~90 )); defparam \fp_pow_0002:fp_pow_inst|Add45~89_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~89_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~89_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~85_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][19] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][19] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~90 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~85 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~86 )); defparam \fp_pow_0002:fp_pow_inst|Add45~85_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~85_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~85_I .lut_mask = "0000FF0000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~81_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][20] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][20] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~86 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~81 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~82 )); defparam \fp_pow_0002:fp_pow_inst|Add45~81_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~81_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~81_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~77_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][21] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][21] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~82 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~78 )); defparam \fp_pow_0002:fp_pow_inst|Add45~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~77_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~1_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][22] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][22] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~1 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~2 )); defparam \fp_pow_0002:fp_pow_inst|Add45~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~1_I .lut_mask = "0000FF00000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~5_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][23] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][23] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~2 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~6 )); defparam \fp_pow_0002:fp_pow_inst|Add45~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~5_I .lut_mask = "0000AAAA00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~9_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][24] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~10 )); defparam \fp_pow_0002:fp_pow_inst|Add45~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~9_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~13_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][25] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~14 )); defparam \fp_pow_0002:fp_pow_inst|Add45~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~13_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~17_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][24] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][26] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~18 )); defparam \fp_pow_0002:fp_pow_inst|Add45~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~17_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~21_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][24] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][27] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~22 )); defparam \fp_pow_0002:fp_pow_inst|Add45~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~21_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~25_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][24] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][28] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~26 )); defparam \fp_pow_0002:fp_pow_inst|Add45~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~25_I .lut_mask = "0000FF0000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~29_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][24] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][29] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~30 )); defparam \fp_pow_0002:fp_pow_inst|Add45~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~29_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~33_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][30] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~34 )); defparam \fp_pow_0002:fp_pow_inst|Add45~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~33_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~37_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][24] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][31] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~38 )); defparam \fp_pow_0002:fp_pow_inst|Add45~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~37_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~41_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][32] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~42 )); defparam \fp_pow_0002:fp_pow_inst|Add45~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~41_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~45_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][33] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~46 )); defparam \fp_pow_0002:fp_pow_inst|Add45~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~45_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~49_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][24] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][34] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~50 )); defparam \fp_pow_0002:fp_pow_inst|Add45~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~49_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~53_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][24] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][35] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~54 )); defparam \fp_pow_0002:fp_pow_inst|Add45~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~53_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~57_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][24] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][36] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~57 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~58 )); defparam \fp_pow_0002:fp_pow_inst|Add45~57_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~57_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~57_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~61_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][24] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][37] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~58 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~62 )); defparam \fp_pow_0002:fp_pow_inst|Add45~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~61_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~65_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][38] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~65 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~66 )); defparam \fp_pow_0002:fp_pow_inst|Add45~65_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~65_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~65_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~69_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][24] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][39] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~66 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~69 ), .cout(\fp_pow_0002:fp_pow_inst|Add45~70 )); defparam \fp_pow_0002:fp_pow_inst|Add45~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~69_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add45~73_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist26|__ALT_INV__delay_signals[0][24] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist28|__ALT_INV__delay_signals[0][40] ), .cin(\fp_pow_0002:fp_pow_inst|Add45~70 ), .sumout(\fp_pow_0002:fp_pow_inst|Add45~73 )); defparam \fp_pow_0002:fp_pow_inst|Add45~73_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~73_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add45~73_I .lut_mask = "0000AAAA00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~73 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][35]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][0]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][0]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][1]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[2][1] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][1]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][2]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][2]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][2]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][2]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][2]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[2][2] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][2]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[0][2] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][3]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][3]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][3]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[2][3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][3]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|delay_signals[0][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][4]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|__ALT_INV__delay_signals[0][4] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][4]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][4]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][4]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[1][4] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][4]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][4]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][5]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[0][5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][5]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][5]~feeder_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|__ALT_INV__delay_signals[0][5] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][5]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][5]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][5]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][5]~feeder_I .lut_mask = "5555555555555555"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][5]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][6]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][6]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][6]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][6]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|__ALT_INV__delay_signals[0][6] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][7]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist90|__ALT_INV__delay_signals[0][7] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][7]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][7]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][7]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][7]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][7]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_inputreg|delay_signals[0][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[2][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[1][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91|delay_signals[0][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_a_first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_b_first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a0 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[1] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_a_first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_b_first_bit_number = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a1 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[2] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_a_first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_b_first_bit_number = 2; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a2 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[3] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_a_first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_b_first_bit_number = 3; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a3 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[4] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_a_first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_b_first_bit_number = 4; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a4 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[5] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_a_first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_b_first_bit_number = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a5 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[6] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_a_first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_b_first_bit_number = 6; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a6 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[7] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_a_first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_b_first_bit_number = 7; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a7 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[8] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_a_first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_b_first_bit_number = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a8 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[9] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_a_first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_b_first_bit_number = 9; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a9 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[10] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_a_first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_b_first_bit_number = 10; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a10 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[11] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_a_first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_b_first_bit_number = 11; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a11 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[12] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_a_first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_b_first_bit_number = 12; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a12 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[13] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_a_first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_b_first_bit_number = 13; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a13 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[14] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_a_first_bit_number = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_b_first_bit_number = 14; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a14 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[15] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_a_first_bit_number = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_b_first_bit_number = 15; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a15 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[16] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_a_first_bit_number = 16; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_b_first_bit_number = 16; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a16 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[17] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_a_first_bit_number = 17; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_b_first_bit_number = 17; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a17 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[18] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_a_first_bit_number = 18; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_b_first_bit_number = 18; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a18 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[19] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_a_first_bit_number = 19; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_b_first_bit_number = 19; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a19 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[20] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_a_first_bit_number = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_b_first_bit_number = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a20 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[21] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_a_first_bit_number = 21; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_b_first_bit_number = 21; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a21 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[22] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_a_first_bit_number = 22; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_b_first_bit_number = 22; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a22 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[23] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_a_first_bit_number = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_b_first_bit_number = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a23 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[24] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_a_first_bit_number = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_b_first_bit_number = 24; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a24 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[25] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_a_first_bit_number = 25; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_b_first_bit_number = 25; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a25 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[26] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_a_first_bit_number = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_b_first_bit_number = 26; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a26 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[27] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_a_first_bit_number = 27; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_b_first_bit_number = 27; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a27 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[28] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_a_first_bit_number = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_b_first_bit_number = 28; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a28 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[29] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_a_first_bit_number = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_b_first_bit_number = 29; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a29 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[30] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_a_first_bit_number = 30; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_b_first_bit_number = 30; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a30 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[31] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_a_first_bit_number = 31; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_b_first_bit_number = 31; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a31 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[32] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_a_first_bit_number = 32; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_b_first_bit_number = 32; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a32 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[33] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_a_first_bit_number = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_b_first_bit_number = 33; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a33 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[34] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_a_first_bit_number = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_b_first_bit_number = 34; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a34 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[35] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_a_first_bit_number = 35; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_b_first_bit_number = 35; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a35 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[36] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_a_first_bit_number = 36; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_b_first_bit_number = 36; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a36 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[37] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_a_first_bit_number = 37; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_b_first_bit_number = 37; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a37 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[38] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_a_first_bit_number = 38; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_b_first_bit_number = 38; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a38 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_ram_block \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 ( .portawe(gnd), .portbre(vcc), .clk0(\clk~CLKENA0 ), .clr0(\areset~CLKENA0 ), .portadatain({\vcc }), .portaaddr({\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[7]~7 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[6]~6 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[5]~5 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[4]~4 , \fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[3]~3 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[2]~2 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[1]~1 ,\fp_pow_0002:fp_pow_inst|addrExp_uid142_fpPowrTest_b[0]~0 }), .portbaddr({\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][7] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][6] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][5] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][4] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][3] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][2] , \fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][1] ,\fp_pow_0002:fp_pow_inst|dspba_delay:redist91_outputreg|delay_signals[0][0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[39] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .operation_mode = "dual_port"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .ram_block_type = "M10K"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .mixed_port_feed_through_mode = "old"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ALTSYNCRAM"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .init_file = "fp_pow_0002_memoryC0_uid419_expTabGen_lutmem.hex"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .init_file_layout = "Port_B"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .data_interleave_width_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .data_interleave_offset_in_bits = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_a_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_a_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_a_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_a_data_out_clock = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_a_data_out_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_a_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_a_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_a_first_bit_number = 39; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_a_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_a_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_a_read_during_write_mode = "new_data_no_nbe_read"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_b_logical_ram_depth = 256; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_b_logical_ram_width = 40; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_b_address_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_b_address_clear = "none"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_b_read_enable_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_b_data_out_clock = "clock0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_b_data_out_clear = "clear0"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_b_first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_b_last_address = 255; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_b_first_bit_number = 39; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_b_data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_b_address_width = 8; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|ram_block2a39 .port_b_read_during_write_mode = "new_data_no_nbe_read"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][39]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[39] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][39]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][39]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][39]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][39]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][39]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][39]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][39] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][39]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][39]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][38]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[38] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][38]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][38]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][38]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][38]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][38]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][38]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][38] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][38]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][38]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][37]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[37] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][37] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][37]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][37]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][36]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[36] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][36]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][36]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][36]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][36]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][36]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][36]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][36] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][36]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][36]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][35]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[35] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][35]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][35]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][35]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][35]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][35]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][35]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][35] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][35]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][35]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][34]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[34] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][34]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][34]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][34]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][34]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][34]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][34]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][33]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[33] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][33]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][33]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][33]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][33]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][33]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][33]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[32] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][32]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][34]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~69 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][34] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][34]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][34]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[31] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][31]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~65 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][33] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][33]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][30]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[30] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][30]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][30]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][30]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][30]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][30]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][30]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][32]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~61 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][32] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][32]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][32]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][31]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~57 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][31] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][31]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][31]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[29] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][29]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][30]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][30] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][30]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][30]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][28]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[28] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][28]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][28]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][28]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][28]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][28]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][28]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][29]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][29] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][29]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][29]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[27] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][27]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][28]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][28] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][28]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][28]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][26]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[26] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][26]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][26]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][26]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][26]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][26]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][26]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][25]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[25] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][25]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][25]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][25]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][25]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][25]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][27]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][27] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][27]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][27]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[24] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][24]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][26]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][26] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][26]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][26]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][25]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][25] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][25]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][25]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[23] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][22]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[22] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][22]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][22]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][22]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][22]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][22]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][24]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][24] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][24]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][24]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][23]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][23] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][23]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][23]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][21]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[21] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][21]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][21]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][21]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][21]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][21]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[20] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][19]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[19] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][19]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][19]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][19]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][19]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][19]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][16]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|__ALT_INV__q_b[16] ), .combout(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][16]~feeder )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][16]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][16]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][16]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][16]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~77 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[14] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~81 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~85 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~89 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~93 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~97 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~101 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~105 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~109 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~113 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~117 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~121 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~125 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~129 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add45~133 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist25|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:memoryC0_uid419_expTabGen_lutmem_dmem|altera_syncram_7sl3:auto_generated|altsyncram_cme4:altsyncram1|q_b[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist14|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~158_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][2] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][0] ), .cin(gnd), .cout(\fp_pow_0002:fp_pow_inst|Add46~158 )); defparam \fp_pow_0002:fp_pow_inst|Add46~158_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~158_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~158_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~154_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][3] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][1] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~158 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~154 )); defparam \fp_pow_0002:fp_pow_inst|Add46~154_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~154_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~154_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~150_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][4] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][2] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~154 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~150 )); defparam \fp_pow_0002:fp_pow_inst|Add46~150_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~150_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~150_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~146_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][5] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][3] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~150 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~146 )); defparam \fp_pow_0002:fp_pow_inst|Add46~146_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~146_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~146_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~142_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][6] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][4] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~146 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~142 )); defparam \fp_pow_0002:fp_pow_inst|Add46~142_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~142_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~142_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~138_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][7] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~142 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~138 )); defparam \fp_pow_0002:fp_pow_inst|Add46~138_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~138_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~138_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~134_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][8] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][6] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~138 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~134 )); defparam \fp_pow_0002:fp_pow_inst|Add46~134_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~134_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~134_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~130_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][9] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~134 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~130 )); defparam \fp_pow_0002:fp_pow_inst|Add46~130_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~130_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~130_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~126_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][10] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][8] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~130 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~126 )); defparam \fp_pow_0002:fp_pow_inst|Add46~126_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~126_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~126_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~122_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][11] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][9] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~126 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~122 )); defparam \fp_pow_0002:fp_pow_inst|Add46~122_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~122_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~122_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~118_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][12] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][10] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~122 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~118 )); defparam \fp_pow_0002:fp_pow_inst|Add46~118_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~118_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~118_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~114_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][13] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][11] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~118 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~114 )); defparam \fp_pow_0002:fp_pow_inst|Add46~114_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~114_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~114_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~110_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][14] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][12] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~114 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~110 )); defparam \fp_pow_0002:fp_pow_inst|Add46~110_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~110_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~110_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~102_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][15] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][13] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~110 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~102 )); defparam \fp_pow_0002:fp_pow_inst|Add46~102_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~102_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~102_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~94_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][16] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][14] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~102 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~94 )); defparam \fp_pow_0002:fp_pow_inst|Add46~94_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~94_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~94_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][15] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][17] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~94 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~1 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~2 )); defparam \fp_pow_0002:fp_pow_inst|Add46~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~1_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~5_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][18] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][16] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~2 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~6 )); defparam \fp_pow_0002:fp_pow_inst|Add46~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~5_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~9_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][19] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][17] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~10 )); defparam \fp_pow_0002:fp_pow_inst|Add46~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~9_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~13_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][20] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][18] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~14 )); defparam \fp_pow_0002:fp_pow_inst|Add46~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~13_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~17_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][19] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][21] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~18 )); defparam \fp_pow_0002:fp_pow_inst|Add46~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~17_I .lut_mask = "0000FF0000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~21_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][20] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][22] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~22 )); defparam \fp_pow_0002:fp_pow_inst|Add46~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~21_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~25_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][23] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][21] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~26 )); defparam \fp_pow_0002:fp_pow_inst|Add46~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~25_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~29_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][22] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][24] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~30 )); defparam \fp_pow_0002:fp_pow_inst|Add46~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~29_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~33_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][25] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][23] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~33 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~34 )); defparam \fp_pow_0002:fp_pow_inst|Add46~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~33_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~37_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][24] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][26] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~34 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~38 )); defparam \fp_pow_0002:fp_pow_inst|Add46~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~37_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~41_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][25] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][27] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~42 )); defparam \fp_pow_0002:fp_pow_inst|Add46~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~41_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~45_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][28] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][26] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~46 )); defparam \fp_pow_0002:fp_pow_inst|Add46~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~45_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~49_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][29] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][27] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~50 )); defparam \fp_pow_0002:fp_pow_inst|Add46~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~49_I .lut_mask = "0000AAAA000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~53_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][30] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][28] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~53 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~54 )); defparam \fp_pow_0002:fp_pow_inst|Add46~53_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~53_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~53_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~57_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][31] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][29] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~54 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~57 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~58 )); defparam \fp_pow_0002:fp_pow_inst|Add46~57_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~57_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~57_I .lut_mask = "0000AAAA00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~61_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][30] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][32] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~58 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~61 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~62 )); defparam \fp_pow_0002:fp_pow_inst|Add46~61_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~61_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~61_I .lut_mask = "0000F0F000003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~65_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][31] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][33] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~62 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~65 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~66 )); defparam \fp_pow_0002:fp_pow_inst|Add46~65_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~65_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~65_I .lut_mask = "0000FF0000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~69_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][32] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][34] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~66 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~69 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~70 )); defparam \fp_pow_0002:fp_pow_inst|Add46~69_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~69_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~69_I .lut_mask = "0000F0F0000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~73_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][33] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][35] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~70 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~73 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~74 )); defparam \fp_pow_0002:fp_pow_inst|Add46~73_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~73_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~73_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~77_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][34] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][35] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~74 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~77 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~78 )); defparam \fp_pow_0002:fp_pow_inst|Add46~77_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~77_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~77_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~81_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][35] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][35] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~78 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~81 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~82 )); defparam \fp_pow_0002:fp_pow_inst|Add46~81_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~81_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~81_I .lut_mask = "0000F0F000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~85_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][35] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][36] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~82 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~85 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~86 )); defparam \fp_pow_0002:fp_pow_inst|Add46~85_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~85_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~85_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~89_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][37] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][35] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~86 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~89 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~90 )); defparam \fp_pow_0002:fp_pow_inst|Add46~89_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~89_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~89_I .lut_mask = "0000CCCC00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~106_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][35] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][38] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~90 ), .cout(\fp_pow_0002:fp_pow_inst|Add46~106 )); defparam \fp_pow_0002:fp_pow_inst|Add46~106_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~106_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~106_I .lut_mask = "0000CCCC000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add46~97_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist25|__ALT_INV__delay_signals[0][35] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist14|__ALT_INV__delay_signals[0][39] ), .cin(\fp_pow_0002:fp_pow_inst|Add46~106 ), .sumout(\fp_pow_0002:fp_pow_inst|Add46~97 )); defparam \fp_pow_0002:fp_pow_inst|Add46~97_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~97_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add46~97_I .lut_mask = "0000CCCC00000F0F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist85|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~97 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist85|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist85|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist85|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add50~1_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist85|__ALT_INV__delay_signals[0][0] ), .cin(gnd), .sumout(\fp_pow_0002:fp_pow_inst|Add50~1 ), .cout(\fp_pow_0002:fp_pow_inst|Add50~2 )); defparam \fp_pow_0002:fp_pow_inst|Add50~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~1_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add50~5_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[1] ), .cin(\fp_pow_0002:fp_pow_inst|Add50~2 ), .sumout(\fp_pow_0002:fp_pow_inst|Add50~5 ), .cout(\fp_pow_0002:fp_pow_inst|Add50~6 )); defparam \fp_pow_0002:fp_pow_inst|Add50~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~5_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add50~9_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[2] ), .cin(\fp_pow_0002:fp_pow_inst|Add50~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add50~9 ), .cout(\fp_pow_0002:fp_pow_inst|Add50~10 )); defparam \fp_pow_0002:fp_pow_inst|Add50~9_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~9_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~9_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add50~13_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[3] ), .cin(\fp_pow_0002:fp_pow_inst|Add50~10 ), .sumout(\fp_pow_0002:fp_pow_inst|Add50~13 ), .cout(\fp_pow_0002:fp_pow_inst|Add50~14 )); defparam \fp_pow_0002:fp_pow_inst|Add50~13_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~13_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~13_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add50~17_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[4] ), .cin(\fp_pow_0002:fp_pow_inst|Add50~14 ), .sumout(\fp_pow_0002:fp_pow_inst|Add50~17 ), .cout(\fp_pow_0002:fp_pow_inst|Add50~18 )); defparam \fp_pow_0002:fp_pow_inst|Add50~17_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~17_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~17_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add50~21_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[5] ), .cin(\fp_pow_0002:fp_pow_inst|Add50~18 ), .sumout(\fp_pow_0002:fp_pow_inst|Add50~21 ), .cout(\fp_pow_0002:fp_pow_inst|Add50~22 )); defparam \fp_pow_0002:fp_pow_inst|Add50~21_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~21_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~21_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add50~25_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[6] ), .cin(\fp_pow_0002:fp_pow_inst|Add50~22 ), .sumout(\fp_pow_0002:fp_pow_inst|Add50~25 ), .cout(\fp_pow_0002:fp_pow_inst|Add50~26 )); defparam \fp_pow_0002:fp_pow_inst|Add50~25_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~25_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~25_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add50~29_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[7] ), .cin(\fp_pow_0002:fp_pow_inst|Add50~26 ), .sumout(\fp_pow_0002:fp_pow_inst|Add50~29 ), .cout(\fp_pow_0002:fp_pow_inst|Add50~30 )); defparam \fp_pow_0002:fp_pow_inst|Add50~29_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~29_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~29_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add50~49_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[8] ), .cin(\fp_pow_0002:fp_pow_inst|Add50~30 ), .sumout(\fp_pow_0002:fp_pow_inst|Add50~49 ), .cout(\fp_pow_0002:fp_pow_inst|Add50~50 )); defparam \fp_pow_0002:fp_pow_inst|Add50~49_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~49_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~49_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add50~45_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[9] ), .cin(\fp_pow_0002:fp_pow_inst|Add50~50 ), .sumout(\fp_pow_0002:fp_pow_inst|Add50~45 ), .cout(\fp_pow_0002:fp_pow_inst|Add50~46 )); defparam \fp_pow_0002:fp_pow_inst|Add50~45_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~45_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~45_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add50~41_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[10] ), .cin(\fp_pow_0002:fp_pow_inst|Add50~46 ), .sumout(\fp_pow_0002:fp_pow_inst|Add50~41 ), .cout(\fp_pow_0002:fp_pow_inst|Add50~42 )); defparam \fp_pow_0002:fp_pow_inst|Add50~41_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~41_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~41_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add50~37_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[11] ), .cin(\fp_pow_0002:fp_pow_inst|Add50~42 ), .sumout(\fp_pow_0002:fp_pow_inst|Add50~37 ), .cout(\fp_pow_0002:fp_pow_inst|Add50~38 )); defparam \fp_pow_0002:fp_pow_inst|Add50~37_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~37_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~37_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add50~33_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc0_uid147_fpPowrTest_o[11] ), .cin(\fp_pow_0002:fp_pow_inst|Add50~38 ), .sumout(\fp_pow_0002:fp_pow_inst|Add50~33 )); defparam \fp_pow_0002:fp_pow_inst|Add50~33_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~33_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add50~33_I .lut_mask = "0000FFFF00003333"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add50~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[12] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add50~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[11] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add50~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[10] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add50~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[9] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add50~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[8] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add50~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[7] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add50~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[6] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add50~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[5] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add50~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[4] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add50~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[3] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[2]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add50~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[2]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[2]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[2]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[2]~DUPLICATE_I .created_from = "Q(expRPostBiasPreExc_uid148_fpPowrTest_o[2])"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add50~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[1] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add50~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[0] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add61~50_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[1] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[0] ), .cin(gnd), .cout(\fp_pow_0002:fp_pow_inst|Add61~50 )); defparam \fp_pow_0002:fp_pow_inst|Add61~50_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~50_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~50_I .lut_mask = "0000CCCC00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add61~46_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[2]~DUPLICATE ), .cin(\fp_pow_0002:fp_pow_inst|Add61~50 ), .cout(\fp_pow_0002:fp_pow_inst|Add61~46 )); defparam \fp_pow_0002:fp_pow_inst|Add61~46_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~46_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~46_I .lut_mask = "0000FFFF00005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add61~42_I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[3] ), .cin(\fp_pow_0002:fp_pow_inst|Add61~46 ), .cout(\fp_pow_0002:fp_pow_inst|Add61~42 )); defparam \fp_pow_0002:fp_pow_inst|Add61~42_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~42_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~42_I .lut_mask = "0000FFFF000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add61~38_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[4] ), .cin(\fp_pow_0002:fp_pow_inst|Add61~42 ), .cout(\fp_pow_0002:fp_pow_inst|Add61~38 )); defparam \fp_pow_0002:fp_pow_inst|Add61~38_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~38_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~38_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add61~34_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[5] ), .cin(\fp_pow_0002:fp_pow_inst|Add61~38 ), .cout(\fp_pow_0002:fp_pow_inst|Add61~34 )); defparam \fp_pow_0002:fp_pow_inst|Add61~34_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~34_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~34_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add61~30_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[6] ), .cin(\fp_pow_0002:fp_pow_inst|Add61~34 ), .cout(\fp_pow_0002:fp_pow_inst|Add61~30 )); defparam \fp_pow_0002:fp_pow_inst|Add61~30_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~30_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~30_I .lut_mask = "0000FFFF00000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add61~26_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[7] ), .cin(\fp_pow_0002:fp_pow_inst|Add61~30 ), .cout(\fp_pow_0002:fp_pow_inst|Add61~26 )); defparam \fp_pow_0002:fp_pow_inst|Add61~26_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~26_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~26_I .lut_mask = "0000FFFF00003333"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add61~22_I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[8] ), .cin(\fp_pow_0002:fp_pow_inst|Add61~26 ), .cout(\fp_pow_0002:fp_pow_inst|Add61~22 )); defparam \fp_pow_0002:fp_pow_inst|Add61~22_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~22_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~22_I .lut_mask = "00000000000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add61~18_I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[9] ), .cin(\fp_pow_0002:fp_pow_inst|Add61~22 ), .cout(\fp_pow_0002:fp_pow_inst|Add61~18 )); defparam \fp_pow_0002:fp_pow_inst|Add61~18_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~18_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~18_I .lut_mask = "00000000000000FF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add61~14_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[10] ), .cin(\fp_pow_0002:fp_pow_inst|Add61~18 ), .cout(\fp_pow_0002:fp_pow_inst|Add61~14 )); defparam \fp_pow_0002:fp_pow_inst|Add61~14_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~14_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~14_I .lut_mask = "0000000000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add61~10_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[11] ), .cin(\fp_pow_0002:fp_pow_inst|Add61~14 ), .cout(\fp_pow_0002:fp_pow_inst|Add61~10 )); defparam \fp_pow_0002:fp_pow_inst|Add61~10_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~10_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~10_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add61~6_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[12] ), .cin(\fp_pow_0002:fp_pow_inst|Add61~10 ), .cout(\fp_pow_0002:fp_pow_inst|Add61~6 )); defparam \fp_pow_0002:fp_pow_inst|Add61~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~6_I .lut_mask = "0000000000005555"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add61~1_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[12] ), .cin(\fp_pow_0002:fp_pow_inst|Add61~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add61~1 )); defparam \fp_pow_0002:fp_pow_inst|Add61~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add61~1_I .lut_mask = "0000000000000F0F"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|infCase4_uid187_fpPowrTest_q_i[0]~I ( .dataa(\fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add61~1 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__zeroCase6_uid165_fpPowrTest_q_i[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|infCase4_uid187_fpPowrTest_q_i[0] )); defparam \fp_pow_0002:fp_pow_inst|infCase4_uid187_fpPowrTest_q_i[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|infCase4_uid187_fpPowrTest_q_i[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|infCase4_uid187_fpPowrTest_q_i[0]~I .lut_mask = "00000000A0A0A0A0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:infCase4_uid187_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|infCase4_uid187_fpPowrTest_q_i[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:infCase4_uid187_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:infCase4_uid187_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:infCase4_uid187_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|infCase0_uid195_fpPowrTest_q_i[0]~I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist130_outputreg|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist127_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist117_outputreg|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|infCase0_uid195_fpPowrTest_q_i[0] )); defparam \fp_pow_0002:fp_pow_inst|infCase0_uid195_fpPowrTest_q_i[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|infCase0_uid195_fpPowrTest_q_i[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|infCase0_uid195_fpPowrTest_q_i[0]~I .lut_mask = "00030003000F000F"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:infCase0_uid195_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|infCase0_uid195_fpPowrTest_q_i[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:infCase0_uid195_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:infCase0_uid195_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:infCase0_uid195_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist81_sticky_ena_q[0]~feeder_I ( .combout(\fp_pow_0002:fp_pow_inst|redist81_sticky_ena_q[0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist81_sticky_ena_q[0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist81_sticky_ena_q[0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist81_sticky_ena_q[0]~feeder_I .lut_mask = "FFFFFFFFFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist81_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist81_sticky_ena_q[0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|redist78_cmpReg_q[0] ), .q(\fp_pow_0002:fp_pow_inst|redist81_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist81_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist81_sticky_ena_q[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add64~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[3] )); defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[2]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add64~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[2]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[2]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[2]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[2]~DUPLICATE_I .created_from = "Q(redist83_replace_rdcnt_i[2])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add64~1_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add54~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_eq ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[3] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Add64~1 )); defparam \fp_pow_0002:fp_pow_inst|Add64~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add64~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add64~1_I .lut_mask = "0AF50AF550AF50AF"; dffeas \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[3]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add64~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[3]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[3]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[3]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[3]~DUPLICATE_I .created_from = "Q(redist83_replace_rdcnt_i[3])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal32~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[4] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[3]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[2] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[1]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Equal32~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal32~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal32~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal32~0_I .lut_mask = "0000000000400040"; dffeas \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_eq~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal32~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_eq )); defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_eq~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_eq~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add64~0_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add54~0 ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_eq ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|Add64~0 )); defparam \fp_pow_0002:fp_pow_inst|Add64~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add64~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add64~0_I .lut_mask = "0FF0F00F0FF0F00F"; dffeas \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add64~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[2] )); defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[4]~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add54~0 ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[2] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_eq ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[4] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[3] ), .combout(\fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[4]~0 )); defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[4]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[4]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[4]~0_I .lut_mask = "07F807F81FE01FE0"; dffeas \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[4]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[4] )); defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Equal31~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[4] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[3]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Equal31~0 )); defparam \fp_pow_0002:fp_pow_inst|Equal31~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal31~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Equal31~0_I .lut_mask = "0400040000000000"; dffeas \fp_pow_0002:fp_pow_inst|redist83_cmpReg_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Equal31~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist83_cmpReg_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist83_cmpReg_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist83_cmpReg_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist83_sticky_ena_q[0]~0_I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_sticky_ena_q[0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_cmpReg_q[0] ), .combout(\fp_pow_0002:fp_pow_inst|redist83_sticky_ena_q[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|redist83_sticky_ena_q[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist83_sticky_ena_q[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist83_sticky_ena_q[0]~0_I .lut_mask = "00FF00FFFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist83_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist83_sticky_ena_q[0]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist83_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist83_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist83_sticky_ena_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~122_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][1]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__oMzLog_uid62_fpPowrTest_o[0] ), .cin(gnd), .cout(\fp_pow_0002:fp_pow_inst|Add65~122 )); defparam \fp_pow_0002:fp_pow_inst|Add65~122_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~122_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~122_I .lut_mask = "000033330000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~118_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][2] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~122 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~118 )); defparam \fp_pow_0002:fp_pow_inst|Add65~118_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~118_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~118_I .lut_mask = "0000FFFF0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~114_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][3] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~118 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~114 )); defparam \fp_pow_0002:fp_pow_inst|Add65~114_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~114_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~114_I .lut_mask = "0000FFFF0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~110_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][4] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~114 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~110 )); defparam \fp_pow_0002:fp_pow_inst|Add65~110_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~110_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~110_I .lut_mask = "0000FFFF0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~106_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~110 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~106 )); defparam \fp_pow_0002:fp_pow_inst|Add65~106_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~106_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~106_I .lut_mask = "0000FFFF0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~102_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][6] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~106 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~102 )); defparam \fp_pow_0002:fp_pow_inst|Add65~102_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~102_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~102_I .lut_mask = "0000FFFF0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~98_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~102 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~98 )); defparam \fp_pow_0002:fp_pow_inst|Add65~98_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~98_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~98_I .lut_mask = "0000FFFF0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~94_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][8] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~98 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~94 )); defparam \fp_pow_0002:fp_pow_inst|Add65~94_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~94_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~94_I .lut_mask = "0000FFFF0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~90_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][9] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~94 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~90 )); defparam \fp_pow_0002:fp_pow_inst|Add65~90_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~90_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~90_I .lut_mask = "0000FFFF0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~86_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][10] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~90 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~86 )); defparam \fp_pow_0002:fp_pow_inst|Add65~86_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~86_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~86_I .lut_mask = "0000FFFF0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~82_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][11] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~86 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~82 )); defparam \fp_pow_0002:fp_pow_inst|Add65~82_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~82_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~82_I .lut_mask = "0000FFFF0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~78_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][12] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~82 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~78 )); defparam \fp_pow_0002:fp_pow_inst|Add65~78_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~78_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~78_I .lut_mask = "0000FFFF0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~74_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][13] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~78 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~74 )); defparam \fp_pow_0002:fp_pow_inst|Add65~74_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~74_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~74_I .lut_mask = "0000FFFF0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~70_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][14] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~74 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~70 )); defparam \fp_pow_0002:fp_pow_inst|Add65~70_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~70_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~70_I .lut_mask = "0000FFFF0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~66_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][15] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~70 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~66 )); defparam \fp_pow_0002:fp_pow_inst|Add65~66_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~66_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~66_I .lut_mask = "0000FFFF0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~62_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][16] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~66 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~62 )); defparam \fp_pow_0002:fp_pow_inst|Add65~62_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~62_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~62_I .lut_mask = "0000FFFF0000AAAA"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~58_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][17] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~62 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~58 )); defparam \fp_pow_0002:fp_pow_inst|Add65~58_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~58_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~58_I .lut_mask = "0000FFFF0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~54_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][18] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~58 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~54 )); defparam \fp_pow_0002:fp_pow_inst|Add65~54_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~54_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~54_I .lut_mask = "0000FFFF0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~50_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][19] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~54 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~50 )); defparam \fp_pow_0002:fp_pow_inst|Add65~50_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~50_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~50_I .lut_mask = "0000FFFF0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~46_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][20] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~50 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~46 )); defparam \fp_pow_0002:fp_pow_inst|Add65~46_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~46_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~46_I .lut_mask = "0000FFFF0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~42_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][21] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~46 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~42 )); defparam \fp_pow_0002:fp_pow_inst|Add65~42_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~42_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~42_I .lut_mask = "0000FFFF0000CCCC"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~38_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist138|__ALT_INV__delay_signals[0][22] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~42 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~38 )); defparam \fp_pow_0002:fp_pow_inst|Add65~38_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~38_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~38_I .lut_mask = "0000FFFF0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~34_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][0] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~38 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~34 )); defparam \fp_pow_0002:fp_pow_inst|Add65~34_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~34_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~34_I .lut_mask = "000000000000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~30_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][1] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~34 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~30 )); defparam \fp_pow_0002:fp_pow_inst|Add65~30_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~30_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~30_I .lut_mask = "000000000000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~26_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][2] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~30 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~26 )); defparam \fp_pow_0002:fp_pow_inst|Add65~26_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~26_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~26_I .lut_mask = "000000000000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~22_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][3] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~26 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~22 )); defparam \fp_pow_0002:fp_pow_inst|Add65~22_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~22_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~22_I .lut_mask = "000000000000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~18_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][4] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~22 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~18 )); defparam \fp_pow_0002:fp_pow_inst|Add65~18_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~18_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~18_I .lut_mask = "000000000000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~14_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][5] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~18 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~14 )); defparam \fp_pow_0002:fp_pow_inst|Add65~14_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~14_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~14_I .lut_mask = "000000000000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~10_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][6] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~14 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~10 )); defparam \fp_pow_0002:fp_pow_inst|Add65~10_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~10_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~10_I .lut_mask = "000000000000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~6_I ( .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist134_outputreg|__ALT_INV__delay_signals[0][7] ), .cin(\fp_pow_0002:fp_pow_inst|Add65~10 ), .cout(\fp_pow_0002:fp_pow_inst|Add65~6 )); defparam \fp_pow_0002:fp_pow_inst|Add65~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~6_I .lut_mask = "0000FFFF0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add65~1_I ( .cin(\fp_pow_0002:fp_pow_inst|Add65~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add65~1 )); defparam \fp_pow_0002:fp_pow_inst|Add65~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add65~1_I .lut_mask = "0000FFFF0000FFFF"; dffeas \fp_pow_0002:fp_pow_inst|expFracXGTExpFracOne_uid155_fpPowrTest_o[33]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add65~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expFracXGTExpFracOne_uid155_fpPowrTest_o[33] )); defparam \fp_pow_0002:fp_pow_inst|expFracXGTExpFracOne_uid155_fpPowrTest_o[33]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expFracXGTExpFracOne_uid155_fpPowrTest_o[33]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[2]~DUPLICATE ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[2] )); defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[3]~DUPLICATE ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[3] )); defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[4]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[4]~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[4]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[4]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[4]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdcnt_i[4]~DUPLICATE_I .created_from = "Q(redist83_replace_rdcnt_i[4])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[4]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[4]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[4]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[4]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[4] )); defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[0]~0_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdreg_q[0] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "FFFFFFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist77_replace_rdcnt_i[1]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[1]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[1] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[2]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[2]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[2]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[2]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[2] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[3]~feeder_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[3]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[3]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[3]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[3] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[4]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist83_replace_rdcnt_i[4]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[4]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[4]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[4]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[4]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[4]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[4] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist83_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_6312,portadatain_unconnected_wire_6313,portadatain_unconnected_wire_6314,portadatain_unconnected_wire_6315,portadatain_unconnected_wire_6316,portadatain_unconnected_wire_6317,portadatain_unconnected_wire_6318, portadatain_unconnected_wire_6319,portadatain_unconnected_wire_6320,portadatain_unconnected_wire_6321,portadatain_unconnected_wire_6322,portadatain_unconnected_wire_6323,portadatain_unconnected_wire_6324,portadatain_unconnected_wire_6325, portadatain_unconnected_wire_6326,portadatain_unconnected_wire_6327,portadatain_unconnected_wire_6328,portadatain_unconnected_wire_6329,portadatain_unconnected_wire_6330,\fp_pow_0002:fp_pow_inst|expFracXGTExpFracOne_uid155_fpPowrTest_o[33] }), .portaaddr({portaaddr_unconnected_wire_6331,\fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist83_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist102_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist77_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_6332,\fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0 .logical_ram_depth = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0 .logical_ram_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0 .last_address = 19; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|xGTOne_uid157_fpPowrTest_q_i[0]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist133|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist83_replace_mem_dmem|altera_syncram_mdg3:auto_generated|altsyncram_hmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .combout(\fp_pow_0002:fp_pow_inst|xGTOne_uid157_fpPowrTest_q_i[0] )); defparam \fp_pow_0002:fp_pow_inst|xGTOne_uid157_fpPowrTest_q_i[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|xGTOne_uid157_fpPowrTest_q_i[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|xGTOne_uid157_fpPowrTest_q_i[0]~I .lut_mask = "0C0C0C0C0C0C0C0C"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:xGTOne_uid157_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|xGTOne_uid157_fpPowrTest_q_i[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:xGTOne_uid157_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:xGTOne_uid157_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:xGTOne_uid157_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "FFFFFFFF00000000"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[1] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist78_replace_rdcnt_i[2] ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[3]~DUPLICATE ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist78_replace_rdcnt_i[4] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist81_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_6333,portadatain_unconnected_wire_6334,portadatain_unconnected_wire_6335,portadatain_unconnected_wire_6336,portadatain_unconnected_wire_6337,portadatain_unconnected_wire_6338,portadatain_unconnected_wire_6339, portadatain_unconnected_wire_6340,portadatain_unconnected_wire_6341,portadatain_unconnected_wire_6342,portadatain_unconnected_wire_6343,portadatain_unconnected_wire_6344,portadatain_unconnected_wire_6345,portadatain_unconnected_wire_6346, portadatain_unconnected_wire_6347,portadatain_unconnected_wire_6348,portadatain_unconnected_wire_6349,portadatain_unconnected_wire_6350,portadatain_unconnected_wire_6351,\fp_pow_0002:fp_pow_inst|dspba_delay:xGTOne_uid157_fpPowrTest_delay|delay_signals[0][0] }), .portaaddr({portaaddr_unconnected_wire_6352,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[1]~DUPLICATE , \fp_pow_0002:fp_pow_inst|redist78_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_6353,\fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_depth = 23; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .last_address = 22; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|ALTDPRAM_INSTANCE"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|infCase1_uid194_fpPowrTest_q_i[0]~I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist130_outputreg|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|infCase1_uid194_fpPowrTest_q_i[0] )); defparam \fp_pow_0002:fp_pow_inst|infCase1_uid194_fpPowrTest_q_i[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|infCase1_uid194_fpPowrTest_q_i[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|infCase1_uid194_fpPowrTest_q_i[0]~I .lut_mask = "0003000300000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:infCase1_uid194_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|infCase1_uid194_fpPowrTest_q_i[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:infCase1_uid194_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:infCase1_uid194_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:infCase1_uid194_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|excRInf_uid196_fpPowrTest_q[0]~I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:infCase2_uid192_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:infCase5_uid184_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:infCase3_uid191_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:infCase4_uid187_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:infCase0_uid195_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:infCase1_uid194_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|excRInf_uid196_fpPowrTest_q[0] )); defparam \fp_pow_0002:fp_pow_inst|excRInf_uid196_fpPowrTest_q[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|excRInf_uid196_fpPowrTest_q[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|excRInf_uid196_fpPowrTest_q[0]~I .lut_mask = "8000000000000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[0]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[0]~feeder_I .lut_mask = "00000000FFFFFFFF"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|redist75_sticky_ena_q[0]~feeder_I ( .combout(\fp_pow_0002:fp_pow_inst|redist75_sticky_ena_q[0]~feeder )); defparam \fp_pow_0002:fp_pow_inst|redist75_sticky_ena_q[0]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|redist75_sticky_ena_q[0]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|redist75_sticky_ena_q[0]~feeder_I .lut_mask = "FFFFFFFFFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|redist75_sticky_ena_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|redist75_sticky_ena_q[0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .ena(\fp_pow_0002:fp_pow_inst|redist75_cmpReg_q[0] ), .q(\fp_pow_0002:fp_pow_inst|redist75_sticky_ena_q[0] )); defparam \fp_pow_0002:fp_pow_inst|redist75_sticky_ena_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|redist75_sticky_ena_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|excROne_uid205_fpPowrTest_q_i[0]~I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist128|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist121|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|excROne_uid205_fpPowrTest_q_i[0] )); defparam \fp_pow_0002:fp_pow_inst|excROne_uid205_fpPowrTest_q_i[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|excROne_uid205_fpPowrTest_q_i[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|excROne_uid205_fpPowrTest_q_i[0]~I .lut_mask = "33333333FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:excROne_uid205_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|excROne_uid205_fpPowrTest_q_i[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:excROne_uid205_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:excROne_uid205_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:excROne_uid205_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0]~0_I ( .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0]~0_I .lut_mask = "FFFF0000FFFF0000"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0]~0 ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[1] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[1] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[2]~DUPLICATE ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[2] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3]~feeder_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__redist75_replace_rdcnt_i[3]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3]~feeder_I .lut_mask = "3333333333333333"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3]~feeder ), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|redist75_replace_rdcnt_i[4]~DUPLICATE ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[4] )); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[4]~I .is_wysiwyg = "true"; cyclonev_mlab_cell \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 ( .clk0(\clk~CLKENA0 ), .clk1(\clk~CLKENA0 ), .ena0(vcc), .ena1(\fp_pow_0002:fp_pow_inst|redist75_sticky_ena_q[0] ), .clr(\areset~CLKENA0 ), .portadatain({portadatain_unconnected_wire_6354,portadatain_unconnected_wire_6355,portadatain_unconnected_wire_6356,portadatain_unconnected_wire_6357,portadatain_unconnected_wire_6358,portadatain_unconnected_wire_6359,portadatain_unconnected_wire_6360, portadatain_unconnected_wire_6361,portadatain_unconnected_wire_6362,portadatain_unconnected_wire_6363,portadatain_unconnected_wire_6364,portadatain_unconnected_wire_6365,portadatain_unconnected_wire_6366,portadatain_unconnected_wire_6367, portadatain_unconnected_wire_6368,portadatain_unconnected_wire_6369,portadatain_unconnected_wire_6370,portadatain_unconnected_wire_6371,portadatain_unconnected_wire_6372,\fp_pow_0002:fp_pow_inst|dspba_delay:excROne_uid205_fpPowrTest_delay|delay_signals[0][0] }), .portaaddr({portaaddr_unconnected_wire_6373,\fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[4] ,\fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[3] ,\fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[2] ,\fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[1] , \fp_pow_0002:fp_pow_inst|redist75_replace_rdreg_q[0] }), .portbaddr({portbaddr_unconnected_wire_6374,\fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[4] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[3] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[2] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[1] , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|rdaddr_reg[0] }), .portbdataout({\fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT19 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT18 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT17 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT16 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT15 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT14 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT13 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT12 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT11 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT10 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT9 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT8 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT7 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT6 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT5 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT4 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT3 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT2 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0~PORTBDATAOUT1 , \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|dataout_reg[0] })); defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .mixed_port_feed_through_mode = "Dont Care"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .init_file = "NONE"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .logical_ram_depth = 21; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .logical_ram_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .address_width = 5; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .first_bit_number = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .data_width = 1; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .first_address = 0; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .last_address = 20; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .port_b_data_out_clock = "clock1"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .port_b_data_out_clear = "clear"; defparam \fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|lutrama0 .logical_ram_name = "fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|ALTDPRAM_INSTANCE"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|altera_syncram:redist75_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|dataout_reg[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[0]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[0] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|zeroCase2_uid174_fpPowrTest_q_i[0]~I ( .dataa(\fp_pow_0002:fp_pow_inst|altera_syncram:redist79_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist130_outputreg|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|zeroCase2_uid174_fpPowrTest_q_i[0] )); defparam \fp_pow_0002:fp_pow_inst|zeroCase2_uid174_fpPowrTest_q_i[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|zeroCase2_uid174_fpPowrTest_q_i[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|zeroCase2_uid174_fpPowrTest_q_i[0]~I .lut_mask = "0005000500000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase2_uid174_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|zeroCase2_uid174_fpPowrTest_q_i[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase2_uid174_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase2_uid174_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase2_uid174_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add66~50_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[1] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[0] ), .cin(gnd), .cout(\fp_pow_0002:fp_pow_inst|Add66~50 )); defparam \fp_pow_0002:fp_pow_inst|Add66~50_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~50_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~50_I .lut_mask = "000033330000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add66~46_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[2]~DUPLICATE ), .cin(\fp_pow_0002:fp_pow_inst|Add66~50 ), .cout(\fp_pow_0002:fp_pow_inst|Add66~46 )); defparam \fp_pow_0002:fp_pow_inst|Add66~46_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~46_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~46_I .lut_mask = "0000FFFF0000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add66~42_I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[3] ), .cin(\fp_pow_0002:fp_pow_inst|Add66~46 ), .cout(\fp_pow_0002:fp_pow_inst|Add66~42 )); defparam \fp_pow_0002:fp_pow_inst|Add66~42_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~42_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~42_I .lut_mask = "0000FFFF0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add66~38_I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[4] ), .cin(\fp_pow_0002:fp_pow_inst|Add66~42 ), .cout(\fp_pow_0002:fp_pow_inst|Add66~38 )); defparam \fp_pow_0002:fp_pow_inst|Add66~38_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~38_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~38_I .lut_mask = "0000FFFF0000FF00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add66~34_I ( .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[5] ), .cin(\fp_pow_0002:fp_pow_inst|Add66~38 ), .cout(\fp_pow_0002:fp_pow_inst|Add66~34 )); defparam \fp_pow_0002:fp_pow_inst|Add66~34_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~34_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~34_I .lut_mask = "0000FFFF0000CCCC"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add66~30_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[6] ), .cin(\fp_pow_0002:fp_pow_inst|Add66~34 ), .cout(\fp_pow_0002:fp_pow_inst|Add66~30 )); defparam \fp_pow_0002:fp_pow_inst|Add66~30_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~30_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~30_I .lut_mask = "0000FFFF0000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add66~26_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[7] ), .cin(\fp_pow_0002:fp_pow_inst|Add66~30 ), .cout(\fp_pow_0002:fp_pow_inst|Add66~26 )); defparam \fp_pow_0002:fp_pow_inst|Add66~26_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~26_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~26_I .lut_mask = "0000FFFF0000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add66~22_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[8] ), .cin(\fp_pow_0002:fp_pow_inst|Add66~26 ), .cout(\fp_pow_0002:fp_pow_inst|Add66~22 )); defparam \fp_pow_0002:fp_pow_inst|Add66~22_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~22_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~22_I .lut_mask = "0000FFFF0000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add66~18_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[9] ), .cin(\fp_pow_0002:fp_pow_inst|Add66~22 ), .cout(\fp_pow_0002:fp_pow_inst|Add66~18 )); defparam \fp_pow_0002:fp_pow_inst|Add66~18_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~18_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~18_I .lut_mask = "0000FFFF0000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add66~14_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[10] ), .cin(\fp_pow_0002:fp_pow_inst|Add66~18 ), .cout(\fp_pow_0002:fp_pow_inst|Add66~14 )); defparam \fp_pow_0002:fp_pow_inst|Add66~14_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~14_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~14_I .lut_mask = "0000FFFF0000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add66~10_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[11] ), .cin(\fp_pow_0002:fp_pow_inst|Add66~14 ), .cout(\fp_pow_0002:fp_pow_inst|Add66~10 )); defparam \fp_pow_0002:fp_pow_inst|Add66~10_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~10_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~10_I .lut_mask = "0000FFFF0000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add66~6_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[12] ), .cin(\fp_pow_0002:fp_pow_inst|Add66~10 ), .cout(\fp_pow_0002:fp_pow_inst|Add66~6 )); defparam \fp_pow_0002:fp_pow_inst|Add66~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~6_I .lut_mask = "0000FFFF0000AAAA"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Add66~1_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[12] ), .cin(\fp_pow_0002:fp_pow_inst|Add66~6 ), .sumout(\fp_pow_0002:fp_pow_inst|Add66~1 )); defparam \fp_pow_0002:fp_pow_inst|Add66~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Add66~1_I .lut_mask = "0000FFFF0000F0F0"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|zeroCase5_uid167_fpPowrTest_q_i[0]~I ( .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__Add66~1 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__zeroCase6_uid165_fpPowrTest_q_i[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|zeroCase5_uid167_fpPowrTest_q_i[0] )); defparam \fp_pow_0002:fp_pow_inst|zeroCase5_uid167_fpPowrTest_q_i[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|zeroCase5_uid167_fpPowrTest_q_i[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|zeroCase5_uid167_fpPowrTest_q_i[0]~I .lut_mask = "00000000FF00FF00"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase5_uid167_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|zeroCase5_uid167_fpPowrTest_q_i[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase5_uid167_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase5_uid167_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase5_uid167_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|zeroCase3_uid172_fpPowrTest_q_i[0]~I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist82_outputreg|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist122_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist130_outputreg|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist81_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .combout(\fp_pow_0002:fp_pow_inst|zeroCase3_uid172_fpPowrTest_q_i[0] )); defparam \fp_pow_0002:fp_pow_inst|zeroCase3_uid172_fpPowrTest_q_i[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|zeroCase3_uid172_fpPowrTest_q_i[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|zeroCase3_uid172_fpPowrTest_q_i[0]~I .lut_mask = "0000000000010001"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase3_uid172_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|zeroCase3_uid172_fpPowrTest_q_i[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase3_uid172_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase3_uid172_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase3_uid172_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[0][0]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[1][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[0][0]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[0][0]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[0][0]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist100|delay_signals[0][0]~DUPLICATE_I .created_from = "Q(delay_signals[0][0])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|zeroCase6_uid165_fpPowrTest_q_i[0]~I ( .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:redist78_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist100|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist97_replace_mem_dmem|altera_syncram_pdg3:auto_generated|altsyncram_kmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__zeroCase6_uid165_fpPowrTest_q_i[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|zeroCase6_uid165_fpPowrTest_q_i[0] )); defparam \fp_pow_0002:fp_pow_inst|zeroCase6_uid165_fpPowrTest_q_i[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|zeroCase6_uid165_fpPowrTest_q_i[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|zeroCase6_uid165_fpPowrTest_q_i[0]~I .lut_mask = "0000000000030003"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase6_uid165_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|zeroCase6_uid165_fpPowrTest_q_i[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase6_uid165_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase6_uid165_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase6_uid165_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|zeroCase4_uid170_fpPowrTest_q_i[0]~I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:redist82_outputreg|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:redist118_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist123_replace_mem_dmem|altera_syncram_tdg3:auto_generated|altsyncram_omb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:redist130_outputreg|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist117_outputreg|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|zeroCase4_uid170_fpPowrTest_q_i[0] )); defparam \fp_pow_0002:fp_pow_inst|zeroCase4_uid170_fpPowrTest_q_i[0]~I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|zeroCase4_uid170_fpPowrTest_q_i[0]~I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|zeroCase4_uid170_fpPowrTest_q_i[0]~I .lut_mask = "0001000100050005"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase4_uid170_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|zeroCase4_uid170_fpPowrTest_q_i[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase4_uid170_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase4_uid170_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase4_uid170_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|excRZero_uid180_fpPowrTest_q[0]~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase2_uid174_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase5_uid167_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase3_uid172_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase6_uid165_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase4_uid170_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|excRZero_uid180_fpPowrTest_q[0]~0 )); defparam \fp_pow_0002:fp_pow_inst|excRZero_uid180_fpPowrTest_q[0]~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|excRZero_uid180_fpPowrTest_q[0]~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|excRZero_uid180_fpPowrTest_q[0]~0_I .lut_mask = "8000800000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux343~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux343~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux343~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux343~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux343~0_I .lut_mask = "00000000002000A0"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[1]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][1] ), .combout(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[1]~feeder )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[1]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[1]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[1]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[1]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[1] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[1]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][1]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[1] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][1] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux342~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][1] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux342~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux342~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux342~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux342~0_I .lut_mask = "0000000000000080"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[2] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][2]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[2] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][2] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux341~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][2] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux341~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux341~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux341~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux341~0_I .lut_mask = "0000000000002000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~13 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[3]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][3] ), .combout(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[3]~feeder )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[3]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[3]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[3]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[3]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[3] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[3]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][3]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[3] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][3] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux340~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][3] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux340~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux340~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux340~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux340~0_I .lut_mask = "0000000000004000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~17 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[4] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[4]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][4]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[4] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][4] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux339~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][4] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux339~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux339~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux339~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux339~0_I .lut_mask = "0000000000000800"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~21 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[5] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[5]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][5]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[5] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][5] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux338~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][5] ), .dataf(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .combout(\fp_pow_0002:fp_pow_inst|Mux338~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux338~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux338~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux338~0_I .lut_mask = "0000040000000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~25 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[6] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[6]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][6]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[6] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][6] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux337~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][6] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux337~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux337~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux337~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux337~0_I .lut_mask = "0000000000000800"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~29 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[7] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[7]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][7]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[7] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][7] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux336~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][7] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux336~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux336~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux336~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux336~0_I .lut_mask = "0000000000004000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~33 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[8]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][8] ), .combout(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[8]~feeder )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[8]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[8]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[8]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[8]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[8]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[8] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[8]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][8]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[8] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][8] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][8]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][8]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux335~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][8] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux335~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux335~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux335~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux335~0_I .lut_mask = "0000000000004000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~37 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[9]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][9] ), .combout(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[9]~feeder )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[9]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[9]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[9]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[9]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[9]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[9] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[9]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][9]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[9] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][9] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][9]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][9]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux334~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][9] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux334~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux334~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux334~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux334~0_I .lut_mask = "0000000000004000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~41 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[10] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[10]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][10]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[10] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][10] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][10]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][10]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux333~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][10] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux333~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux333~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux333~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux333~0_I .lut_mask = "0000000000004000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~45 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[11] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[11]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][11]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[11] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][11] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][11]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][11]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux332~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][11] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux332~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux332~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux332~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux332~0_I .lut_mask = "0000000000000080"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|zeroCase0_uid179_fpPowrTest_q_i[0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|delay_signals[0][0]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~49 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[12] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[12]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][12]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[12] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][12] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][12]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][12]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux331~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][12] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux331~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux331~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux331~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux331~0_I .lut_mask = "0000000000000080"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~53 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[13]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][13] ), .combout(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[13]~feeder )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[13]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[13]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[13]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[13]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[13]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[13] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[13]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][13]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[13] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][13] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][13]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][13]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux330~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][13] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux330~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux330~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux330~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux330~0_I .lut_mask = "0000000000000080"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~57 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[14]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][14] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[14] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[14]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][14]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[14] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][14] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][14]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][14]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux329~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][14] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux329~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux329~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux329~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux329~0_I .lut_mask = "0000000000000800"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~61 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[15]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[15] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[15]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][15]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[15] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][15] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][15]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][15]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux328~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][15] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux328~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux328~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux328~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux328~0_I .lut_mask = "0000000000004000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~65 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[16]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[16] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[16]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][16]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[16] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][16] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][16]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][16]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux327~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][16] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux327~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux327~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux327~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux327~0_I .lut_mask = "0000000000000080"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~69 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[17]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[17] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[17]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][17]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[17] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][17] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][17]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][17]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux326~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][17] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux326~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux326~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux326~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux326~0_I .lut_mask = "0000000000002000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~73 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[18]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][18] ), .combout(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[18]~feeder )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[18]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[18]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[18]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[18]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[18]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[18] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[18]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][18]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[18] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][18] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][18]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][18]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux325~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][18] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux325~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux325~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux325~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux325~0_I .lut_mask = "0000000000004000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~77 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[19]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[19] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[19]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][19]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[19] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][19] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][19]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][19]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux324~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][19] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux324~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux324~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux324~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux324~0_I .lut_mask = "0000000000004000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~81 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[20]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][20] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[20] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[20]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][20]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[20] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][20] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][20]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][20]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux323~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][20] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux323~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux323~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux323~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux323~0_I .lut_mask = "0000000000000800"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~85 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[21]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[21] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[21]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][21]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[21] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][21] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][21]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][21]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux322~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][21] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux322~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux322~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux322~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux322~0_I .lut_mask = "0000000000000080"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add46~89 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist84|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[22]~feeder_I ( .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist84|__ALT_INV__delay_signals[0][22] ), .combout(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[22]~feeder )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[22]~feeder_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[22]~feeder_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[22]~feeder_I .lut_mask = "00000000FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[22]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[22]~feeder ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sclr(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .q(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[22] )); defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[22]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][22]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|fracRPostOne_uid206_fpPowrTest_q[22] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][22] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][22]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist74|delay_signals[0][22]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux321~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:redist74|__ALT_INV__delay_signals[0][22] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Mux321~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux321~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux321~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux321~0_I .lut_mask = "0000020000000000"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist76|delay_signals[0][0]~DUPLICATE_I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist76|delay_signals[0][0]~DUPLICATE )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist76|delay_signals[0][0]~DUPLICATE_I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist76|delay_signals[0][0]~DUPLICATE_I .is_wysiwyg = "true"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist76|delay_signals[0][0]~DUPLICATE_I .created_from = "Q(delay_signals[0][0])"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist76|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~0 )); defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~0_I .lut_mask = "55555555FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[0]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~0 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[0] )); defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux320~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Mux320~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux320~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux320~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux320~0_I .lut_mask = "2213000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~1_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist76|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[1] ), .combout(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~1 )); defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~1_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~1_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~1_I .lut_mask = "3F3F3F3F3F3F3F3F"; dffeas \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[1]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~1 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[1] )); defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[1]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[1]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux319~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[1] ), .combout(\fp_pow_0002:fp_pow_inst|Mux319~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux319~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux319~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux319~0_I .lut_mask = "0000800800008808"; dffeas \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|Add50~9 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[2] )); defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostBiasPreExc_uid148_fpPowrTest_o[2]~I .is_wysiwyg = "true"; dffeas \fp_pow_0002:fp_pow_inst|dspba_delay:redist76|delay_signals[0][0]~I ( .clk(\clk~CLKENA0 ), .asdata(\fp_pow_0002:fp_pow_inst|dspba_delay:redist75_outputreg|delay_signals[0][0] ), .clrn(\__ALT_INV__areset~CLKENA0 ), .sload(vcc), .q(\fp_pow_0002:fp_pow_inst|dspba_delay:redist76|delay_signals[0][0] )); defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist76|delay_signals[0][0]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|dspba_delay:redist76|delay_signals[0][0]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~2_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[2] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist76|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~2 )); defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~2_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~2_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~2_I .lut_mask = "0F0F0F0FFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[2]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~2 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[2] )); defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[2]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[2]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux318~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[2] ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datad(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datae(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .combout(\fp_pow_0002:fp_pow_inst|Mux318~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux318~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux318~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux318~0_I .lut_mask = "00000000A2000A00"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~3_I ( .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[3] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist76|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~3 )); defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~3_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~3_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~3_I .lut_mask = "0000FFFFFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[3]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~3 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[3] )); defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[3]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[3]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux317~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[3] ), .combout(\fp_pow_0002:fp_pow_inst|Mux317~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux317~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux317~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux317~0_I .lut_mask = "0000800800008088"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~4_I ( .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:redist76|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[4] ), .combout(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~4 )); defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~4_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~4_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~4_I .lut_mask = "33333333FFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[4]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~4 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[4] )); defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[4]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[4]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux316~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[4] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|Mux316~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux316~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux316~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux316~0_I .lut_mask = "2020103000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~5_I ( .datac(\fp_pow_0002:fp_pow_inst|dspba_delay:redist76|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[5] ), .combout(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~5 )); defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~5_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~5_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~5_I .lut_mask = "0F0F0F0FFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[5]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~5 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[5] )); defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[5]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[5]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux315~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datad(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[5] ), .combout(\fp_pow_0002:fp_pow_inst|Mux315~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux315~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux315~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux315~0_I .lut_mask = "0000800800008808"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~6_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[6] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist76|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~6 )); defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~6_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~6_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~6_I .lut_mask = "0F0F0F0FFFFFFFFF"; dffeas \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[6]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~6 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[6] )); defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[6]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[6]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux314~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[6] ), .datab(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datae(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .combout(\fp_pow_0002:fp_pow_inst|Mux314~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux314~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux314~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux314~0_I .lut_mask = "3013000000000000"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~7_I ( .datac(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostBiasPreExc_uid148_fpPowrTest_o[7] ), .dataf(\fp_pow_0002:fp_pow_inst|dspba_delay:redist76|__ALT_INV__delay_signals[0][0] ), .combout(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~7 )); defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~7_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~7_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~7_I .lut_mask = "0F0F0F0F00000000"; dffeas \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[7]~I ( .clk(\clk~CLKENA0 ), .d(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q~7 ), .clrn(\__ALT_INV__areset~CLKENA0 ), .q(\fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[7] )); defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[7]~I .power_up = "low"; defparam \fp_pow_0002:fp_pow_inst|expRPostOne_uid207_fpPowrTest_q[7]~I .is_wysiwyg = "true"; cyclonev_lcell_comb \fp_pow_0002:fp_pow_inst|Mux313~0_I ( .dataa(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase1_uid177_fpPowrTest_delay|__ALT_INV__delay_signals[0][0] ), .datab(\fp_pow_0002:fp_pow_inst|dspba_delay:zeroCase0_uid179_fpPowrTest_delay|__ALT_INV__delay_signals[0][0]~DUPLICATE ), .datac(\fp_pow_0002:fp_pow_inst|altera_syncram:redist77_replace_mem_dmem|altera_syncram_udg3:auto_generated|altsyncram_pmb4:altsyncram1|__ALT_INV__dataout_reg[0] ), .datad(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRInf_uid196_fpPowrTest_q[0] ), .datae(\fp_pow_0002:fp_pow_inst|__ALT_INV__excRZero_uid180_fpPowrTest_q[0]~0 ), .dataf(\fp_pow_0002:fp_pow_inst|__ALT_INV__expRPostOne_uid207_fpPowrTest_q[7] ), .combout(\fp_pow_0002:fp_pow_inst|Mux313~0 )); defparam \fp_pow_0002:fp_pow_inst|Mux313~0_I .shared_arith = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux313~0_I .extended_lut = "off"; defparam \fp_pow_0002:fp_pow_inst|Mux313~0_I .lut_mask = "0000800800008088"; endmodule