{ "dataType": "CVE_RECORD", "dataVersion": "5.1", "cveMetadata": { "cveId": "CVE-2023-6068", "assignerOrgId": "c8b34d1a-69ae-45c3-88fe-f3b3d44f39b7", "state": "PUBLISHED", "assignerShortName": "Arista", "dateReserved": "2023-11-09T23:06:28.873Z", "datePublished": "2024-03-04T19:44:08.620Z", "dateUpdated": "2024-08-02T08:21:17.180Z" }, "containers": { "cna": { "affected": [ { "defaultStatus": "unaffected", "modules": [ "MultiAccess FPGA Software" ], "product": "MOS", "vendor": "Arista Networks", "versions": [ { "status": "affected", "version": "1.7.1" }, { "status": "affected", "version": "1.6" } ] } ], "configurations": [ { "lang": "en", "supportingMedia": [ { "base64": false, "type": "text/html", "value": "
In order to be vulnerable to CVE-2023-6068, the following condition must be met:
MOS must be configured with MultiAccess FPGA software versions 1.7.1 or 1.6.x and can be determined by running the show version command and referring to the highlighted section as shown below.
switch(config)#show version\nDevice: Metamako MetaMux 48 with L-Series\nSKU: DCS-7130-48LB\nSerial number: M48LB-A3-27719-4\n \nSoftware image version: 0.39.0alpha4\nInternal build ID: master+9345\nApplications: multiaccess-1.7.1The recommended resolution is to upgrade to a remediated software version at your earliest convenience. Arista recommends customers move to the latest version of each release that contains all the fixes listed below.
CVE-2023-6068 has been fixed in the following releases:
The workaround is to only apply one access-list to any particular port after the MultiAccess image is loaded into the FPGA. If a new access-list is to be applied to a port, the FPGA image should be reloaded after the access-list is applied.
Run the following commands to reload the FPGA image, where the line in yellow represents new access control lists to be added:
switch(config-app-multiaccess)#shut\nswitch(config-app-multiaccess)#multiaccess-group 0 client 0 access-list new_acl_if_need\nswitch(config-app-multiaccess)#no shut\nThe previous applied access control lists will automatically apply after FPGA reload.