(kicad_pcb (version 20211014) (generator pcbnew)

  (general
    (thickness 1.6)
  )

  (paper "A4")
  (layers
    (0 "F.Cu" signal "Top")
    (31 "B.Cu" signal "Bottom")
    (32 "B.Adhes" user "B.Adhesive")
    (33 "F.Adhes" user "F.Adhesive")
    (34 "B.Paste" user)
    (35 "F.Paste" user)
    (36 "B.SilkS" user "B.Silkscreen")
    (37 "F.SilkS" user "F.Silkscreen")
    (38 "B.Mask" user)
    (39 "F.Mask" user)
    (40 "Dwgs.User" user "User.Drawings")
    (41 "Cmts.User" user "User.Comments")
    (42 "Eco1.User" user "User.Eco1")
    (43 "Eco2.User" user "User.Eco2")
    (44 "Edge.Cuts" user)
    (45 "Margin" user)
    (46 "B.CrtYd" user "B.Courtyard")
    (47 "F.CrtYd" user "F.Courtyard")
    (48 "B.Fab" user)
    (49 "F.Fab" user)
  )

  (setup
    (stackup
      (layer "F.SilkS" (type "Top Silk Screen"))
      (layer "F.Paste" (type "Top Solder Paste"))
      (layer "F.Mask" (type "Top Solder Mask") (thickness 0.01))
      (layer "F.Cu" (type "copper") (thickness 0.035))
      (layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
      (layer "B.Cu" (type "copper") (thickness 0.035))
      (layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01))
      (layer "B.Paste" (type "Bottom Solder Paste"))
      (layer "B.SilkS" (type "Bottom Silk Screen"))
      (copper_finish "None")
      (dielectric_constraints no)
    )
    (pad_to_mask_clearance 0)
    (grid_origin 1.27 11.43)
    (pcbplotparams
      (layerselection 0x00010fc_ffffffff)
      (disableapertmacros false)
      (usegerberextensions true)
      (usegerberattributes false)
      (usegerberadvancedattributes false)
      (creategerberjobfile false)
      (svguseinch false)
      (svgprecision 6)
      (excludeedgelayer true)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15.000000)
      (dxfpolygonmode true)
      (dxfimperialunits true)
      (dxfusepcbnewfont true)
      (psnegative false)
      (psa4output false)
      (plotreference false)
      (plotvalue false)
      (plotinvisibletext false)
      (sketchpadsonfab false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 0)
      (scaleselection 1)
      (outputdirectory "//nas.cehq.io/Production/Assemblies/P57 Logic Level Converter Bi-Directional/P57 v2 2022-10-28/gerbers/")
    )
  )

  (net 0 "")
  (net 1 "LV")
  (net 2 "HV")
  (net 3 "/LV4")
  (net 4 "/HV4")
  (net 5 "/LV1")
  (net 6 "/HV1")
  (net 7 "/LV2")
  (net 8 "/GND")
  (net 9 "/LV3")
  (net 10 "/HV3")
  (net 11 "/HV2")

  (footprint "Fiducial:Fiducial_0.5mm_Mask1mm" (layer "F.Cu")
    (tedit 5C18CB26) (tstamp 00000000-0000-0000-0000-00005fb1c8c0)
    (at 11.4808 8.128)
    (descr "Circular Fiducial, 0.5mm bare copper, 1mm soldermask opening (Level C)")
    (tags "fiducial")
    (property "Sheetfile" "//nas.cehq.io/Product Design/Team Workspace/Michael Ruppe/GitHub/CoreElectronics-Logic-Level-Converter-Bidirectional/PCB/CoreElectronics-Logic-Level-Converter-Bidirectional.sch")
    (property "Sheetname" "")
    (property "Supplier Link" "-")
    (path "/00000000-0000-0000-0000-0000193933ab")
    (attr smd)
    (fp_text reference "JP3" (at 0 -1.5) (layer "F.SilkS") hide
      (effects (font (size 1 1) (thickness 0.15)))
      (tstamp 8dd85cf1-190f-4b05-a0f7-cd7a03a914ff)
    )
    (fp_text value "FIDUCIALUFIDUCIAL" (at 21.3192 10.572) (layer "F.Fab")
      (effects (font (size 1 1) (thickness 0.15)))
      (tstamp eb6d5518-e86f-4f01-8806-58643b7abf38)
    )
    (fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
      (effects (font (size 0.2 0.2) (thickness 0.04)))
      (tstamp f88df7ed-5e6f-4f5e-b65e-40ad46e0d47b)
    )
    (fp_circle (center 0 0) (end 0.75 0) (layer "F.CrtYd") (width 0.05) (fill none) (tstamp 186c498c-e0c4-42be-a9e7-e23c52617292))
    (fp_circle (center 0 0) (end 0.5 0) (layer "F.Fab") (width 0.1) (fill none) (tstamp d9e5cee9-5c86-4fdf-ab96-c4049ea2fca9))
    (pad "" smd circle locked (at 0 0) (size 0.5 0.5) (layers "F.Cu" "F.Mask")
      (solder_mask_margin 0.25) (clearance 0.25) (tstamp 583186ae-b633-4dc2-8adb-2fe3e31218d6))
  )

  (footprint "Package_TO_SOT_SMD:SOT-23" (layer "F.Cu")
    (tedit 5A02FF57) (tstamp 00000000-0000-0000-0000-00005fb1c8e2)
    (at 5.8166 6.2738 90)
    (descr "SOT-23, Standard")
    (tags "SOT-23")
    (property "Sheetfile" "//nas.cehq.io/Product Design/Team Workspace/Michael Ruppe/GitHub/CoreElectronics-Logic-Level-Converter-Bidirectional/PCB/CoreElectronics-Logic-Level-Converter-Bidirectional.sch")
    (property "Sheetname" "")
    (path "/00000000-0000-0000-0000-00005f3c4854")
    (attr smd)
    (fp_text reference "Q2" (at 0 -2.5 90) (layer "F.SilkS") hide
      (effects (font (size 1 1) (thickness 0.15)))
      (tstamp 97ecc249-674e-4b84-9dfb-153cda759717)
    )
    (fp_text value "BSS138" (at 0 2.5 90) (layer "F.Fab")
      (effects (font (size 1 1) (thickness 0.15)))
      (tstamp 0b81f3e6-9364-49f4-9d03-7efb592e8b2a)
    )
    (fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
      (effects (font (size 0.5 0.5) (thickness 0.075)))
      (tstamp a696ba77-a9c9-4d3e-98fe-289f22bdbbf3)
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    (fp_line (start 0.76 -1.58) (end 0.76 -0.65) (layer "F.SilkS") (width 0.12) (tstamp 0330fbc0-39d9-4f4d-bfc3-3e799949f001))
    (fp_line (start 0.76 1.58) (end 0.76 0.65) (layer "F.SilkS") (width 0.12) (tstamp 093f45bc-a286-4f7c-a2c7-cdfa2a16bf85))
    (fp_line (start 0.76 -1.58) (end -1.4 -1.58) (layer "F.SilkS") (width 0.12) (tstamp 26393ef4-1c1b-4651-88c5-141af2c2591b))
    (fp_line (start 0.76 1.58) (end -0.7 1.58) (layer "F.SilkS") (width 0.12) (tstamp f3086947-24cd-4e97-a60c-45a3e06db679))
    (fp_line (start 1.7 -1.75) (end 1.7 1.75) (layer "F.CrtYd") (width 0.05) (tstamp 9fd3c4aa-e09d-45d0-9555-c12c6e01821f))
    (fp_line (start -1.7 -1.75) (end 1.7 -1.75) (layer "F.CrtYd") (width 0.05) (tstamp a8c217d1-db97-41fb-9182-af79762f666b))
    (fp_line (start -1.7 1.75) (end -1.7 -1.75) (layer "F.CrtYd") (width 0.05) (tstamp ae2ce547-ec93-4087-b29f-7734efa4f855))
    (fp_line (start 1.7 1.75) (end -1.7 1.75) (layer "F.CrtYd") (width 0.05) (tstamp e2e748df-ab8a-4246-a2ef-c76ac41826c1))
    (fp_line (start 0.7 -1.52) (end 0.7 1.52) (layer "F.Fab") (width 0.1) (tstamp 2797dbc5-dd96-40d9-beaf-9352d414f7c5))
    (fp_line (start -0.7 -0.95) (end -0.15 -1.52) (layer "F.Fab") (width 0.1) (tstamp 42cc9420-20bc-45b5-8950-2cf6ba6fc60c))
    (fp_line (start -0.7 -0.95) (end -0.7 1.5) (layer "F.Fab") (width 0.1) (tstamp bdbb864a-b3a2-43fb-814f-1434253bc6da))
    (fp_line (start -0.15 -1.52) (end 0.7 -1.52) (layer "F.Fab") (width 0.1) (tstamp d1440465-41df-4503-a20d-49e28b2bb294))
    (fp_line (start -0.7 1.52) (end 0.7 1.52) (layer "F.Fab") (width 0.1) (tstamp f5a6f1fb-ef9c-40eb-a0b8-a6d75182f012))
    (pad "1" smd rect locked (at -1 -0.95 90) (size 0.9 0.8) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "LV") (pinfunction "G") (pintype "input") (tstamp 2be9e865-87a1-40bd-b52f-1a29002cac90))
    (pad "2" smd rect locked (at -1 0.95 90) (size 0.9 0.8) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 7 "/LV2") (pinfunction "S") (pintype "passive") (tstamp 2620036d-3baa-48a9-8300-9cba317f1fe8))
    (pad "3" smd rect locked (at 1 0 90) (size 0.9 0.8) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 11 "/HV2") (pinfunction "D") (pintype "passive") (tstamp 23282256-4c88-4815-8ed0-47ace3169f7e))
    (model "${KISYS3DMOD}/Package_TO_SOT_SMD.3dshapes/SOT-23.wrl"
      (offset (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )

  (footprint "Package_TO_SOT_SMD:SOT-23" (layer "F.Cu")
    (tedit 5A02FF57) (tstamp 00000000-0000-0000-0000-00005fb1c91e)
    (at 13.3604 6.2738 90)
    (descr "SOT-23, Standard")
    (tags "SOT-23")
    (property "Sheetfile" "//nas.cehq.io/Product Design/Team Workspace/Michael Ruppe/GitHub/CoreElectronics-Logic-Level-Converter-Bidirectional/PCB/CoreElectronics-Logic-Level-Converter-Bidirectional.sch")
    (property "Sheetname" "")
    (path "/00000000-0000-0000-0000-00005f3c7b27")
    (attr smd)
    (fp_text reference "Q4" (at 0 -2.5 90) (layer "F.SilkS") hide
      (effects (font (size 1 1) (thickness 0.15)))
      (tstamp 3479d095-3a11-48f9-bd95-48a086ac56d9)
    )
    (fp_text value "BSS138" (at 0 2.5 90) (layer "F.Fab")
      (effects (font (size 1 1) (thickness 0.15)))
      (tstamp aac30f28-c4f1-4e39-9b50-2de3fa3d215d)
    )
    (fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
      (effects (font (size 0.5 0.5) (thickness 0.075)))
      (tstamp e3709248-7465-4dcc-a0e8-e1c5cea987ca)
    )
    (fp_line (start 0.76 1.58) (end -0.7 1.58) (layer "F.SilkS") (width 0.12) (tstamp 9e28ef7f-4309-4ec9-9b6b-2706ba1f5827))
    (fp_line (start 0.76 -1.58) (end 0.76 -0.65) (layer "F.SilkS") (width 0.12) (tstamp b71efe8f-2fb2-484a-bc35-57dece0afe90))
    (fp_line (start 0.76 -1.58) (end -1.4 -1.58) (layer "F.SilkS") (width 0.12) (tstamp b7be4fc8-b2e0-433b-a04e-a2beaf3488e6))
    (fp_line (start 0.76 1.58) (end 0.76 0.65) (layer "F.SilkS") (width 0.12) (tstamp de143995-8ee2-4ce1-b29b-9b48bc6055ec))
    (fp_line (start -1.7 1.75) (end -1.7 -1.75) (layer "F.CrtYd") (width 0.05) (tstamp 3f61cbbb-49e7-450a-b873-7ac73165616e))
    (fp_line (start 1.7 1.75) (end -1.7 1.75) (layer "F.CrtYd") (width 0.05) (tstamp 3fcc1e0b-61d9-46a7-9593-6ae053f30c99))
    (fp_line (start -1.7 -1.75) (end 1.7 -1.75) (layer "F.CrtYd") (width 0.05) (tstamp d88b66b0-fefb-4bc0-b017-39dbb55676a0))
    (fp_line (start 1.7 -1.75) (end 1.7 1.75) (layer "F.CrtYd") (width 0.05) (tstamp e8d96983-4ed7-493a-a571-f83c723f7f12))
    (fp_line (start -0.15 -1.52) (end 0.7 -1.52) (layer "F.Fab") (width 0.1) (tstamp 1c586cd8-09b3-4f8f-9c1e-f521e08ca718))
    (fp_line (start -0.7 -0.95) (end -0.15 -1.52) (layer "F.Fab") (width 0.1) (tstamp 520eac38-db32-4add-a538-b3afce2fa7f6))
    (fp_line (start -0.7 -0.95) (end -0.7 1.5) (layer "F.Fab") (width 0.1) (tstamp 67f0aac4-f59a-433c-81f5-5cde85939903))
    (fp_line (start 0.7 -1.52) (end 0.7 1.52) (layer "F.Fab") (width 0.1) (tstamp 9cfe6825-a9a3-4db8-90c7-2140e80ad4e2))
    (fp_line (start -0.7 1.52) (end 0.7 1.52) (layer "F.Fab") (width 0.1) (tstamp dbe4d874-2590-40e7-97d8-bef26f5ead45))
    (pad "1" smd rect locked (at -1 -0.95 90) (size 0.9 0.8) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "LV") (pinfunction "G") (pintype "input") (tstamp 1a9ac330-afaa-419e-99be-ae81b2dcab38))
    (pad "2" smd rect locked (at -1 0.95 90) (size 0.9 0.8) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 3 "/LV4") (pinfunction "S") (pintype "passive") (tstamp 97a64552-cc02-4a11-a9f4-0e71fd1c7ebb))
    (pad "3" smd rect locked (at 1 0 90) (size 0.9 0.8) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 4 "/HV4") (pinfunction "D") (pintype "passive") (tstamp 4f3cfefb-504a-47ea-9fb0-ef8196f4aef9))
    (model "${KISYS3DMOD}/Package_TO_SOT_SMD.3dshapes/SOT-23.wrl"
      (offset (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )

  (footprint "Fiducial:Fiducial_0.5mm_Mask1mm" (layer "F.Cu")
    (tedit 5C18CB26) (tstamp 00000000-0000-0000-0000-00005fb1c94d)
    (at 0.635 4.826)
    (descr "Circular Fiducial, 0.5mm bare copper, 1mm soldermask opening (Level C)")
    (tags "fiducial")
    (property "Sheetfile" "//nas.cehq.io/Product Design/Team Workspace/Michael Ruppe/GitHub/CoreElectronics-Logic-Level-Converter-Bidirectional/PCB/CoreElectronics-Logic-Level-Converter-Bidirectional.sch")
    (property "Sheetname" "")
    (property "Supplier Link" "-")
    (path "/00000000-0000-0000-0000-00008182258e")
    (attr smd)
    (fp_text reference "JP2" (at 0 -1.5) (layer "F.SilkS") hide
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      (tstamp 94b96e04-ca17-452c-b800-47f22773bcb6)
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    (fp_text value "FIDUCIALUFIDUCIAL" (at -19.0754 -1.1684) (layer "F.Fab")
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      (tstamp 3bb69a72-aa09-4a68-8a82-1e869716675f)
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      (effects (font (size 0.2 0.2) (thickness 0.04)))
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    (fp_circle (center 0 0) (end 0.75 0) (layer "F.CrtYd") (width 0.05) (fill none) (tstamp b1080232-e796-4aa8-b7ef-7b66d9afcee6))
    (fp_circle (center 0 0) (end 0.5 0) (layer "F.Fab") (width 0.1) (fill none) (tstamp af301d1d-402f-40a5-814d-705654630dbf))
    (pad "" smd circle locked (at 0 0) (size 0.5 0.5) (layers "F.Cu" "F.Mask")
      (solder_mask_margin 0.25) (clearance 0.25) (tstamp 34641555-b5ec-46f2-bf99-73f9275b4bbe))
  )

  (footprint "Package_TO_SOT_SMD:SOT-23" (layer "F.Cu")
    (tedit 5A02FF57) (tstamp 00000000-0000-0000-0000-00005fb1c96f)
    (at 1.9558 6.2738 90)
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    (attr smd)
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    (pad "1" smd rect locked (at -1 -0.95 90) (size 0.9 0.8) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "LV") (pinfunction "G") (pintype "input") (tstamp be95ab76-8375-46a8-8f83-dbe6f32637f5))
    (pad "2" smd rect locked (at -1 0.95 90) (size 0.9 0.8) (layers "F.Cu" "F.Paste" "F.Mask")
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    (pad "3" smd rect locked (at 1 0 90) (size 0.9 0.8) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 6 "/HV1") (pinfunction "D") (pintype "passive") (tstamp 63cfb942-bbea-4aee-9e72-880dea5ee3c6))
    (model "${KISYS3DMOD}/Package_TO_SOT_SMD.3dshapes/SOT-23.wrl"
      (offset (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )

  (footprint "Package_TO_SOT_SMD:SOT-23" (layer "F.Cu")
    (tedit 5A02FF57) (tstamp 00000000-0000-0000-0000-00005fb1c9ab)
    (at 9.6012 6.2738 90)
    (descr "SOT-23, Standard")
    (tags "SOT-23")
    (property "Sheetfile" "//nas.cehq.io/Product Design/Team Workspace/Michael Ruppe/GitHub/CoreElectronics-Logic-Level-Converter-Bidirectional/PCB/CoreElectronics-Logic-Level-Converter-Bidirectional.sch")
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    (attr smd)
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