(kicad_pcb (version 20171130) (host pcbnew 5.1.5-52549c5~84~ubuntu19.04.1)

  (general
    (thickness 1.6)
    (drawings 22)
    (tracks 31)
    (zones 0)
    (modules 3)
    (nets 7)
  )

  (page A4)
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )

  (setup
    (last_trace_width 0.25)
    (trace_clearance 0.2)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.2)
    (via_size 0.8)
    (via_drill 0.4)
    (via_min_size 0.4)
    (via_min_drill 0.3)
    (uvia_size 0.3)
    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (edge_width 0.05)
    (segment_width 0.2)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.12)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 1.524 1.524)
    (pad_drill 0.762)
    (pad_to_mask_clearance 0.051)
    (solder_mask_min_width 0.25)
    (aux_axis_origin 0 0)
    (visible_elements FFFFFF7F)
    (pcbplotparams
      (layerselection 0x010fc_ffffffff)
      (usegerberextensions false)
      (usegerberattributes false)
      (usegerberadvancedattributes false)
      (creategerberjobfile false)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15.000000)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 0)
      (scaleselection 1)
      (outputdirectory "ilulissat_debug"))
  )

  (net 0 "")
  (net 1 VDD)
  (net 2 /SWCLK)
  (net 3 GND)
  (net 4 /SWDIO)
  (net 5 /UART_RX)
  (net 6 /UART_TX)

  (net_class Default "This is the default net class."
    (clearance 0.2)
    (trace_width 0.25)
    (via_dia 0.8)
    (via_drill 0.4)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
    (add_net /SWCLK)
    (add_net /SWDIO)
    (add_net /UART_RX)
    (add_net /UART_TX)
    (add_net GND)
    (add_net VDD)
  )

  (module Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5E48F05E)
    (at 155.2 93.5 90)
    (descr "Through hole straight pin header, 1x04, 2.54mm pitch, single row")
    (tags "Through hole pin header THT 1x04 2.54mm single row")
    (path /5E48A1C5)
    (fp_text reference J3 (at 0 -2.33 90) (layer F.SilkS)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_text value Conn_01x04 (at 0 9.95 90) (layer F.Fab)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_text user %R (at 0 3.81) (layer F.Fab)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
    (fp_line (start 1.8 9.4) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
    (fp_line (start -1.8 9.4) (end 1.8 9.4) (layer F.CrtYd) (width 0.05))
    (fp_line (start -1.8 -1.8) (end -1.8 9.4) (layer F.CrtYd) (width 0.05))
    (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
    (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
    (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
    (fp_line (start 1.33 1.27) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
    (fp_line (start -1.33 1.27) (end -1.33 8.95) (layer F.SilkS) (width 0.12))
    (fp_line (start -1.33 8.95) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
    (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
    (fp_line (start -1.27 8.89) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
    (fp_line (start 1.27 8.89) (end -1.27 8.89) (layer F.Fab) (width 0.1))
    (fp_line (start 1.27 -1.27) (end 1.27 8.89) (layer F.Fab) (width 0.1))
    (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
    (pad 4 thru_hole oval (at 0 7.62 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 3 GND))
    (pad 3 thru_hole oval (at 0 5.08 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 VDD))
    (pad 2 thru_hole oval (at 0 2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 5 /UART_RX))
    (pad 1 thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 6 /UART_TX))
    (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x04_P2.54mm_Vertical.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )

  (module Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5E48F0A3)
    (at 162.8 112.525 270)
    (descr "Through hole straight pin header, 1x04, 2.54mm pitch, single row")
    (tags "Through hole pin header THT 1x04 2.54mm single row")
    (path /5E48B193)
    (fp_text reference J2 (at 0 -2.33 90) (layer F.SilkS)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_text value Conn_01x04 (at 0 9.95 90) (layer F.Fab)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_text user %R (at 0 3.81) (layer F.Fab)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
    (fp_line (start 1.8 9.4) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
    (fp_line (start -1.8 9.4) (end 1.8 9.4) (layer F.CrtYd) (width 0.05))
    (fp_line (start -1.8 -1.8) (end -1.8 9.4) (layer F.CrtYd) (width 0.05))
    (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
    (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
    (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
    (fp_line (start 1.33 1.27) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
    (fp_line (start -1.33 1.27) (end -1.33 8.95) (layer F.SilkS) (width 0.12))
    (fp_line (start -1.33 8.95) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
    (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
    (fp_line (start -1.27 8.89) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
    (fp_line (start 1.27 8.89) (end -1.27 8.89) (layer F.Fab) (width 0.1))
    (fp_line (start 1.27 -1.27) (end 1.27 8.89) (layer F.Fab) (width 0.1))
    (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
    (pad 4 thru_hole oval (at 0 7.62 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 VDD))
    (pad 3 thru_hole oval (at 0 5.08 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 2 /SWCLK))
    (pad 2 thru_hole oval (at 0 2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 3 GND))
    (pad 1 thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 4 /SWDIO))
    (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x04_P2.54mm_Vertical.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )

  (module Connector_PinSocket_1.27mm:PinSocket_1x06_P1.27mm_Vertical (layer B.Cu) (tedit 5A19A420) (tstamp 5E48F19A)
    (at 147 100 180)
    (descr "Through hole straight socket strip, 1x06, 1.27mm pitch, single row (from Kicad 4.0.7), script generated")
    (tags "Through hole socket strip THT 1x06 1.27mm single row")
    (path /5E489C5B)
    (fp_text reference J1 (at 0 2.135) (layer B.SilkS)
      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
    )
    (fp_text value Conn_01x06 (at 0 -8.485) (layer B.Fab)
      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
    )
    (fp_text user %R (at 0 -3.175 270) (layer B.Fab)
      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
    )
    (fp_line (start -1.8 -7.5) (end -1.8 1.15) (layer B.CrtYd) (width 0.05))
    (fp_line (start 1.75 -7.5) (end -1.8 -7.5) (layer B.CrtYd) (width 0.05))
    (fp_line (start 1.75 1.15) (end 1.75 -7.5) (layer B.CrtYd) (width 0.05))
    (fp_line (start -1.8 1.15) (end 1.75 1.15) (layer B.CrtYd) (width 0.05))
    (fp_line (start 0 0.76) (end 1.33 0.76) (layer B.SilkS) (width 0.12))
    (fp_line (start 1.33 0.76) (end 1.33 0) (layer B.SilkS) (width 0.12))
    (fp_line (start 1.33 -0.635) (end 1.33 -7.045) (layer B.SilkS) (width 0.12))
    (fp_line (start 0.30753 -7.045) (end 1.33 -7.045) (layer B.SilkS) (width 0.12))
    (fp_line (start -1.33 -7.045) (end -0.30753 -7.045) (layer B.SilkS) (width 0.12))
    (fp_line (start -1.33 -0.635) (end -1.33 -7.045) (layer B.SilkS) (width 0.12))
    (fp_line (start 0.76 -0.635) (end 1.33 -0.635) (layer B.SilkS) (width 0.12))
    (fp_line (start -1.33 -0.635) (end -0.76 -0.635) (layer B.SilkS) (width 0.12))
    (fp_line (start -1.27 -6.985) (end -1.27 0.635) (layer B.Fab) (width 0.1))
    (fp_line (start 1.27 -6.985) (end -1.27 -6.985) (layer B.Fab) (width 0.1))
    (fp_line (start 1.27 0) (end 1.27 -6.985) (layer B.Fab) (width 0.1))
    (fp_line (start 0.635 0.635) (end 1.27 0) (layer B.Fab) (width 0.1))
    (fp_line (start -1.27 0.635) (end 0.635 0.635) (layer B.Fab) (width 0.1))
    (pad 6 thru_hole oval (at 0 -6.35 180) (size 1 1) (drill 0.7) (layers *.Cu *.Mask)
      (net 1 VDD))
    (pad 5 thru_hole oval (at 0 -5.08 180) (size 1 1) (drill 0.7) (layers *.Cu *.Mask)
      (net 2 /SWCLK))
    (pad 4 thru_hole oval (at 0 -3.81 180) (size 1 1) (drill 0.7) (layers *.Cu *.Mask)
      (net 3 GND))
    (pad 3 thru_hole oval (at 0 -2.54 180) (size 1 1) (drill 0.7) (layers *.Cu *.Mask)
      (net 4 /SWDIO))
    (pad 2 thru_hole oval (at 0 -1.27 180) (size 1 1) (drill 0.7) (layers *.Cu *.Mask)
      (net 5 /UART_RX))
    (pad 1 thru_hole rect (at 0 0 180) (size 1 1) (drill 0.7) (layers *.Cu *.Mask)
      (net 6 /UART_TX))
    (model ${KISYS3DMOD}/Connector_PinSocket_1.27mm.3dshapes/PinSocket_1x06_P1.27mm_Vertical.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )

  (gr_line (start 149.5 107.5) (end 145.2 107.5) (layer Edge.Cuts) (width 0.05) (tstamp 5E48F5CD))
  (gr_line (start 153.4 114.325) (end 149.5 107.5) (layer Edge.Cuts) (width 0.05))
  (gr_line (start 164.6 114.325) (end 153.4 114.325) (layer Edge.Cuts) (width 0.05))
  (gr_line (start 164.6 91.7) (end 164.6 114.325) (layer Edge.Cuts) (width 0.05))
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  (gr_text 3.3V (at 155.05 108.994048 90) (layer F.SilkS)
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  (gr_text "SWCLK\n" (at 157.658333 108.160714 90) (layer F.SilkS)
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  )
  (gr_text GND (at 160.266666 109.089286 90) (layer F.SilkS)
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  )
  (gr_text SWDIO (at 162.875 108.303571 90) (layer F.SilkS)
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  )
  (gr_text UART_TX (at 155.125 98.225 90) (layer F.SilkS)
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  )
  (gr_text UART_RX (at 157.783333 98.344047 90) (layer F.SilkS)
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