ST PM0214 Rev10 March2020, exception states, vector table, priorities, grouping and exception entry/return:
https://www.st.com/resource/en/programming_manual/pm0214-stm32-cortexm4-mcus-and-mpus-programming-manual-stmicroelectronics.pdf
ST DS9118 Rev14:
https://www.st.com/resource/en/datasheet/stm32f303cb.pdf
Board visually inspected V2.0: PB6physical42 PB7physical43, both exposed, PB6active-HIGH NPN LED circuit:
https://gebrabit.com/wp-content/uploads/2024/07/GebraBit-STM32F303-Schematic-V2.0.pdf
HAL pinned953955afe65f89e60e556bbcdba752597f5da65d:
https://github.com/STMicroelectronics/stm32f3xx_hal_driver/tree/953955afe65f89e60e556bbcdba752597f5da65d
Exact device header defines4prioritybits and EXTI0IRQ6/EXTI1IRQ7. Actual ELF inspection verifies strong application handler pointers in exception22/23. No EXTI line is physically configured.


## Inspected official STM32CubeF3 V1.11.6 examples
Projects/STM32F3-Discovery/Examples/GPIO/GPIO_EXTI/Src/main.c
https://github.com/STMicroelectronics/STM32CubeF3/blob/663d2baae3604244f90ed80d0d757df17e36ada9/Projects/STM32F3-Discovery/Examples/GPIO/GPIO_EXTI/Src/main.c
Projects/STM32303C_EVAL/Examples/Cortex/CORTEXM_SysTick/Src/main.c
https://github.com/STMicroelectronics/STM32CubeF3/blob/663d2baae3604244f90ed80d0d757df17e36ada9/Projects/STM32303C_EVAL/Examples/Cortex/CORTEXM_SysTick/Src/main.c
Relevant source snippets were actually inspected. GPIO_EXTI demonstrates HAL priority setup, NVIC enable and the IRQ/callback route on Discovery PA0; this lesson instead uses original software-pended EXTI0/EXTI1 vectors with no physical EXTI line. Cortex SysTick confirms the HSEPLL72 baseline, not a two-IRQ preemption demonstration. Board-specific BSP mappings and the original GPIO busy-loop debounce were not copied.
