{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1697779655261 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1697779655337 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 20 13:27:34 2023 " "Processing started: Fri Oct 20 13:27:34 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1697779655337 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1697779655337 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off bus2627 -c bus2627 " "Command: quartus_map --read_settings_files=on --write_settings_files=off bus2627 -c bus2627" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1697779655337 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1697779657037 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1697779657037 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lpm_mux0.v 1 1 " "Found 1 design units, including 1 entities, in source file lpm_mux0.v" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux0 " "Found entity 1: lpm_mux0" {  } { { "lpm_mux0.v" "" { Text "D:/Projects/quartus/bus/lpm_mux0.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1697779676454 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1697779676454 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bus2627.bdf 1 1 " "Found 1 design units, including 1 entities, in source file bus2627.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 bus2627 " "Found entity 1: bus2627" {  } { { "bus2627.bdf" "" { Schematic "D:/Projects/quartus/bus/bus2627.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1697779676457 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1697779676457 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "bus2627 " "Elaborating entity \"bus2627\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1697779676705 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mux0 lpm_mux0:MUX " "Elaborating entity \"lpm_mux0\" for hierarchy \"lpm_mux0:MUX\"" {  } { { "bus2627.bdf" "MUX" { Schematic "D:/Projects/quartus/bus/bus2627.bdf" { { 184 688 832 296 "MUX" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697779676734 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mux lpm_mux0:MUX\|lpm_mux:LPM_MUX_component " "Elaborating entity \"lpm_mux\" for hierarchy \"lpm_mux0:MUX\|lpm_mux:LPM_MUX_component\"" {  } { { "lpm_mux0.v" "LPM_MUX_component" { Text "D:/Projects/quartus/bus/lpm_mux0.v" 72 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697779676920 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux0:MUX\|lpm_mux:LPM_MUX_component " "Elaborated megafunction instantiation \"lpm_mux0:MUX\|lpm_mux:LPM_MUX_component\"" {  } { { "lpm_mux0.v" "" { Text "D:/Projects/quartus/bus/lpm_mux0.v" 72 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697779676929 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mux0:MUX\|lpm_mux:LPM_MUX_component " "Instantiated megafunction \"lpm_mux0:MUX\|lpm_mux:LPM_MUX_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_size 4 " "Parameter \"lpm_size\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1697779676929 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_MUX " "Parameter \"lpm_type\" = \"LPM_MUX\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1697779676929 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1697779676929 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widths 2 " "Parameter \"lpm_widths\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1697779676929 ""}  } { { "lpm_mux0.v" "" { Text "D:/Projects/quartus/bus/lpm_mux0.v" 72 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1697779676929 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_hrc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_hrc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_hrc " "Found entity 1: mux_hrc" {  } { { "db/mux_hrc.tdf" "" { Text "D:/Projects/quartus/bus/db/mux_hrc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1697779677058 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1697779677058 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_hrc lpm_mux0:MUX\|lpm_mux:LPM_MUX_component\|mux_hrc:auto_generated " "Elaborating entity \"mux_hrc\" for hierarchy \"lpm_mux0:MUX\|lpm_mux:LPM_MUX_component\|mux_hrc:auto_generated\"" {  } { { "lpm_mux.tdf" "auto_generated" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_mux.tdf" 86 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697779677058 ""}
{ "Warning" "WSGN_SEARCH_FILE" "reg8.bdf 1 1 " "Using design file reg8.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Reg8 " "Found entity 1: Reg8" {  } { { "reg8.bdf" "" { Schematic "D:/Projects/quartus/bus/reg8.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1697779677104 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1697779677104 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Reg8 Reg8:R0 " "Elaborating entity \"Reg8\" for hierarchy \"Reg8:R0\"" {  } { { "bus2627.bdf" "R0" { Schematic "D:/Projects/quartus/bus/bus2627.bdf" { { 80 416 552 176 "R0" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697779677104 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_RAM_DQ LPM_RAM_DQ:RAM " "Elaborating entity \"LPM_RAM_DQ\" for hierarchy \"LPM_RAM_DQ:RAM\"" {  } { { "bus2627.bdf" "RAM" { Schematic "D:/Projects/quartus/bus/bus2627.bdf" { { 336 424 544 448 "RAM" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697779677489 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "LPM_RAM_DQ:RAM " "Elaborated megafunction instantiation \"LPM_RAM_DQ:RAM\"" {  } { { "bus2627.bdf" "" { Schematic "D:/Projects/quartus/bus/bus2627.bdf" { { 336 424 544 448 "RAM" "" } } } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697779677496 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "LPM_RAM_DQ:RAM " "Instantiated megafunction \"LPM_RAM_DQ:RAM\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_OUTDATA UNREGISTERED " "Parameter \"LPM_OUTDATA\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1697779677497 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1697779677497 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHAD 8 " "Parameter \"LPM_WIDTHAD\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1697779677497 ""}  } { { "bus2627.bdf" "" { Schematic "D:/Projects/quartus/bus/bus2627.bdf" { { 336 424 544 448 "RAM" "" } } } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1697779677497 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altram LPM_RAM_DQ:RAM\|altram:sram " "Elaborating entity \"altram\" for hierarchy \"LPM_RAM_DQ:RAM\|altram:sram\"" {  } { { "lpm_ram_dq.tdf" "sram" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 75 6 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697779677551 ""}
{ "Warning" "WTDFX_ASSERTION" "altram does not support Cyclone IV E device family -- attempting best-case memory conversions, but power-up states and read during write behavior will be different for Cyclone IV E devices " "Assertion warning: altram does not support Cyclone IV E device family -- attempting best-case memory conversions, but power-up states and read during write behavior will be different for Cyclone IV E devices" {  } { { "altram.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altram.tdf" 211 2 0 } } { "lpm_ram_dq.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 75 6 0 } } { "bus2627.bdf" "" { Schematic "D:/Projects/quartus/bus/bus2627.bdf" { { 336 424 544 448 "RAM" "" } } } }  } 0 287001 "Assertion warning: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1697779677564 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "LPM_RAM_DQ:RAM\|altram:sram LPM_RAM_DQ:RAM " "Elaborated megafunction instantiation \"LPM_RAM_DQ:RAM\|altram:sram\", which is child of megafunction instantiation \"LPM_RAM_DQ:RAM\"" {  } { { "lpm_ram_dq.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 75 6 0 } } { "bus2627.bdf" "" { Schematic "D:/Projects/quartus/bus/bus2627.bdf" { { 336 424 544 448 "RAM" "" } } } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697779677565 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram LPM_RAM_DQ:RAM\|altram:sram\|altsyncram:ram_block " "Elaborating entity \"altsyncram\" for hierarchy \"LPM_RAM_DQ:RAM\|altram:sram\|altsyncram:ram_block\"" {  } { { "altram.tdf" "ram_block" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altram.tdf" 102 5 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697779677652 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "LPM_RAM_DQ:RAM\|altram:sram\|altsyncram:ram_block LPM_RAM_DQ:RAM " "Elaborated megafunction instantiation \"LPM_RAM_DQ:RAM\|altram:sram\|altsyncram:ram_block\", which is child of megafunction instantiation \"LPM_RAM_DQ:RAM\"" {  } { { "altram.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altram.tdf" 102 5 0 } } { "bus2627.bdf" "" { Schematic "D:/Projects/quartus/bus/bus2627.bdf" { { 336 424 544 448 "RAM" "" } } } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697779677687 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_ap71.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_ap71.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_ap71 " "Found entity 1: altsyncram_ap71" {  } { { "db/altsyncram_ap71.tdf" "" { Text "D:/Projects/quartus/bus/db/altsyncram_ap71.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1697779677834 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1697779677834 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_ap71 LPM_RAM_DQ:RAM\|altram:sram\|altsyncram:ram_block\|altsyncram_ap71:auto_generated " "Elaborating entity \"altsyncram_ap71\" for hierarchy \"LPM_RAM_DQ:RAM\|altram:sram\|altsyncram:ram_block\|altsyncram_ap71:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697779677836 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1697779678900 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1697779680042 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697779680042 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "79 " "Implemented 79 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "15 " "Implemented 15 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1697779680491 ""} { "Info" "ICUT_CUT_TM_OPINS" "16 " "Implemented 16 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1697779680491 ""} { "Info" "ICUT_CUT_TM_LCELLS" "40 " "Implemented 40 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1697779680491 ""} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Implemented 8 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1697779680491 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1697779680491 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4842 " "Peak virtual memory: 4842 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1697779680513 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 20 13:28:00 2023 " "Processing ended: Fri Oct 20 13:28:00 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1697779680513 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:26 " "Elapsed time: 00:00:26" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1697779680513 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:46 " "Total CPU time (on all processors): 00:00:46" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1697779680513 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1697779680513 ""}