// Copyright (C) 2017  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "10/20/2023 13:29:28"
                                                                                
// Verilog Test Bench (with test vectors) for design :                          bus2627
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module bus2627_vlg_vec_tst();
// constants                                           
// general purpose registers
reg CLK1;
reg CLK2;
reg CLK3;
reg CLK4;
reg [7:0] d0;
reg [1:0] SELECT;
reg we;
// wires                                               
wire [7:0] bus;
wire [7:0] led;

// assign statements (if any)                          
bus2627 i1 (
// port map - connection between master ports and signals/registers   
	.bus(bus),
	.CLK1(CLK1),
	.CLK2(CLK2),
	.CLK3(CLK3),
	.CLK4(CLK4),
	.d0(d0),
	.led(led),
	.SELECT(SELECT),
	.we(we)
);
initial 
begin 
#320000 $finish;
end 
// d0[ 7 ]
initial
begin
	d0[7] = 1'b0;
end 
// d0[ 6 ]
initial
begin
	d0[6] = 1'b0;
end 
// d0[ 5 ]
initial
begin
	d0[5] = 1'b0;
end 
// d0[ 4 ]
initial
begin
	d0[4] = 1'b0;
end 
// d0[ 3 ]
initial
begin
	d0[3] = 1'b0;
end 
// d0[ 2 ]
initial
begin
	d0[2] = 1'b0;
end 
// d0[ 1 ]
initial
begin
	d0[1] = 1'b0;
	d0[1] = #50000 1'b1;
	d0[1] = #40000 1'b0;
end 
// d0[ 0 ]
initial
begin
	d0[0] = 1'b1;
	d0[0] = #50000 1'b0;
end 
// SELECT[ 1 ]
initial
begin
	SELECT[1] = 1'b0;
	SELECT[1] = #120000 1'b1;
end 
// SELECT[ 0 ]
initial
begin
	SELECT[0] = 1'b0;
	SELECT[0] = #90000 1'b1;
	SELECT[0] = #30000 1'b0;
end 

// CLK1
initial
begin
	CLK1 = 1'b0;
	CLK1 = #10000 1'b1;
	CLK1 = #10000 1'b0;
end 

// CLK2
initial
begin
	CLK2 = 1'b0;
	CLK2 = #60000 1'b1;
	CLK2 = #10000 1'b0;
end 

// CLK3
initial
begin
	CLK3 = 1'b0;
	CLK3 = #100000 1'b1;
	CLK3 = #10000 1'b0;
	CLK3 = #20000 1'b1;
	CLK3 = #10000 1'b0;
end 

// we
initial
begin
	we = 1'b0;
	we = #100000 1'b1;
	we = #10000 1'b0;
end 

// CLK4
initial
begin
	CLK4 = 1'b0;
	CLK4 = #170000 1'b1;
	CLK4 = #10000 1'b0;
end 
endmodule