vendor_name = ModelSim
source_file = 1, D:/Projects/quartus/bus/lpm_mux0.qip
source_file = 1, D:/Projects/quartus/bus/lpm_mux0.v
source_file = 1, D:/Projects/quartus/bus/bus2627.bdf
source_file = 1, D:/Projects/quartus/bus/Waveform.vwf
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_mux.tdf
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/aglobal171.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/muxlut.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/bypassff.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altshift.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/cbx.lst
source_file = 1, D:/Projects/quartus/bus/db/mux_hrc.tdf
source_file = 1, D:/Projects/quartus/bus/reg8.bdf
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_ram_dq.tdf
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altram.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_mux.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_decode.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altram.tdf
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/others/maxplus2/memmodes.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altsyncram.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altsyncram.tdf
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/stratix_ram_block.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/a_rdenreg.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altrom.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altdpram.inc
source_file = 1, D:/Projects/quartus/bus/db/altsyncram_ap71.tdf
design_name = bus2627
instance = comp, \bus[7]~output , bus[7]~output, bus2627, 1
instance = comp, \bus[6]~output , bus[6]~output, bus2627, 1
instance = comp, \bus[5]~output , bus[5]~output, bus2627, 1
instance = comp, \bus[4]~output , bus[4]~output, bus2627, 1
instance = comp, \bus[3]~output , bus[3]~output, bus2627, 1
instance = comp, \bus[2]~output , bus[2]~output, bus2627, 1
instance = comp, \bus[1]~output , bus[1]~output, bus2627, 1
instance = comp, \bus[0]~output , bus[0]~output, bus2627, 1
instance = comp, \led[7]~output , led[7]~output, bus2627, 1
instance = comp, \led[6]~output , led[6]~output, bus2627, 1
instance = comp, \led[5]~output , led[5]~output, bus2627, 1
instance = comp, \led[4]~output , led[4]~output, bus2627, 1
instance = comp, \led[3]~output , led[3]~output, bus2627, 1
instance = comp, \led[2]~output , led[2]~output, bus2627, 1
instance = comp, \led[1]~output , led[1]~output, bus2627, 1
instance = comp, \led[0]~output , led[0]~output, bus2627, 1
instance = comp, \CLK1~input , CLK1~input, bus2627, 1
instance = comp, \R0|12~feeder , R0|12~feeder, bus2627, 1
instance = comp, \R0|12 , R0|12, bus2627, 1
instance = comp, \SELECT[0]~input , SELECT[0]~input, bus2627, 1
instance = comp, \d0[7]~input , d0[7]~input, bus2627, 1
instance = comp, \we~input , we~input, bus2627, 1
instance = comp, \CLK3~input , CLK3~input, bus2627, 1
instance = comp, \SELECT[1]~input , SELECT[1]~input, bus2627, 1
instance = comp, \CLK2~input , CLK2~input, bus2627, 1
instance = comp, \CLK2~inputclkctrl , CLK2~inputclkctrl, bus2627, 1
instance = comp, \AR|19~feeder , AR|19~feeder, bus2627, 1
instance = comp, \AR|19 , AR|19, bus2627, 1
instance = comp, \R0|18~feeder , R0|18~feeder, bus2627, 1
instance = comp, \R0|18 , R0|18, bus2627, 1
instance = comp, \d0[1]~input , d0[1]~input, bus2627, 1
instance = comp, \R0|16~feeder , R0|16~feeder, bus2627, 1
instance = comp, \R0|16 , R0|16, bus2627, 1
instance = comp, \d0[3]~input , d0[3]~input, bus2627, 1
instance = comp, \R0|14~feeder , R0|14~feeder, bus2627, 1
instance = comp, \R0|14 , R0|14, bus2627, 1
instance = comp, \d0[5]~input , d0[5]~input, bus2627, 1
instance = comp, \AR|12~feeder , AR|12~feeder, bus2627, 1
instance = comp, \AR|12 , AR|12, bus2627, 1
instance = comp, \RAM|sram|ram_block|auto_generated|ram_block1a0 , RAM|sram|ram_block|auto_generated|ram_block1a0, bus2627, 1
instance = comp, \d0[6]~input , d0[6]~input, bus2627, 1
instance = comp, \R0|13~feeder , R0|13~feeder, bus2627, 1
instance = comp, \R0|13 , R0|13, bus2627, 1
instance = comp, \MUX|LPM_MUX_component|auto_generated|result_node[6]~2 , MUX|LPM_MUX_component|auto_generated|result_node[6]~2, bus2627, 1
instance = comp, \MUX|LPM_MUX_component|auto_generated|result_node[6]~3 , MUX|LPM_MUX_component|auto_generated|result_node[6]~3, bus2627, 1
instance = comp, \AR|13~feeder , AR|13~feeder, bus2627, 1
instance = comp, \AR|13 , AR|13, bus2627, 1
instance = comp, \MUX|LPM_MUX_component|auto_generated|result_node[5]~4 , MUX|LPM_MUX_component|auto_generated|result_node[5]~4, bus2627, 1
instance = comp, \MUX|LPM_MUX_component|auto_generated|result_node[5]~5 , MUX|LPM_MUX_component|auto_generated|result_node[5]~5, bus2627, 1
instance = comp, \AR|14~feeder , AR|14~feeder, bus2627, 1
instance = comp, \AR|14 , AR|14, bus2627, 1
instance = comp, \d0[4]~input , d0[4]~input, bus2627, 1
instance = comp, \R0|15~feeder , R0|15~feeder, bus2627, 1
instance = comp, \R0|15 , R0|15, bus2627, 1
instance = comp, \MUX|LPM_MUX_component|auto_generated|result_node[4]~6 , MUX|LPM_MUX_component|auto_generated|result_node[4]~6, bus2627, 1
instance = comp, \MUX|LPM_MUX_component|auto_generated|result_node[4]~7 , MUX|LPM_MUX_component|auto_generated|result_node[4]~7, bus2627, 1
instance = comp, \AR|15~feeder , AR|15~feeder, bus2627, 1
instance = comp, \AR|15 , AR|15, bus2627, 1
instance = comp, \MUX|LPM_MUX_component|auto_generated|result_node[3]~8 , MUX|LPM_MUX_component|auto_generated|result_node[3]~8, bus2627, 1
instance = comp, \MUX|LPM_MUX_component|auto_generated|result_node[3]~9 , MUX|LPM_MUX_component|auto_generated|result_node[3]~9, bus2627, 1
instance = comp, \AR|16~feeder , AR|16~feeder, bus2627, 1
instance = comp, \AR|16 , AR|16, bus2627, 1
instance = comp, \d0[2]~input , d0[2]~input, bus2627, 1
instance = comp, \R0|17~feeder , R0|17~feeder, bus2627, 1
instance = comp, \R0|17 , R0|17, bus2627, 1
instance = comp, \MUX|LPM_MUX_component|auto_generated|result_node[2]~10 , MUX|LPM_MUX_component|auto_generated|result_node[2]~10, bus2627, 1
instance = comp, \MUX|LPM_MUX_component|auto_generated|result_node[2]~11 , MUX|LPM_MUX_component|auto_generated|result_node[2]~11, bus2627, 1
instance = comp, \AR|17~feeder , AR|17~feeder, bus2627, 1
instance = comp, \AR|17 , AR|17, bus2627, 1
instance = comp, \MUX|LPM_MUX_component|auto_generated|result_node[1]~12 , MUX|LPM_MUX_component|auto_generated|result_node[1]~12, bus2627, 1
instance = comp, \MUX|LPM_MUX_component|auto_generated|result_node[1]~13 , MUX|LPM_MUX_component|auto_generated|result_node[1]~13, bus2627, 1
instance = comp, \AR|18~feeder , AR|18~feeder, bus2627, 1
instance = comp, \AR|18 , AR|18, bus2627, 1
instance = comp, \d0[0]~input , d0[0]~input, bus2627, 1
instance = comp, \R0|19~feeder , R0|19~feeder, bus2627, 1
instance = comp, \R0|19 , R0|19, bus2627, 1
instance = comp, \MUX|LPM_MUX_component|auto_generated|result_node[0]~14 , MUX|LPM_MUX_component|auto_generated|result_node[0]~14, bus2627, 1
instance = comp, \MUX|LPM_MUX_component|auto_generated|result_node[0]~15 , MUX|LPM_MUX_component|auto_generated|result_node[0]~15, bus2627, 1
instance = comp, \MUX|LPM_MUX_component|auto_generated|result_node[7]~0 , MUX|LPM_MUX_component|auto_generated|result_node[7]~0, bus2627, 1
instance = comp, \MUX|LPM_MUX_component|auto_generated|result_node[7]~1 , MUX|LPM_MUX_component|auto_generated|result_node[7]~1, bus2627, 1
instance = comp, \CLK4~input , CLK4~input, bus2627, 1
instance = comp, \LED0|12~feeder , LED0|12~feeder, bus2627, 1
instance = comp, \LED0|12 , LED0|12, bus2627, 1
instance = comp, \LED0|13~feeder , LED0|13~feeder, bus2627, 1
instance = comp, \LED0|13 , LED0|13, bus2627, 1
instance = comp, \LED0|14~feeder , LED0|14~feeder, bus2627, 1
instance = comp, \LED0|14 , LED0|14, bus2627, 1
instance = comp, \LED0|15~feeder , LED0|15~feeder, bus2627, 1
instance = comp, \LED0|15 , LED0|15, bus2627, 1
instance = comp, \LED0|16~feeder , LED0|16~feeder, bus2627, 1
instance = comp, \LED0|16 , LED0|16, bus2627, 1
instance = comp, \LED0|17~feeder , LED0|17~feeder, bus2627, 1
instance = comp, \LED0|17 , LED0|17, bus2627, 1
instance = comp, \LED0|18~feeder , LED0|18~feeder, bus2627, 1
instance = comp, \LED0|18 , LED0|18, bus2627, 1
instance = comp, \LED0|19~feeder , LED0|19~feeder, bus2627, 1
instance = comp, \LED0|19 , LED0|19, bus2627, 1
design_name = hard_block
instance = comp, \~ALTERA_ASDO_DATA1~~ibuf , ~ALTERA_ASDO_DATA1~~ibuf, hard_block, 1
instance = comp, \~ALTERA_FLASH_nCE_nCSO~~ibuf , ~ALTERA_FLASH_nCE_nCSO~~ibuf, hard_block, 1
instance = comp, \~ALTERA_DATA0~~ibuf , ~ALTERA_DATA0~~ibuf, hard_block, 1