{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1699233496167 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1699233496175 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 06 09:18:16 2023 " "Processing started: Mon Nov 06 09:18:16 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1699233496175 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1699233496175 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off mux21a2627 -c mux21a2627 " "Command: quartus_map --read_settings_files=on --write_settings_files=off mux21a2627 -c mux21a2627" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1699233496175 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1699233496469 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1699233496469 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lpm_mux1.v 1 1 " "Found 1 design units, including 1 entities, in source file lpm_mux1.v" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux1 " "Found entity 1: lpm_mux1" { } { { "lpm_mux1.v" "" { Text "D:/Projects/quartus/computer/lpm_mux1.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1699233504657 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1699233504657 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lpm_counter0.v 1 1 " "Found 1 design units, including 1 entities, in source file lpm_counter0.v" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter0 " "Found entity 1: lpm_counter0" { } { { "lpm_counter0.v" "" { Text "D:/Projects/quartus/computer/lpm_counter0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1699233504659 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1699233504659 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mux21a2627.bdf 1 1 " "Found 1 design units, including 1 entities, in source file mux21a2627.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux21a2627 " "Found entity 1: mux21a2627" { } { { "mux21a2627.bdf" "" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1699233504661 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1699233504661 ""} { "Info" "ISGN_START_ELABORATION_TOP" "mux21a2627 " "Elaborating entity \"mux21a2627\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1699233504689 ""} { "Warning" "WSGN_SEARCH_FILE" "decodeb.bdf 1 1 " "Using design file decodeb.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 decodeb " "Found entity 1: decodeb" { } { { "decodeb.bdf" "" { Schematic "D:/Projects/quartus/computer/decodeb.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1699233504724 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1699233504724 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "decodeb decodeb:inst5 " "Elaborating entity \"decodeb\" for hierarchy \"decodeb:inst5\"" { } { { "mux21a2627.bdf" "inst5" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -688 1472 1584 -560 "inst5" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233504725 ""} { "Warning" "WSGN_SEARCH_FILE" "lpm_rom0.bdf 1 1 " "Using design file lpm_rom0.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom0 " "Found entity 1: lpm_rom0" { } { { "lpm_rom0.bdf" "" { Schematic "D:/Projects/quartus/computer/lpm_rom0.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1699233504742 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1699233504742 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom0 lpm_rom0:inst9 " "Elaborating entity \"lpm_rom0\" for hierarchy \"lpm_rom0:inst9\"" { } { { "mux21a2627.bdf" "inst9" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -368 1160 1352 -272 "inst9" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233504742 ""} { "Warning" "WGDFX_UNRESOLVED_PARAMETER" "LPM_FILE lpm_rom0.hex " "Can't find a definition for parameter LPM_FILE -- assuming lpm_rom0.hex was intended to be a quoted string" { } { { "lpm_rom0.bdf" "" { Schematic "D:/Projects/quartus/computer/lpm_rom0.bdf" { { 216 480 592 312 "inst" "" } } } } } 0 275006 "Can't find a definition for parameter %1!s! -- assuming %2!s! was intended to be a quoted string" 0 0 "Analysis & Synthesis" 0 -1 1699233504743 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_ROM lpm_rom0:inst9\|LPM_ROM:inst " "Elaborating entity \"LPM_ROM\" for hierarchy \"lpm_rom0:inst9\|LPM_ROM:inst\"" { } { { "lpm_rom0.bdf" "inst" { Schematic "D:/Projects/quartus/computer/lpm_rom0.bdf" { { 216 480 592 312 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233504770 ""} { "Info" "ISGN_ELABORATION_HEADER" "lpm_rom0:inst9\|LPM_ROM:inst " "Elaborated megafunction instantiation \"lpm_rom0:inst9\|LPM_ROM:inst\"" { } { { "lpm_rom0.bdf" "" { Schematic "D:/Projects/quartus/computer/lpm_rom0.bdf" { { 216 480 592 312 "inst" "" } } } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233504776 ""} { "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_rom0:inst9\|LPM_ROM:inst " "Instantiated megafunction \"lpm_rom0:inst9\|LPM_ROM:inst\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_FILE lpm_rom0.hex " "Parameter \"LPM_FILE\" = \"lpm_rom0.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1699233504777 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_OUTDATA UNREGISTERED " "Parameter \"LPM_OUTDATA\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1699233504777 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 24 " "Parameter \"LPM_WIDTH\" = \"24\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1699233504777 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHAD 6 " "Parameter \"LPM_WIDTHAD\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1699233504777 ""} } { { "lpm_rom0.bdf" "" { Schematic "D:/Projects/quartus/computer/lpm_rom0.bdf" { { 216 480 592 312 "inst" "" } } } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1699233504777 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom lpm_rom0:inst9\|LPM_ROM:inst\|altrom:srom " "Elaborating entity \"altrom\" for hierarchy \"lpm_rom0:inst9\|LPM_ROM:inst\|altrom:srom\"" { } { { "lpm_rom.tdf" "srom" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 54 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233504829 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_rom0:inst9\|LPM_ROM:inst\|altrom:srom lpm_rom0:inst9\|LPM_ROM:inst " "Elaborated megafunction instantiation \"lpm_rom0:inst9\|LPM_ROM:inst\|altrom:srom\", which is child of megafunction instantiation \"lpm_rom0:inst9\|LPM_ROM:inst\"" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 54 3 0 } } { "lpm_rom0.bdf" "" { Schematic "D:/Projects/quartus/computer/lpm_rom0.bdf" { { 216 480 592 312 "inst" "" } } } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233504840 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram lpm_rom0:inst9\|LPM_ROM:inst\|altrom:srom\|altsyncram:rom_block " "Elaborating entity \"altsyncram\" for hierarchy \"lpm_rom0:inst9\|LPM_ROM:inst\|altrom:srom\|altsyncram:rom_block\"" { } { { "altrom.tdf" "rom_block" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altrom.tdf" 88 6 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233504908 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_rom0:inst9\|LPM_ROM:inst\|altrom:srom\|altsyncram:rom_block lpm_rom0:inst9\|LPM_ROM:inst " "Elaborated megafunction instantiation \"lpm_rom0:inst9\|LPM_ROM:inst\|altrom:srom\|altsyncram:rom_block\", which is child of megafunction instantiation \"lpm_rom0:inst9\|LPM_ROM:inst\"" { } { { "altrom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altrom.tdf" 88 6 0 } } { "lpm_rom0.bdf" "" { Schematic "D:/Projects/quartus/computer/lpm_rom0.bdf" { { 216 480 592 312 "inst" "" } } } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233504919 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_od01.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_od01.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_od01 " "Found entity 1: altsyncram_od01" { } { { "db/altsyncram_od01.tdf" "" { Text "D:/Projects/quartus/computer/db/altsyncram_od01.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1699233504964 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1699233504964 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_od01 lpm_rom0:inst9\|LPM_ROM:inst\|altrom:srom\|altsyncram:rom_block\|altsyncram_od01:auto_generated " "Elaborating entity \"altsyncram_od01\" for hierarchy \"lpm_rom0:inst9\|LPM_ROM:inst\|altrom:srom\|altsyncram:rom_block\|altsyncram_od01:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233504965 ""} { "Warning" "WSGN_SEARCH_FILE" "timing.bdf 1 1 " "Using design file timing.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Timing " "Found entity 1: Timing" { } { { "timing.bdf" "" { Schematic "D:/Projects/quartus/computer/timing.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1699233505006 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1699233505006 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "Timing Timing:inst1 " "Elaborating entity \"Timing\" for hierarchy \"Timing:inst1\"" { } { { "mux21a2627.bdf" "inst1" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -448 1928 2024 -320 "inst1" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505006 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "21mux Timing:inst1\|21mux:inst10 " "Elaborating entity \"21mux\" for hierarchy \"Timing:inst1\|21mux:inst10\"" { } { { "timing.bdf" "inst10" { Schematic "D:/Projects/quartus/computer/timing.bdf" { { 184 -112 8 264 "inst10" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505028 ""} { "Info" "ISGN_ELABORATION_HEADER" "Timing:inst1\|21mux:inst10 " "Elaborated megafunction instantiation \"Timing:inst1\|21mux:inst10\"" { } { { "timing.bdf" "" { Schematic "D:/Projects/quartus/computer/timing.bdf" { { 184 -112 8 264 "inst10" "" } } } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505032 ""} { "Warning" "WSGN_SEARCH_FILE" "uarreg.bdf 1 1 " "Using design file uarreg.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 uARReg " "Found entity 1: uARReg" { } { { "uarreg.bdf" "" { Schematic "D:/Projects/quartus/computer/uarreg.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1699233505045 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1699233505045 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "uARReg uARReg:inst2 " "Elaborating entity \"uARReg\" for hierarchy \"uARReg:inst2\"" { } { { "mux21a2627.bdf" "inst2" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -368 880 1032 -240 "inst2" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505046 ""} { "Warning" "WSGN_SEARCH_FILE" "ucontrol.bdf 1 1 " "Using design file ucontrol.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 uControl " "Found entity 1: uControl" { } { { "ucontrol.bdf" "" { Schematic "D:/Projects/quartus/computer/ucontrol.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1699233505064 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1699233505064 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "uControl uControl:inst " "Elaborating entity \"uControl\" for hierarchy \"uControl:inst\"" { } { { "mux21a2627.bdf" "inst" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -368 544 704 -208 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505064 ""} { "Warning" "WSGN_SEARCH_FILE" "alu.bdf 1 1 " "Using design file alu.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ALU " "Found entity 1: ALU" { } { { "alu.bdf" "" { Schematic "D:/Projects/quartus/computer/alu.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1699233505082 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1699233505082 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "ALU ALU:_ALU_BUSIN1 " "Elaborating entity \"ALU\" for hierarchy \"ALU:_ALU_BUSIN1\"" { } { { "mux21a2627.bdf" "_ALU_BUSIN1" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -1336 1176 1304 -1208 "_ALU_BUSIN1" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505082 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "74181 ALU:_ALU_BUSIN1\|74181:inst " "Elaborating entity \"74181\" for hierarchy \"ALU:_ALU_BUSIN1\|74181:inst\"" { } { { "alu.bdf" "inst" { Schematic "D:/Projects/quartus/computer/alu.bdf" { { 80 520 640 336 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505103 ""} { "Info" "ISGN_ELABORATION_HEADER" "ALU:_ALU_BUSIN1\|74181:inst " "Elaborated megafunction instantiation \"ALU:_ALU_BUSIN1\|74181:inst\"" { } { { "alu.bdf" "" { Schematic "D:/Projects/quartus/computer/alu.bdf" { { 80 520 640 336 "inst" "" } } } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505117 ""} { "Warning" "WSGN_SEARCH_FILE" "reg8.bdf 1 1 " "Using design file reg8.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Reg8 " "Found entity 1: Reg8" { } { { "reg8.bdf" "" { Schematic "D:/Projects/quartus/computer/reg8.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1699233505131 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1699233505131 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "Reg8 Reg8:_R1 " "Elaborating entity \"Reg8\" for hierarchy \"Reg8:_R1\"" { } { { "mux21a2627.bdf" "_R1" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -1352 872 1008 -1256 "_R1" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505132 ""} { "Warning" "WGDFX_PRIMITIVE_IGNORED" "DFF 12 " "Primitive \"DFF\" of instance \"12\" not used" { } { { "reg8.bdf" "" { Schematic "D:/Projects/quartus/computer/reg8.bdf" { { 1128 952 1016 1208 "12" "" } } } } } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Analysis & Synthesis" 0 -1 1699233505133 ""} { "Warning" "WSGN_SEARCH_FILE" "decodea.bdf 1 1 " "Using design file decodea.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 decodea " "Found entity 1: decodea" { } { { "decodea.bdf" "" { Schematic "D:/Projects/quartus/computer/decodea.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1699233505149 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1699233505149 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "decodea decodea:inst6 " "Elaborating entity \"decodea\" for hierarchy \"decodea:inst6\"" { } { { "mux21a2627.bdf" "inst6" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -1008 1472 1584 -848 "inst6" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505149 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mux1 lpm_mux1:inst21 " "Elaborating entity \"lpm_mux1\" for hierarchy \"lpm_mux1:inst21\"" { } { { "mux21a2627.bdf" "inst21" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -1256 1496 1640 -1096 "inst21" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505158 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mux lpm_mux1:inst21\|lpm_mux:LPM_MUX_component " "Elaborating entity \"lpm_mux\" for hierarchy \"lpm_mux1:inst21\|lpm_mux:LPM_MUX_component\"" { } { { "lpm_mux1.v" "LPM_MUX_component" { Text "D:/Projects/quartus/computer/lpm_mux1.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505203 ""} { "Info" "ISGN_ELABORATION_HEADER" "lpm_mux1:inst21\|lpm_mux:LPM_MUX_component " "Elaborated megafunction instantiation \"lpm_mux1:inst21\|lpm_mux:LPM_MUX_component\"" { } { { "lpm_mux1.v" "" { Text "D:/Projects/quartus/computer/lpm_mux1.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505210 ""} { "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mux1:inst21\|lpm_mux:LPM_MUX_component " "Instantiated megafunction \"lpm_mux1:inst21\|lpm_mux:LPM_MUX_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_size 7 " "Parameter \"lpm_size\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1699233505210 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_MUX " "Parameter \"lpm_type\" = \"LPM_MUX\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1699233505210 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1699233505210 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widths 3 " "Parameter \"lpm_widths\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1699233505210 ""} } { { "lpm_mux1.v" "" { Text "D:/Projects/quartus/computer/lpm_mux1.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1699233505210 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_lrc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_lrc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_lrc " "Found entity 1: mux_lrc" { } { { "db/mux_lrc.tdf" "" { Text "D:/Projects/quartus/computer/db/mux_lrc.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1699233505250 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1699233505250 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_lrc lpm_mux1:inst21\|lpm_mux:LPM_MUX_component\|mux_lrc:auto_generated " "Elaborating entity \"mux_lrc\" for hierarchy \"lpm_mux1:inst21\|lpm_mux:LPM_MUX_component\|mux_lrc:auto_generated\"" { } { { "lpm_mux.tdf" "auto_generated" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_mux.tdf" 86 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505250 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_RAM_DQ LPM_RAM_DQ:_RAM_BUSIN2 " "Elaborating entity \"LPM_RAM_DQ\" for hierarchy \"LPM_RAM_DQ:_RAM_BUSIN2\"" { } { { "mux21a2627.bdf" "_RAM_BUSIN2" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -1112 880 1000 -1000 "_RAM_BUSIN2" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505285 ""} { "Info" "ISGN_ELABORATION_HEADER" "LPM_RAM_DQ:_RAM_BUSIN2 " "Elaborated megafunction instantiation \"LPM_RAM_DQ:_RAM_BUSIN2\"" { } { { "mux21a2627.bdf" "" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -1112 880 1000 -1000 "_RAM_BUSIN2" "" } } } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505290 ""} { "Info" "ISGN_MEGAFN_PARAM_TOP" "LPM_RAM_DQ:_RAM_BUSIN2 " "Instantiated megafunction \"LPM_RAM_DQ:_RAM_BUSIN2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_OUTDATA UNREGISTERED " "Parameter \"LPM_OUTDATA\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1699233505290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1699233505290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHAD 8 " "Parameter \"LPM_WIDTHAD\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1699233505290 ""} } { { "mux21a2627.bdf" "" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -1112 880 1000 -1000 "_RAM_BUSIN2" "" } } } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1699233505290 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "altram LPM_RAM_DQ:_RAM_BUSIN2\|altram:sram " "Elaborating entity \"altram\" for hierarchy \"LPM_RAM_DQ:_RAM_BUSIN2\|altram:sram\"" { } { { "lpm_ram_dq.tdf" "sram" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 75 6 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505314 ""} { "Warning" "WTDFX_ASSERTION" "altram does not support Cyclone IV E device family -- attempting best-case memory conversions, but power-up states and read during write behavior will be different for Cyclone IV E devices " "Assertion warning: altram does not support Cyclone IV E device family -- attempting best-case memory conversions, but power-up states and read during write behavior will be different for Cyclone IV E devices" { } { { "altram.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altram.tdf" 211 2 0 } } { "lpm_ram_dq.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 75 6 0 } } { "mux21a2627.bdf" "" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -1112 880 1000 -1000 "_RAM_BUSIN2" "" } } } } } 0 287001 "Assertion warning: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1699233505318 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "LPM_RAM_DQ:_RAM_BUSIN2\|altram:sram LPM_RAM_DQ:_RAM_BUSIN2 " "Elaborated megafunction instantiation \"LPM_RAM_DQ:_RAM_BUSIN2\|altram:sram\", which is child of megafunction instantiation \"LPM_RAM_DQ:_RAM_BUSIN2\"" { } { { "lpm_ram_dq.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 75 6 0 } } { "mux21a2627.bdf" "" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -1112 880 1000 -1000 "_RAM_BUSIN2" "" } } } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505328 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram LPM_RAM_DQ:_RAM_BUSIN2\|altram:sram\|altsyncram:ram_block " "Elaborating entity \"altsyncram\" for hierarchy \"LPM_RAM_DQ:_RAM_BUSIN2\|altram:sram\|altsyncram:ram_block\"" { } { { "altram.tdf" "ram_block" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altram.tdf" 102 5 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505349 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "LPM_RAM_DQ:_RAM_BUSIN2\|altram:sram\|altsyncram:ram_block LPM_RAM_DQ:_RAM_BUSIN2 " "Elaborated megafunction instantiation \"LPM_RAM_DQ:_RAM_BUSIN2\|altram:sram\|altsyncram:ram_block\", which is child of megafunction instantiation \"LPM_RAM_DQ:_RAM_BUSIN2\"" { } { { "altram.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altram.tdf" 102 5 0 } } { "mux21a2627.bdf" "" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -1112 880 1000 -1000 "_RAM_BUSIN2" "" } } } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505359 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_ap71.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_ap71.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_ap71 " "Found entity 1: altsyncram_ap71" { } { { "db/altsyncram_ap71.tdf" "" { Text "D:/Projects/quartus/computer/db/altsyncram_ap71.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1699233505399 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1699233505399 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_ap71 LPM_RAM_DQ:_RAM_BUSIN2\|altram:sram\|altsyncram:ram_block\|altsyncram_ap71:auto_generated " "Elaborating entity \"altsyncram_ap71\" for hierarchy \"LPM_RAM_DQ:_RAM_BUSIN2\|altram:sram\|altsyncram:ram_block\|altsyncram_ap71:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505400 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "BUSMUX BUSMUX:inst28 " "Elaborating entity \"BUSMUX\" for hierarchy \"BUSMUX:inst28\"" { } { { "mux21a2627.bdf" "inst28" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -744 1040 1152 -656 "inst28" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505428 ""} { "Info" "ISGN_ELABORATION_HEADER" "BUSMUX:inst28 " "Elaborated megafunction instantiation \"BUSMUX:inst28\"" { } { { "mux21a2627.bdf" "" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -744 1040 1152 -656 "inst28" "" } } } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505432 ""} { "Info" "ISGN_MEGAFN_PARAM_TOP" "BUSMUX:inst28 " "Instantiated megafunction \"BUSMUX:inst28\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH 8 " "Parameter \"WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1699233505432 ""} } { { "mux21a2627.bdf" "" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -744 1040 1152 -656 "inst28" "" } } } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1699233505432 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mux BUSMUX:inst28\|lpm_mux:\$00000 " "Elaborating entity \"lpm_mux\" for hierarchy \"BUSMUX:inst28\|lpm_mux:\$00000\"" { } { { "busmux.tdf" "\$00000" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/busmux.tdf" 43 13 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505440 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "BUSMUX:inst28\|lpm_mux:\$00000 BUSMUX:inst28 " "Elaborated megafunction instantiation \"BUSMUX:inst28\|lpm_mux:\$00000\", which is child of megafunction instantiation \"BUSMUX:inst28\"" { } { { "busmux.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/busmux.tdf" 43 13 0 } } { "mux21a2627.bdf" "" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -744 1040 1152 -656 "inst28" "" } } } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505447 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_erc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_erc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_erc " "Found entity 1: mux_erc" { } { { "db/mux_erc.tdf" "" { Text "D:/Projects/quartus/computer/db/mux_erc.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1699233505486 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1699233505486 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_erc BUSMUX:inst28\|lpm_mux:\$00000\|mux_erc:auto_generated " "Elaborating entity \"mux_erc\" for hierarchy \"BUSMUX:inst28\|lpm_mux:\$00000\|mux_erc:auto_generated\"" { } { { "lpm_mux.tdf" "auto_generated" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_mux.tdf" 86 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505486 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter0 lpm_counter0:_PC " "Elaborating entity \"lpm_counter0\" for hierarchy \"lpm_counter0:_PC\"" { } { { "mux21a2627.bdf" "_PC" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -840 872 1016 -744 "_PC" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505497 ""} { "Warning" "WCBX_LPM_COUNTER_CBX_LPM_COUNTER_LATCH_USED_WARNING" "" "Counter will power up to an undefined state. An asynchronous signal should be asserted before the counter reaches a known state." { } { { "lpm_counter0.v" "LPM_COUNTER_component" { Text "D:/Projects/quartus/computer/lpm_counter0.v" 70 0 0 } } } 0 272007 "Warning message" 0 0 "Analysis & Synthesis" 0 -1 1699233505566 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter lpm_counter0:_PC\|lpm_counter:LPM_COUNTER_component " "Elaborating entity \"lpm_counter\" for hierarchy \"lpm_counter0:_PC\|lpm_counter:LPM_COUNTER_component\"" { } { { "lpm_counter0.v" "LPM_COUNTER_component" { Text "D:/Projects/quartus/computer/lpm_counter0.v" 70 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505567 ""} { "Info" "ISGN_ELABORATION_HEADER" "lpm_counter0:_PC\|lpm_counter:LPM_COUNTER_component " "Elaborated megafunction instantiation \"lpm_counter0:_PC\|lpm_counter:LPM_COUNTER_component\"" { } { { "lpm_counter0.v" "" { Text "D:/Projects/quartus/computer/lpm_counter0.v" 70 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505576 ""} { "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter0:_PC\|lpm_counter:LPM_COUNTER_component " "Instantiated megafunction \"lpm_counter0:_PC\|lpm_counter:LPM_COUNTER_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction UP " "Parameter \"lpm_direction\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1699233505577 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_port_updown PORT_UNUSED " "Parameter \"lpm_port_updown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1699233505577 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_COUNTER " "Parameter \"lpm_type\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1699233505577 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1699233505577 ""} } { { "lpm_counter0.v" "" { Text "D:/Projects/quartus/computer/lpm_counter0.v" 70 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1699233505577 ""} { "Warning" "WTDFX_ASSERTION" "Counter will power up to an undefined state. An asynchronous signal should be asserted before the counter reaches a known state. " "Assertion warning: Counter will power up to an undefined state. An asynchronous signal should be asserted before the counter reaches a known state." { } { { "db/cntr_b6j.tdf" "" { Text "D:/Projects/quartus/computer/db/cntr_b6j.tdf" 152 2 0 } } } 0 287001 "Assertion warning: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1699233505618 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_b6j.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_b6j.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_b6j " "Found entity 1: cntr_b6j" { } { { "db/cntr_b6j.tdf" "" { Text "D:/Projects/quartus/computer/db/cntr_b6j.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1699233505618 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1699233505618 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_b6j lpm_counter0:_PC\|lpm_counter:LPM_COUNTER_component\|cntr_b6j:auto_generated " "Elaborating entity \"cntr_b6j\" for hierarchy \"lpm_counter0:_PC\|lpm_counter:LPM_COUNTER_component\|cntr_b6j:auto_generated\"" { } { { "lpm_counter.tdf" "auto_generated" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_counter.tdf" 258 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505619 ""} { "Warning" "WSGN_SEARCH_FILE" "decodec.bdf 1 1 " "Using design file decodec.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 decodec " "Found entity 1: decodec" { } { { "decodec.bdf" "" { Schematic "D:/Projects/quartus/computer/decodec.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1699233505641 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1699233505641 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "decodec decodec:inst7 " "Elaborating entity \"decodec\" for hierarchy \"decodec:inst7\"" { } { { "mux21a2627.bdf" "inst7" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -544 1488 1584 -416 "inst7" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505641 ""} { "Warning" "WSGN_SEARCH_FILE" "registers_3.bdf 1 1 " "Using design file registers_3.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Registers_3 " "Found entity 1: Registers_3" { } { { "registers_3.bdf" "" { Schematic "D:/Projects/quartus/computer/registers_3.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1699233505659 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1699233505659 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "Registers_3 Registers_3:_R4-5-6_BUSIN4-5-6 " "Elaborating entity \"Registers_3\" for hierarchy \"Registers_3:_R4-5-6_BUSIN4-5-6\"" { } { { "mux21a2627.bdf" "_R4-5-6_BUSIN4-5-6" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -1496 864 1008 -1368 "_R4-5-6_BUSIN4-5-6" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505659 ""} { "Warning" "WSGN_SEARCH_FILE" "regcontrol.bdf 1 1 " "Using design file regcontrol.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 RegControl " "Found entity 1: RegControl" { } { { "regcontrol.bdf" "" { Schematic "D:/Projects/quartus/computer/regcontrol.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1699233505679 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1699233505679 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "RegControl RegControl:inst12 " "Elaborating entity \"RegControl\" for hierarchy \"RegControl:inst12\"" { } { { "mux21a2627.bdf" "inst12" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -1464 696 808 -1336 "inst12" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505679 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "74148 74148:inst4 " "Elaborating entity \"74148\" for hierarchy \"74148:inst4\"" { } { { "mux21a2627.bdf" "inst4" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -752 1952 2072 -576 "inst4" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505702 ""} { "Info" "ISGN_ELABORATION_HEADER" "74148:inst4 " "Elaborated megafunction instantiation \"74148:inst4\"" { } { { "mux21a2627.bdf" "" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -752 1952 2072 -576 "inst4" "" } } } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505709 ""} { "Warning" "WSGN_SEARCH_FILE" "decode2_4.bdf 1 1 " "Using design file decode2_4.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 decode2_4 " "Found entity 1: decode2_4" { } { { "decode2_4.bdf" "" { Schematic "D:/Projects/quartus/computer/decode2_4.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1699233505723 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1699233505723 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode2_4 decode2_4:inst34 " "Elaborating entity \"decode2_4\" for hierarchy \"decode2_4:inst34\"" { } { { "mux21a2627.bdf" "inst34" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -832 1472 1584 -704 "inst34" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233505724 ""} { "Info" "IMLS_MLS_IGNORED_SUMMARY" "37 " "Ignored 37 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_CARRY" "8 " "Ignored 8 CARRY buffer(s)" { } { } 0 13015 "Ignored %1!d! CARRY buffer(s)" 0 0 "Design Software" 0 -1 1699233505950 ""} { "Info" "IMLS_MLS_IGNORED_SOFT" "29 " "Ignored 29 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Design Software" 0 -1 1699233505950 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Analysis & Synthesis" 0 -1 1699233505950 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI_HDR" "" "Always-enabled tri-state buffer(s) removed" { { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[11\] M\[11\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[11\]\" to the node \"M\[11\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[10\] M\[10\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[10\]\" to the node \"M\[10\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[9\] M\[9\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[9\]\" to the node \"M\[9\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[23\] M\[23\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[23\]\" to the node \"M\[23\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[22\] M\[22\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[22\]\" to the node \"M\[22\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[21\] M\[21\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[21\]\" to the node \"M\[21\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[20\] M\[20\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[20\]\" to the node \"M\[20\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[19\] M\[19\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[19\]\" to the node \"M\[19\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[18\] M\[18\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[18\]\" to the node \"M\[18\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[17\] M\[17\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[17\]\" to the node \"M\[17\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[16\] M\[16\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[16\]\" to the node \"M\[16\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[15\] M\[15\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[15\]\" to the node \"M\[15\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[14\] M\[14\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[14\]\" to the node \"M\[14\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[13\] M\[13\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[13\]\" to the node \"M\[13\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[12\] M\[12\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[12\]\" to the node \"M\[12\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[8\] M\[8\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[8\]\" to the node \"M\[8\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[7\] M\[7\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[7\]\" to the node \"M\[7\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[6\] M\[6\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[6\]\" to the node \"M\[6\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[5\] M\[5\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[5\]\" to the node \"M\[5\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[4\] M\[4\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[4\]\" to the node \"M\[4\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[3\] M\[3\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[3\]\" to the node \"M\[3\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[2\] M\[2\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[2\]\" to the node \"M\[2\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[1\] M\[1\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[1\]\" to the node \"M\[1\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[0\] M\[0\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[0\]\" to the node \"M\[0\]\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[5\] uARReg:inst2\|inst45 " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[5\]\" to the node \"uARReg:inst2\|inst45\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[4\] uARReg:inst2\|inst44 " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[4\]\" to the node \"uARReg:inst2\|inst44\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[3\] uARReg:inst2\|inst43 " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[3\]\" to the node \"uARReg:inst2\|inst43\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[2\] uARReg:inst2\|inst42 " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[2\]\" to the node \"uARReg:inst2\|inst42\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[1\] uARReg:inst2\|inst41 " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[1\]\" to the node \"uARReg:inst2\|inst41\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[0\] uARReg:inst2\|inst40 " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[0\]\" to the node \"uARReg:inst2\|inst40\" into a wire" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1699233506205 ""} } { } 0 13044 "Always-enabled tri-state buffer(s) removed" 0 0 "Analysis & Synthesis" 0 -1 1699233506205 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[11\] decodeb:inst5\|inst " "Converted the fan-out from the tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[11\]\" to the node \"decodeb:inst5\|inst\" into an OR gate" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[10\] decodeb:inst5\|inst " "Converted the fan-out from the tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[10\]\" to the node \"decodeb:inst5\|inst\" into an OR gate" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[9\] decodeb:inst5\|inst " "Converted the fan-out from the tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[9\]\" to the node \"decodeb:inst5\|inst\" into an OR gate" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[23\] ALU:_ALU_BUSIN1\|74181:inst2\|46 " "Converted the fan-out from the tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[23\]\" to the node \"ALU:_ALU_BUSIN1\|74181:inst2\|46\" into an OR gate" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[22\] ALU:_ALU_BUSIN1\|74181:inst2\|46 " "Converted the fan-out from the tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[22\]\" to the node \"ALU:_ALU_BUSIN1\|74181:inst2\|46\" into an OR gate" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[21\] ALU:_ALU_BUSIN1\|74181:inst\|12 " "Converted the fan-out from the tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[21\]\" to the node \"ALU:_ALU_BUSIN1\|74181:inst\|12\" into an OR gate" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[20\] ALU:_ALU_BUSIN1\|74181:inst\|11 " "Converted the fan-out from the tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[20\]\" to the node \"ALU:_ALU_BUSIN1\|74181:inst\|11\" into an OR gate" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[19\] ALU:_ALU_BUSIN1\|74181:inst2\|66 " "Converted the fan-out from the tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[19\]\" to the node \"ALU:_ALU_BUSIN1\|74181:inst2\|66\" into an OR gate" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[18\] ALU:_ALU_BUSIN1\|74181:inst2\|66 " "Converted the fan-out from the tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[18\]\" to the node \"ALU:_ALU_BUSIN1\|74181:inst2\|66\" into an OR gate" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[17\] lpm_ram_dq:_RAM_BUSIN2\|altram:sram\|altsyncram:ram_block\|altsyncram_ap71:auto_generated\|q_a\[0\] " "Converted the fan-out from the tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[17\]\" to the node \"lpm_ram_dq:_RAM_BUSIN2\|altram:sram\|altsyncram:ram_block\|altsyncram_ap71:auto_generated\|q_a\[0\]\" into an OR gate" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[16\] decode2_4:inst34\|inst6 " "Converted the fan-out from the tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[16\]\" to the node \"decode2_4:inst34\|inst6\" into an OR gate" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[15\] decode2_4:inst34\|inst7 " "Converted the fan-out from the tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[15\]\" to the node \"decode2_4:inst34\|inst7\" into an OR gate" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[14\] decodea:inst6\|inst " "Converted the fan-out from the tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[14\]\" to the node \"decodea:inst6\|inst\" into an OR gate" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[13\] decodea:inst6\|inst " "Converted the fan-out from the tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[13\]\" to the node \"decodea:inst6\|inst\" into an OR gate" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[12\] decodea:inst6\|inst " "Converted the fan-out from the tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[12\]\" to the node \"decodea:inst6\|inst\" into an OR gate" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[8\] decodec:inst7\|inst " "Converted the fan-out from the tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[8\]\" to the node \"decodec:inst7\|inst\" into an OR gate" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[7\] decodec:inst7\|inst " "Converted the fan-out from the tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[7\]\" to the node \"decodec:inst7\|inst\" into an OR gate" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Design Software" 0 -1 1699233506205 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "lpm_rom0:inst9\|lpm_rom:inst\|otri\[6\] decodec:inst7\|inst " "Converted the fan-out from the tri-state buffer \"lpm_rom0:inst9\|lpm_rom:inst\|otri\[6\]\" to the node \"decodec:inst7\|inst\" into an OR gate" { } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Design Software" 0 -1 1699233506205 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Analysis & Synthesis" 0 -1 1699233506205 ""} { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT" "" "Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state." { { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "uARReg:inst2\|inst44 uARReg:inst2\|inst44~_emulated uARReg:inst2\|inst44~1 " "Register \"uARReg:inst2\|inst44\" is converted into an equivalent circuit using register \"uARReg:inst2\|inst44~_emulated\" and latch \"uARReg:inst2\|inst44~1\"" { } { { "uarreg.bdf" "" { Schematic "D:/Projects/quartus/computer/uarreg.bdf" { { 144 536 600 224 "inst44" "" } } } } } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Design Software" 0 -1 1699233506207 "|mux21a2627|uARReg:inst2|inst44"} { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "uARReg:inst2\|inst42 uARReg:inst2\|inst42~_emulated uARReg:inst2\|inst42~1 " "Register \"uARReg:inst2\|inst42\" is converted into an equivalent circuit using register \"uARReg:inst2\|inst42~_emulated\" and latch \"uARReg:inst2\|inst42~1\"" { } { { "uarreg.bdf" "" { Schematic "D:/Projects/quartus/computer/uarreg.bdf" { { 272 368 432 352 "inst42" "" } } } } } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Design Software" 0 -1 1699233506207 "|mux21a2627|uARReg:inst2|inst42"} { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "uARReg:inst2\|inst41 uARReg:inst2\|inst41~_emulated uARReg:inst2\|inst41~1 " "Register \"uARReg:inst2\|inst41\" is converted into an equivalent circuit using register \"uARReg:inst2\|inst41~_emulated\" and latch \"uARReg:inst2\|inst41~1\"" { } { { "uarreg.bdf" "" { Schematic "D:/Projects/quartus/computer/uarreg.bdf" { { 144 368 432 224 "inst41" "" } } } } } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Design Software" 0 -1 1699233506207 "|mux21a2627|uARReg:inst2|inst41"} { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "uARReg:inst2\|inst40 uARReg:inst2\|inst40~_emulated uARReg:inst2\|inst40~1 " "Register \"uARReg:inst2\|inst40\" is converted into an equivalent circuit using register \"uARReg:inst2\|inst40~_emulated\" and latch \"uARReg:inst2\|inst40~1\"" { } { { "uarreg.bdf" "" { Schematic "D:/Projects/quartus/computer/uarreg.bdf" { { 24 368 432 104 "inst40" "" } } } } } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Design Software" 0 -1 1699233506207 "|mux21a2627|uARReg:inst2|inst40"} } { } 0 13004 "Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state." 0 0 "Analysis & Synthesis" 0 -1 1699233506207 ""} { "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "I\[7\] GND " "Pin \"I\[7\]\" is stuck at GND" { } { { "mux21a2627.bdf" "" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -528 1048 1224 -512 "I\[7..0\]" "" } { -1448 656 696 -1431 "I\[3\]" "" } { -1432 656 696 -1415 "I\[2\]" "" } { -1416 656 696 -1399 "I\[1\]" "" } { -1400 656 696 -1383 "I\[0\]" "" } { -536 1016 1048 -519 "I\[7..0\]" "" } { -256 488 544 -239 "I\[7..2\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1699233506263 "|mux21a2627|I[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "led\[7\] GND " "Pin \"led\[7\]\" is stuck at GND" { } { { "mux21a2627.bdf" "" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -624 1048 1224 -608 "led\[7..0\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1699233506263 "|mux21a2627|led[7]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1699233506263 ""} { "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1699233506342 ""} { "Info" "ISCL_REMOVED_CONST_ADDR_LINES" "lpm_ram_dq:_RAM_BUSIN2\|altram:sram\|altsyncram:ram_block\|altsyncram_ap71:auto_generated\|ALTSYNCRAM 1 " "Removed 1 MSB VCC or GND address nodes from RAM block \"lpm_ram_dq:_RAM_BUSIN2\|altram:sram\|altsyncram:ram_block\|altsyncram_ap71:auto_generated\|ALTSYNCRAM\"" { } { { "db/altsyncram_ap71.tdf" "" { Text "D:/Projects/quartus/computer/db/altsyncram_ap71.tdf" 32 2 0 } } { "altsyncram.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "altram.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altram.tdf" 102 5 0 } } { "lpm_ram_dq.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 75 6 0 } } { "mux21a2627.bdf" "" { Schematic "D:/Projects/quartus/computer/mux21a2627.bdf" { { -1112 880 1000 -1000 "_RAM_BUSIN2" "" } } } } } 0 17036 "Removed %2!d! MSB VCC or GND address nodes from RAM block \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233506715 ""} { "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1699233506871 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1699233506871 ""} { "Info" "ICUT_CUT_TM_SUMMARY" "355 " "Implemented 355 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "13 " "Implemented 13 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1699233506948 ""} { "Info" "ICUT_CUT_TM_OPINS" "80 " "Implemented 80 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1699233506948 ""} { "Info" "ICUT_CUT_TM_LCELLS" "230 " "Implemented 230 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1699233506948 ""} { "Info" "ICUT_CUT_TM_RAMS" "32 " "Implemented 32 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1699233506948 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1699233506948 ""} { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 76 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 76 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4861 " "Peak virtual memory: 4861 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1699233506962 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 06 09:18:26 2023 " "Processing ended: Mon Nov 06 09:18:26 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1699233506962 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1699233506962 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:20 " "Total CPU time (on all processors): 00:00:20" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1699233506962 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1699233506962 ""}