--lpm_mux CASCADE_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone IV E" IGNORE_CASCADE_BUFFERS="OFF" LPM_SIZE=7 LPM_WIDTH=8 LPM_WIDTHS=3 data result sel --VERSION_BEGIN 17.1 cbx_lpm_mux 2017:10:25:18:06:53:SJ cbx_mgl 2017:10:25:18:08:29:SJ VERSION_END -- Copyright (C) 2017 Intel Corporation. All rights reserved. -- Your use of Intel Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Intel Program License -- Subscription Agreement, the Intel Quartus Prime License Agreement, -- the Intel FPGA IP License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for -- the sole purpose of programming logic devices manufactured by -- Intel and sold by Intel or its authorized distributors. Please -- refer to the applicable agreement for further details. --synthesis_resources = lut 40 SUBDESIGN mux_lrc ( data[55..0] : input; result[7..0] : output; sel[2..0] : input; ) VARIABLE result_node[7..0] : WIRE; sel_ffs_wire[2..0] : WIRE; sel_node[2..0] : WIRE; w_data102w[3..0] : WIRE; w_data103w[3..0] : WIRE; w_data149w[7..0] : WIRE; w_data171w[3..0] : WIRE; w_data172w[3..0] : WIRE; w_data218w[7..0] : WIRE; w_data240w[3..0] : WIRE; w_data241w[3..0] : WIRE; w_data287w[7..0] : WIRE; w_data309w[3..0] : WIRE; w_data310w[3..0] : WIRE; w_data31w[3..0] : WIRE; w_data32w[3..0] : WIRE; w_data356w[7..0] : WIRE; w_data378w[3..0] : WIRE; w_data379w[3..0] : WIRE; w_data425w[7..0] : WIRE; w_data447w[3..0] : WIRE; w_data448w[3..0] : WIRE; w_data494w[7..0] : WIRE; w_data516w[3..0] : WIRE; w_data517w[3..0] : WIRE; w_data80w[7..0] : WIRE; w_data9w[7..0] : WIRE; w_sel104w[1..0] : WIRE; w_sel173w[1..0] : WIRE; w_sel242w[1..0] : WIRE; w_sel311w[1..0] : WIRE; w_sel33w[1..0] : WIRE; w_sel380w[1..0] : WIRE; w_sel449w[1..0] : WIRE; w_sel518w[1..0] : WIRE; BEGIN result[] = result_node[]; result_node[] = ( ((sel_node[2..2] & (((w_data517w[1..1] & w_sel518w[0..0]) & (! (((w_data517w[0..0] & (! w_sel518w[1..1])) & (! w_sel518w[0..0])) # (w_sel518w[1..1] & (w_sel518w[0..0] # w_data517w[2..2]))))) # ((((w_data517w[0..0] & (! w_sel518w[1..1])) & (! w_sel518w[0..0])) # (w_sel518w[1..1] & (w_sel518w[0..0] # w_data517w[2..2]))) & (w_data517w[3..3] # (! w_sel518w[0..0]))))) # ((! sel_node[2..2]) & (((w_data516w[1..1] & w_sel518w[0..0]) & (! (((w_data516w[0..0] & (! w_sel518w[1..1])) & (! w_sel518w[0..0])) # (w_sel518w[1..1] & (w_sel518w[0..0] # w_data516w[2..2]))))) # ((((w_data516w[0..0] & (! w_sel518w[1..1])) & (! w_sel518w[0..0])) # (w_sel518w[1..1] & (w_sel518w[0..0] # w_data516w[2..2]))) & (w_data516w[3..3] # (! w_sel518w[0..0])))))), ((sel_node[2..2] & (((w_data448w[1..1] & w_sel449w[0..0]) & (! (((w_data448w[0..0] & (! w_sel449w[1..1])) & (! w_sel449w[0..0])) # (w_sel449w[1..1] & (w_sel449w[0..0] # w_data448w[2..2]))))) # ((((w_data448w[0..0] & (! w_sel449w[1..1])) & (! w_sel449w[0..0])) # (w_sel449w[1..1] & (w_sel449w[0..0] # w_data448w[2..2]))) & (w_data448w[3..3] # (! w_sel449w[0..0]))))) # ((! sel_node[2..2]) & (((w_data447w[1..1] & w_sel449w[0..0]) & (! (((w_data447w[0..0] & (! w_sel449w[1..1])) & (! w_sel449w[0..0])) # (w_sel449w[1..1] & (w_sel449w[0..0] # w_data447w[2..2]))))) # ((((w_data447w[0..0] & (! w_sel449w[1..1])) & (! w_sel449w[0..0])) # (w_sel449w[1..1] & (w_sel449w[0..0] # w_data447w[2..2]))) & (w_data447w[3..3] # (! w_sel449w[0..0])))))), ((sel_node[2..2] & (((w_data379w[1..1] & w_sel380w[0..0]) & (! (((w_data379w[0..0] & (! w_sel380w[1..1])) & (! w_sel380w[0..0])) # (w_sel380w[1..1] & (w_sel380w[0..0] # w_data379w[2..2]))))) # ((((w_data379w[0..0] & (! w_sel380w[1..1])) & (! w_sel380w[0..0])) # (w_sel380w[1..1] & (w_sel380w[0..0] # w_data379w[2..2]))) & (w_data379w[3..3] # (! w_sel380w[0..0]))))) # ((! sel_node[2..2]) & (((w_data378w[1..1] & w_sel380w[0..0]) & (! (((w_data378w[0..0] & (! w_sel380w[1..1])) & (! w_sel380w[0..0])) # (w_sel380w[1..1] & (w_sel380w[0..0] # w_data378w[2..2]))))) # ((((w_data378w[0..0] & (! w_sel380w[1..1])) & (! w_sel380w[0..0])) # (w_sel380w[1..1] & (w_sel380w[0..0] # w_data378w[2..2]))) & (w_data378w[3..3] # (! w_sel380w[0..0])))))), ((sel_node[2..2] & (((w_data310w[1..1] & w_sel311w[0..0]) & (! (((w_data310w[0..0] & (! w_sel311w[1..1])) & (! w_sel311w[0..0])) # (w_sel311w[1..1] & (w_sel311w[0..0] # w_data310w[2..2]))))) # ((((w_data310w[0..0] & (! w_sel311w[1..1])) & (! w_sel311w[0..0])) # (w_sel311w[1..1] & (w_sel311w[0..0] # w_data310w[2..2]))) & (w_data310w[3..3] # (! w_sel311w[0..0]))))) # ((! sel_node[2..2]) & (((w_data309w[1..1] & w_sel311w[0..0]) & (! (((w_data309w[0..0] & (! w_sel311w[1..1])) & (! w_sel311w[0..0])) # (w_sel311w[1..1] & (w_sel311w[0..0] # w_data309w[2..2]))))) # ((((w_data309w[0..0] & (! w_sel311w[1..1])) & (! w_sel311w[0..0])) # (w_sel311w[1..1] & (w_sel311w[0..0] # w_data309w[2..2]))) & (w_data309w[3..3] # (! w_sel311w[0..0])))))), ((sel_node[2..2] & (((w_data241w[1..1] & w_sel242w[0..0]) & (! (((w_data241w[0..0] & (! w_sel242w[1..1])) & (! w_sel242w[0..0])) # (w_sel242w[1..1] & (w_sel242w[0..0] # w_data241w[2..2]))))) # ((((w_data241w[0..0] & (! w_sel242w[1..1])) & (! w_sel242w[0..0])) # (w_sel242w[1..1] & (w_sel242w[0..0] # w_data241w[2..2]))) & (w_data241w[3..3] # (! w_sel242w[0..0]))))) # ((! sel_node[2..2]) & (((w_data240w[1..1] & w_sel242w[0..0]) & (! (((w_data240w[0..0] & (! w_sel242w[1..1])) & (! w_sel242w[0..0])) # (w_sel242w[1..1] & (w_sel242w[0..0] # w_data240w[2..2]))))) # ((((w_data240w[0..0] & (! w_sel242w[1..1])) & (! w_sel242w[0..0])) # (w_sel242w[1..1] & (w_sel242w[0..0] # w_data240w[2..2]))) & (w_data240w[3..3] # (! w_sel242w[0..0])))))), ((sel_node[2..2] & (((w_data172w[1..1] & w_sel173w[0..0]) & (! (((w_data172w[0..0] & (! w_sel173w[1..1])) & (! w_sel173w[0..0])) # (w_sel173w[1..1] & (w_sel173w[0..0] # w_data172w[2..2]))))) # ((((w_data172w[0..0] & (! w_sel173w[1..1])) & (! w_sel173w[0..0])) # (w_sel173w[1..1] & (w_sel173w[0..0] # w_data172w[2..2]))) & (w_data172w[3..3] # (! w_sel173w[0..0]))))) # ((! sel_node[2..2]) & (((w_data171w[1..1] & w_sel173w[0..0]) & (! (((w_data171w[0..0] & (! w_sel173w[1..1])) & (! w_sel173w[0..0])) # (w_sel173w[1..1] & (w_sel173w[0..0] # w_data171w[2..2]))))) # ((((w_data171w[0..0] & (! w_sel173w[1..1])) & (! w_sel173w[0..0])) # (w_sel173w[1..1] & (w_sel173w[0..0] # w_data171w[2..2]))) & (w_data171w[3..3] # (! w_sel173w[0..0])))))), ((sel_node[2..2] & (((w_data103w[1..1] & w_sel104w[0..0]) & (! (((w_data103w[0..0] & (! w_sel104w[1..1])) & (! w_sel104w[0..0])) # (w_sel104w[1..1] & (w_sel104w[0..0] # w_data103w[2..2]))))) # ((((w_data103w[0..0] & (! w_sel104w[1..1])) & (! w_sel104w[0..0])) # (w_sel104w[1..1] & (w_sel104w[0..0] # w_data103w[2..2]))) & (w_data103w[3..3] # (! w_sel104w[0..0]))))) # ((! sel_node[2..2]) & (((w_data102w[1..1] & w_sel104w[0..0]) & (! (((w_data102w[0..0] & (! w_sel104w[1..1])) & (! w_sel104w[0..0])) # (w_sel104w[1..1] & (w_sel104w[0..0] # w_data102w[2..2]))))) # ((((w_data102w[0..0] & (! w_sel104w[1..1])) & (! w_sel104w[0..0])) # (w_sel104w[1..1] & (w_sel104w[0..0] # w_data102w[2..2]))) & (w_data102w[3..3] # (! w_sel104w[0..0])))))), ((sel_node[2..2] & (((w_data32w[1..1] & w_sel33w[0..0]) & (! (((w_data32w[0..0] & (! w_sel33w[1..1])) & (! w_sel33w[0..0])) # (w_sel33w[1..1] & (w_sel33w[0..0] # w_data32w[2..2]))))) # ((((w_data32w[0..0] & (! w_sel33w[1..1])) & (! w_sel33w[0..0])) # (w_sel33w[1..1] & (w_sel33w[0..0] # w_data32w[2..2]))) & (w_data32w[3..3] # (! w_sel33w[0..0]))))) # ((! sel_node[2..2]) & (((w_data31w[1..1] & w_sel33w[0..0]) & (! (((w_data31w[0..0] & (! w_sel33w[1..1])) & (! w_sel33w[0..0])) # (w_sel33w[1..1] & (w_sel33w[0..0] # w_data31w[2..2]))))) # ((((w_data31w[0..0] & (! w_sel33w[1..1])) & (! w_sel33w[0..0])) # (w_sel33w[1..1] & (w_sel33w[0..0] # w_data31w[2..2]))) & (w_data31w[3..3] # (! w_sel33w[0..0]))))))); sel_ffs_wire[] = ( sel[2..0]); sel_node[] = ( sel_ffs_wire[2..2], sel[1..0]); w_data102w[3..0] = w_data80w[3..0]; w_data103w[3..0] = w_data80w[7..4]; w_data149w[] = ( B"0", data[50..50], data[42..42], data[34..34], data[26..26], data[18..18], data[10..10], data[2..2]); w_data171w[3..0] = w_data149w[3..0]; w_data172w[3..0] = w_data149w[7..4]; w_data218w[] = ( B"0", data[51..51], data[43..43], data[35..35], data[27..27], data[19..19], data[11..11], data[3..3]); w_data240w[3..0] = w_data218w[3..0]; w_data241w[3..0] = w_data218w[7..4]; w_data287w[] = ( B"0", data[52..52], data[44..44], data[36..36], data[28..28], data[20..20], data[12..12], data[4..4]); w_data309w[3..0] = w_data287w[3..0]; w_data310w[3..0] = w_data287w[7..4]; w_data31w[3..0] = w_data9w[3..0]; w_data32w[3..0] = w_data9w[7..4]; w_data356w[] = ( B"0", data[53..53], data[45..45], data[37..37], data[29..29], data[21..21], data[13..13], data[5..5]); w_data378w[3..0] = w_data356w[3..0]; w_data379w[3..0] = w_data356w[7..4]; w_data425w[] = ( B"0", data[54..54], data[46..46], data[38..38], data[30..30], data[22..22], data[14..14], data[6..6]); w_data447w[3..0] = w_data425w[3..0]; w_data448w[3..0] = w_data425w[7..4]; w_data494w[] = ( B"0", data[55..55], data[47..47], data[39..39], data[31..31], data[23..23], data[15..15], data[7..7]); w_data516w[3..0] = w_data494w[3..0]; w_data517w[3..0] = w_data494w[7..4]; w_data80w[] = ( B"0", data[49..49], data[41..41], data[33..33], data[25..25], data[17..17], data[9..9], data[1..1]); w_data9w[] = ( B"0", data[48..48], data[40..40], data[32..32], data[24..24], data[16..16], data[8..8], data[0..0]); w_sel104w[1..0] = sel_node[1..0]; w_sel173w[1..0] = sel_node[1..0]; w_sel242w[1..0] = sel_node[1..0]; w_sel311w[1..0] = sel_node[1..0]; w_sel33w[1..0] = sel_node[1..0]; w_sel380w[1..0] = sel_node[1..0]; w_sel449w[1..0] = sel_node[1..0]; w_sel518w[1..0] = sel_node[1..0]; END; --VALID FILE