--lpm_mux CASCADE_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone IV E" IGNORE_CASCADE_BUFFERS="OFF" LPM_SIZE=2 LPM_WIDTH=8 LPM_WIDTHS=1 data result sel --VERSION_BEGIN 17.1 cbx_lpm_mux 2017:10:25:18:06:53:SJ cbx_mgl 2017:10:25:18:08:29:SJ VERSION_END -- Copyright (C) 2017 Intel Corporation. All rights reserved. -- Your use of Intel Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Intel Program License -- Subscription Agreement, the Intel Quartus Prime License Agreement, -- the Intel FPGA IP License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for -- the sole purpose of programming logic devices manufactured by -- Intel and sold by Intel or its authorized distributors. Please -- refer to the applicable agreement for further details. --synthesis_resources = lut 8 SUBDESIGN mux_erc ( data[15..0] : input; result[7..0] : output; sel[0..0] : input; ) VARIABLE result_node[7..0] : WIRE; sel_node[0..0] : WIRE; w_data18w[1..0] : WIRE; w_data30w[1..0] : WIRE; w_data42w[1..0] : WIRE; w_data4w[1..0] : WIRE; w_data54w[1..0] : WIRE; w_data66w[1..0] : WIRE; w_data78w[1..0] : WIRE; w_data90w[1..0] : WIRE; BEGIN result[] = result_node[]; result_node[] = ( ((sel_node[] & w_data90w[1..1]) # ((! sel_node[]) & w_data90w[0..0])), ((sel_node[] & w_data78w[1..1]) # ((! sel_node[]) & w_data78w[0..0])), ((sel_node[] & w_data66w[1..1]) # ((! sel_node[]) & w_data66w[0..0])), ((sel_node[] & w_data54w[1..1]) # ((! sel_node[]) & w_data54w[0..0])), ((sel_node[] & w_data42w[1..1]) # ((! sel_node[]) & w_data42w[0..0])), ((sel_node[] & w_data30w[1..1]) # ((! sel_node[]) & w_data30w[0..0])), ((sel_node[] & w_data18w[1..1]) # ((! sel_node[]) & w_data18w[0..0])), ((sel_node[] & w_data4w[1..1]) # ((! sel_node[]) & w_data4w[0..0]))); sel_node[] = ( sel[0..0]); w_data18w[] = ( data[9..9], data[1..1]); w_data30w[] = ( data[10..10], data[2..2]); w_data42w[] = ( data[11..11], data[3..3]); w_data4w[] = ( data[8..8], data[0..0]); w_data54w[] = ( data[12..12], data[4..4]); w_data66w[] = ( data[13..13], data[5..5]); w_data78w[] = ( data[14..14], data[6..6]); w_data90w[] = ( data[15..15], data[7..7]); END; --VALID FILE