{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1698129286689 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1698129286697 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 24 14:34:46 2023 " "Processing started: Tue Oct 24 14:34:46 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1698129286697 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1698129286697 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off PC_AR2627 -c PC_AR2627 " "Command: quartus_map --read_settings_files=on --write_settings_files=off PC_AR2627 -c PC_AR2627" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1698129286697 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1698129287042 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1698129287042 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lpm_counter0.v 1 1 " "Found 1 design units, including 1 entities, in source file lpm_counter0.v" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter0 " "Found entity 1: lpm_counter0" { } { { "lpm_counter0.v" "" { Text "D:/Projects/quartus/pc_ar/lpm_counter0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1698129295527 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1698129295527 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pc_ar2627.bdf 1 1 " "Found 1 design units, including 1 entities, in source file pc_ar2627.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 PC_AR2627 " "Found entity 1: PC_AR2627" { } { { "PC_AR2627.bdf" "" { Schematic "D:/Projects/quartus/pc_ar/PC_AR2627.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1698129295529 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1698129295529 ""} { "Info" "ISGN_START_ELABORATION_TOP" "PC_AR2627 " "Elaborating entity \"PC_AR2627\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1698129295565 ""} { "Warning" "WSGN_SEARCH_FILE" "reg8.bdf 1 1 " "Using design file reg8.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Reg8 " "Found entity 1: Reg8" { } { { "reg8.bdf" "" { Schematic "D:/Projects/quartus/pc_ar/reg8.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1698129295584 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1698129295584 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "Reg8 Reg8:inst " "Elaborating entity \"Reg8\" for hierarchy \"Reg8:inst\"" { } { { "PC_AR2627.bdf" "inst" { Schematic "D:/Projects/quartus/pc_ar/PC_AR2627.bdf" { { 224 856 992 320 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698129295584 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "BUSMUX BUSMUX:inst2 " "Elaborating entity \"BUSMUX\" for hierarchy \"BUSMUX:inst2\"" { } { { "PC_AR2627.bdf" "inst2" { Schematic "D:/Projects/quartus/pc_ar/PC_AR2627.bdf" { { 208 648 760 296 "inst2" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698129295602 ""} { "Info" "ISGN_ELABORATION_HEADER" "BUSMUX:inst2 " "Elaborated megafunction instantiation \"BUSMUX:inst2\"" { } { { "PC_AR2627.bdf" "" { Schematic "D:/Projects/quartus/pc_ar/PC_AR2627.bdf" { { 208 648 760 296 "inst2" "" } } } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698129295603 ""} { "Info" "ISGN_MEGAFN_PARAM_TOP" "BUSMUX:inst2 " "Instantiated megafunction \"BUSMUX:inst2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH 8 " "Parameter \"WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1698129295603 ""} } { { "PC_AR2627.bdf" "" { Schematic "D:/Projects/quartus/pc_ar/PC_AR2627.bdf" { { 208 648 760 296 "inst2" "" } } } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1698129295603 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mux BUSMUX:inst2\|lpm_mux:\$00000 " "Elaborating entity \"lpm_mux\" for hierarchy \"BUSMUX:inst2\|lpm_mux:\$00000\"" { } { { "busmux.tdf" "\$00000" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/busmux.tdf" 43 13 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698129295628 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "BUSMUX:inst2\|lpm_mux:\$00000 BUSMUX:inst2 " "Elaborated megafunction instantiation \"BUSMUX:inst2\|lpm_mux:\$00000\", which is child of megafunction instantiation \"BUSMUX:inst2\"" { } { { "busmux.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/busmux.tdf" 43 13 0 } } { "PC_AR2627.bdf" "" { Schematic "D:/Projects/quartus/pc_ar/PC_AR2627.bdf" { { 208 648 760 296 "inst2" "" } } } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698129295629 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_erc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_erc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_erc " "Found entity 1: mux_erc" { } { { "db/mux_erc.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/mux_erc.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1698129295666 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1698129295666 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_erc BUSMUX:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated " "Elaborating entity \"mux_erc\" for hierarchy \"BUSMUX:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\"" { } { { "lpm_mux.tdf" "auto_generated" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_mux.tdf" 86 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698129295667 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter0 lpm_counter0:inst5 " "Elaborating entity \"lpm_counter0\" for hierarchy \"lpm_counter0:inst5\"" { } { { "PC_AR2627.bdf" "inst5" { Schematic "D:/Projects/quartus/pc_ar/PC_AR2627.bdf" { { 136 408 552 232 "inst5" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698129295674 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter lpm_counter0:inst5\|lpm_counter:LPM_COUNTER_component " "Elaborating entity \"lpm_counter\" for hierarchy \"lpm_counter0:inst5\|lpm_counter:LPM_COUNTER_component\"" { } { { "lpm_counter0.v" "LPM_COUNTER_component" { Text "D:/Projects/quartus/pc_ar/lpm_counter0.v" 70 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698129295707 ""} { "Info" "ISGN_ELABORATION_HEADER" "lpm_counter0:inst5\|lpm_counter:LPM_COUNTER_component " "Elaborated megafunction instantiation \"lpm_counter0:inst5\|lpm_counter:LPM_COUNTER_component\"" { } { { "lpm_counter0.v" "" { Text "D:/Projects/quartus/pc_ar/lpm_counter0.v" 70 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698129295708 ""} { "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter0:inst5\|lpm_counter:LPM_COUNTER_component " "Instantiated megafunction \"lpm_counter0:inst5\|lpm_counter:LPM_COUNTER_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction UP " "Parameter \"lpm_direction\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1698129295708 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_port_updown PORT_UNUSED " "Parameter \"lpm_port_updown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1698129295708 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_COUNTER " "Parameter \"lpm_type\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1698129295708 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1698129295708 ""} } { { "lpm_counter0.v" "" { Text "D:/Projects/quartus/pc_ar/lpm_counter0.v" 70 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1698129295708 ""} { "Warning" "WTDFX_ASSERTION" "Counter will power up to an undefined state. An asynchronous signal should be asserted before the counter reaches a known state. " "Assertion warning: Counter will power up to an undefined state. An asynchronous signal should be asserted before the counter reaches a known state." { } { { "db/cntr_b6j.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/cntr_b6j.tdf" 152 2 0 } } } 0 287001 "Assertion warning: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1698129295747 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_b6j.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_b6j.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_b6j " "Found entity 1: cntr_b6j" { } { { "db/cntr_b6j.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/cntr_b6j.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1698129295748 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1698129295748 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_b6j lpm_counter0:inst5\|lpm_counter:LPM_COUNTER_component\|cntr_b6j:auto_generated " "Elaborating entity \"cntr_b6j\" for hierarchy \"lpm_counter0:inst5\|lpm_counter:LPM_COUNTER_component\|cntr_b6j:auto_generated\"" { } { { "lpm_counter.tdf" "auto_generated" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_counter.tdf" 258 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698129295748 ""} { "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1698129296125 ""} { "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1698129296507 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698129296507 ""} { "Info" "ICUT_CUT_TM_SUMMARY" "71 " "Implemented 71 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "13 " "Implemented 13 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1698129296535 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1698129296535 ""} { "Info" "ICUT_CUT_TM_LCELLS" "50 " "Implemented 50 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1698129296535 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1698129296535 ""} { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4839 " "Peak virtual memory: 4839 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1698129296546 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 24 14:34:56 2023 " "Processing ended: Tue Oct 24 14:34:56 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1698129296546 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1698129296546 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:19 " "Total CPU time (on all processors): 00:00:19" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1698129296546 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1698129296546 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1698129297697 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1698129297706 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 24 14:34:57 2023 " "Processing started: Tue Oct 24 14:34:57 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1698129297706 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1698129297706 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off PC_AR2627 -c PC_AR2627 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off PC_AR2627 -c PC_AR2627" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1698129297706 ""} { "Info" "0" "" "qfit2_default_script.tcl version: #3" { } { } 0 0 "qfit2_default_script.tcl version: #3" 0 0 "Fitter" 0 0 1698129297813 ""} { "Info" "0" "" "Project = PC_AR2627" { } { } 0 0 "Project = PC_AR2627" 0 0 "Fitter" 0 0 1698129297813 ""} { "Info" "0" "" "Revision = PC_AR2627" { } { } 0 0 "Revision = PC_AR2627" 0 0 "Fitter" 0 0 1698129297813 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1698129297869 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1698129297869 ""} { "Info" "IMPP_MPP_USER_DEVICE" "PC_AR2627 EP4CE55F23C8 " "Selected device EP4CE55F23C8 for design \"PC_AR2627\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1698129297874 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1698129297918 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1698129297918 ""} { "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1698129298071 ""} { "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1698129298074 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F23C8 " "Device EP4CE15F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1698129298178 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F23C8 " "Device EP4CE40F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1698129298178 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F23C8 " "Device EP4CE30F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1698129298178 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F23C8 " "Device EP4CE75F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1698129298178 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F23C8 " "Device EP4CE115F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1698129298178 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1698129298178 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" { } { { "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 153 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1698129298180 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 155 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1698129298180 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" { } { { "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 157 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1698129298180 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" { } { { "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 159 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1698129298180 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" { } { { "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 161 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1698129298180 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1698129298180 ""} { "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1698129298181 ""} { "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "21 21 " "No exact pin location assignment(s) for 21 pins of 21 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1698129298550 ""} { "Warning" "WTDB_ANALYZE_COMB_LATCHES" "8 " "TimeQuest Timing Analyzer is analyzing 8 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." { } { } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1698129298674 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "PC_AR2627.sdc " "Synopsys Design Constraints File file not found: 'PC_AR2627.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1698129298674 ""} { "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1698129298674 ""} { "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1698129298676 ""} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1698129298676 ""} { "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1698129298676 ""} { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "LOAD~input (placed in PIN G1 (CLK1, DIFFCLK_0n)) " "Automatically promoted node LOAD~input (placed in PIN G1 (CLK1, DIFFCLK_0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1698129298703 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[7\]~14 " "Destination node busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[7\]~14" { } { { "db/mux_erc.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/mux_erc.tdf" 29 13 0 } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 94 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1698129298703 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lpm_counter0:inst5\|lpm_counter:LPM_COUNTER_component\|cntr_b6j:auto_generated\|aclr_actual~0 " "Destination node lpm_counter0:inst5\|lpm_counter:LPM_COUNTER_component\|cntr_b6j:auto_generated\|aclr_actual~0" { } { { "db/cntr_b6j.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/cntr_b6j.tdf" 94 2 0 } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 95 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1698129298703 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[6\]~16 " "Destination node busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[6\]~16" { } { { "db/mux_erc.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/mux_erc.tdf" 29 13 0 } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 97 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1698129298703 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[5\]~18 " "Destination node busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[5\]~18" { } { { "db/mux_erc.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/mux_erc.tdf" 29 13 0 } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 99 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1698129298703 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[4\]~20 " "Destination node busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[4\]~20" { } { { "db/mux_erc.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/mux_erc.tdf" 29 13 0 } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 101 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1698129298703 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[3\]~22 " "Destination node busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[3\]~22" { } { { "db/mux_erc.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/mux_erc.tdf" 29 13 0 } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 103 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1698129298703 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[2\]~24 " "Destination node busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[2\]~24" { } { { "db/mux_erc.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/mux_erc.tdf" 29 13 0 } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 105 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1698129298703 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[1\]~26 " "Destination node busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[1\]~26" { } { { "db/mux_erc.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/mux_erc.tdf" 29 13 0 } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 107 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1698129298703 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[0\]~28 " "Destination node busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[0\]~28" { } { { "db/mux_erc.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/mux_erc.tdf" 29 13 0 } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 109 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1698129298703 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[7\]~30 " "Destination node busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[7\]~30" { } { { "db/mux_erc.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/mux_erc.tdf" 29 13 0 } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 127 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1698129298703 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1698129298703 ""} } { { "PC_AR2627.bdf" "" { Schematic "D:/Projects/quartus/pc_ar/PC_AR2627.bdf" { { 328 152 320 344 "LOAD" "" } } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 138 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1698129298703 ""} { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "T2~input (placed in PIN T2 (CLK2, DIFFCLK_1p)) " "Automatically promoted node T2~input (placed in PIN T2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1698129298703 ""} } { { "PC_AR2627.bdf" "" { Schematic "D:/Projects/quartus/pc_ar/PC_AR2627.bdf" { { 192 152 320 208 "T2" "" } } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 148 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1698129298703 ""} { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "T4~input (placed in PIN T1 (CLK3, DIFFCLK_1n)) " "Automatically promoted node T4~input (placed in PIN T1 (CLK3, DIFFCLK_1n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1698129298703 ""} } { { "PC_AR2627.bdf" "" { Schematic "D:/Projects/quartus/pc_ar/PC_AR2627.bdf" { { 400 152 320 416 "T4" "" } } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 140 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1698129298703 ""} { "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1698129298850 ""} { "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1698129298851 ""} { "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1698129298851 ""} { "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1698129298851 ""} { "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1698129298851 ""} { "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1698129298851 ""} { "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1698129298851 ""} { "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1698129298852 ""} { "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1698129298859 ""} { "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1698129298859 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1698129298859 ""} { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "18 unused 2.5V 10 8 0 " "Number of I/O pins in group: 18 (unused VREF, 2.5V VCCIO, 10 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1698129298861 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1698129298861 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1698129298861 ""} { "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 5 28 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used -- 28 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1698129298861 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 2 39 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 39 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1698129298861 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 42 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 42 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1698129298861 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 43 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1698129298861 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 41 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 41 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1698129298861 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 38 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 38 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1698129298861 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 43 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1698129298861 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1698129298861 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1698129298861 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1698129298861 ""} { "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1698129298878 ""} { "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1698129298881 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1698129299775 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1698129299839 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1698129299855 ""} { "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1698129301837 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1698129301837 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1698129301980 ""} { "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y10 X10_Y20 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X10_Y20" { } { { "loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X10_Y20"} { { 12 { 0 ""} 0 10 11 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1698129303133 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1698129303133 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1698129303425 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1698129303425 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1698129303428 ""} { "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.12 " "Total time spent on timing analysis during the Fitter is 0.12 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1698129303516 ""} { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1698129303521 ""} { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1698129303647 ""} { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1698129303647 ""} { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1698129303775 ""} { "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1698129304041 ""} { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/Projects/quartus/pc_ar/output_files/PC_AR2627.fit.smsg " "Generated suppressed messages file D:/Projects/quartus/pc_ar/output_files/PC_AR2627.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1698129304290 ""} { "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "6565 " "Peak virtual memory: 6565 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1698129304526 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 24 14:35:04 2023 " "Processing ended: Tue Oct 24 14:35:04 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1698129304526 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1698129304526 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:14 " "Total CPU time (on all processors): 00:00:14" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1698129304526 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1698129304526 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1698129305513 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1698129305522 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 24 14:35:05 2023 " "Processing started: Tue Oct 24 14:35:05 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1698129305522 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1698129305522 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off PC_AR2627 -c PC_AR2627 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off PC_AR2627 -c PC_AR2627" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1698129305522 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1698129305763 ""} { "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1698129306709 ""} { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1698129306745 ""} { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4671 " "Peak virtual memory: 4671 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1698129306883 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 24 14:35:06 2023 " "Processing ended: Tue Oct 24 14:35:06 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1698129306883 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1698129306883 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1698129306883 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1698129306883 ""} { "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1698129307478 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1698129307994 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1698129308002 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 24 14:35:07 2023 " "Processing started: Tue Oct 24 14:35:07 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1698129308002 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308002 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta PC_AR2627 -c PC_AR2627 " "Command: quartus_sta PC_AR2627 -c PC_AR2627" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308003 ""} { "Info" "0" "" "qsta_default_script.tcl version: #3" { } { } 0 0 "qsta_default_script.tcl version: #3" 0 0 "TimeQuest Timing Analyzer" 0 0 1698129308109 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308258 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308258 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308303 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308303 ""} { "Warning" "WTDB_ANALYZE_COMB_LATCHES" "8 " "TimeQuest Timing Analyzer is analyzing 8 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." { } { } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308505 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "PC_AR2627.sdc " "Synopsys Design Constraints File file not found: 'PC_AR2627.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308515 ""} { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308515 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name T2 T2 " "create_clock -period 1.000 -name T2 T2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1698129308516 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name LOAD LOAD " "create_clock -period 1.000 -name LOAD LOAD" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1698129308516 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name T4 T4 " "create_clock -period 1.000 -name T4 T4" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1698129308516 ""} } { } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308516 ""} { "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308516 ""} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308517 ""} { "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1698129308517 ""} { "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1698129308523 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1698129308531 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308531 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -3.359 " "Worst-case setup slack is -3.359" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308533 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308533 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.359 -22.917 T2 " " -3.359 -22.917 T2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308533 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.795 -21.045 T4 " " -2.795 -21.045 T4 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308533 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308533 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.584 " "Worst-case hold slack is 0.584" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.584 0.000 T4 " " 0.584 0.000 T4 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.624 0.000 T2 " " 0.624 0.000 T2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308535 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308535 ""} { "Info" "ISTA_WORST_CASE_SLACK" "recovery -2.360 " "Worst-case recovery slack is -2.360" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308537 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308537 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.360 -18.581 T2 " " -2.360 -18.581 T2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308537 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308537 ""} { "Info" "ISTA_WORST_CASE_SLACK" "removal 1.876 " "Worst-case removal slack is 1.876" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308538 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308538 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.876 0.000 T2 " " 1.876 0.000 T2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308538 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308538 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308540 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308540 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -14.896 T2 " " -3.000 -14.896 T2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308540 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -14.896 T4 " " -3.000 -14.896 T4 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308540 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -3.000 LOAD " " -3.000 -3.000 LOAD " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308540 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308540 ""} { "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1698129308565 ""} { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308581 ""} { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308744 ""} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308782 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1698129308785 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308785 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -3.035 " "Worst-case setup slack is -3.035" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308787 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308787 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.035 -20.735 T2 " " -3.035 -20.735 T2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308787 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.674 -21.011 T4 " " -2.674 -21.011 T4 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308787 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308787 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.535 " "Worst-case hold slack is 0.535" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308790 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308790 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.535 0.000 T4 " " 0.535 0.000 T4 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308790 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.571 0.000 T2 " " 0.571 0.000 T2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308790 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308790 ""} { "Info" "ISTA_WORST_CASE_SLACK" "recovery -2.230 " "Worst-case recovery slack is -2.230" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308794 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308794 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.230 -17.575 T2 " " -2.230 -17.575 T2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308794 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308794 ""} { "Info" "ISTA_WORST_CASE_SLACK" "removal 1.778 " "Worst-case removal slack is 1.778" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308796 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308796 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.778 0.000 T2 " " 1.778 0.000 T2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308796 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308796 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308799 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308799 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -14.896 T2 " " -3.000 -14.896 T2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308799 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -14.896 T4 " " -3.000 -14.896 T4 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308799 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -3.000 LOAD " " -3.000 -3.000 LOAD " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308799 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308799 ""} { "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1698129308827 ""} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308907 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1698129308908 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308908 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -1.551 " "Worst-case setup slack is -1.551" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308911 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308911 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.551 -10.700 T2 " " -1.551 -10.700 T2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308911 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.172 -8.748 T4 " " -1.172 -8.748 T4 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308911 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308911 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.341 " "Worst-case hold slack is 0.341" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308915 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308915 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.341 0.000 T4 " " 0.341 0.000 T4 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308915 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.727 0.000 T2 " " 0.727 0.000 T2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308915 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308915 ""} { "Info" "ISTA_WORST_CASE_SLACK" "recovery -1.001 " "Worst-case recovery slack is -1.001" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308918 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308918 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.001 -7.868 T2 " " -1.001 -7.868 T2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308918 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308918 ""} { "Info" "ISTA_WORST_CASE_SLACK" "removal 0.768 " "Worst-case removal slack is 0.768" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308920 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308920 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.768 0.000 T2 " " 0.768 0.000 T2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308920 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308920 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308923 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308923 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -11.464 T2 " " -3.000 -11.464 T2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308923 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -11.456 T4 " " -3.000 -11.456 T4 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308923 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -3.000 LOAD " " -3.000 -3.000 LOAD " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698129308923 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129308923 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129309214 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129309215 ""} { "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4928 " "Peak virtual memory: 4928 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1698129309254 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 24 14:35:09 2023 " "Processing ended: Tue Oct 24 14:35:09 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1698129309254 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1698129309254 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1698129309254 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129309254 ""} { "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 16 s " "Quartus Prime Full Compilation was successful. 0 errors, 16 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698129309926 ""}