vendor_name = ModelSim
source_file = 1, F:/quartus/pc_ar/PC_AR.bdf
source_file = 1, F:/quartus/pc_ar/lpm_counter0.qip
source_file = 1, F:/quartus/pc_ar/lpm_counter0.v
source_file = 1, F:/quartus/pc_ar/reg8.bdf
source_file = 1, c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/busmux.tdf
source_file = 1, c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_mux.inc
source_file = 1, c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_mux.tdf
source_file = 1, c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/aglobal171.inc
source_file = 1, c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/muxlut.inc
source_file = 1, c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/bypassff.inc
source_file = 1, c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altshift.inc
source_file = 1, c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/cbx.lst
source_file = 1, F:/quartus/pc_ar/db/mux_erc.tdf
source_file = 1, c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_counter.tdf
source_file = 1, c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_constant.inc
source_file = 1, c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_decode.inc
source_file = 1, c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_add_sub.inc
source_file = 1, c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/cmpconst.inc
source_file = 1, c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_compare.inc
source_file = 1, c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_counter.inc
source_file = 1, c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/dffeea.inc
source_file = 1, c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/alt_counter_stratix.inc
source_file = 1, F:/quartus/pc_ar/db/cntr_b6j.tdf
design_name = PC_AR
instance = comp, \Q[7]~output , Q[7]~output, PC_AR, 1
instance = comp, \Q[6]~output , Q[6]~output, PC_AR, 1
instance = comp, \Q[5]~output , Q[5]~output, PC_AR, 1
instance = comp, \Q[4]~output , Q[4]~output, PC_AR, 1
instance = comp, \Q[3]~output , Q[3]~output, PC_AR, 1
instance = comp, \Q[2]~output , Q[2]~output, PC_AR, 1
instance = comp, \Q[1]~output , Q[1]~output, PC_AR, 1
instance = comp, \Q[0]~output , Q[0]~output, PC_AR, 1
instance = comp, \T4~input , T4~input, PC_AR, 1
instance = comp, \T4~inputclkctrl , T4~inputclkctrl, PC_AR, 1
instance = comp, \CLR~input , CLR~input, PC_AR, 1
instance = comp, \LOAD~input , LOAD~input, PC_AR, 1
instance = comp, \PC_B~input , PC_B~input, PC_AR, 1
instance = comp, \inst2|$00000|auto_generated|result_node[7]~30 , inst2|$00000|auto_generated|result_node[7]~30, PC_AR, 1
instance = comp, \D[7]~input , D[7]~input, PC_AR, 1
instance = comp, \inst2|$00000|auto_generated|result_node[7]~14 , inst2|$00000|auto_generated|result_node[7]~14, PC_AR, 1
instance = comp, \T2~input , T2~input, PC_AR, 1
instance = comp, \T2~inputclkctrl , T2~inputclkctrl, PC_AR, 1
instance = comp, \LOAD~inputclkctrl , LOAD~inputclkctrl, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|latch_signal[7]~8 , inst5|LPM_COUNTER_component|auto_generated|latch_signal[7]~8, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|pre_hazard[7] , inst5|LPM_COUNTER_component|auto_generated|pre_hazard[7], PC_AR, 1
instance = comp, \D[5]~input , D[5]~input, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|latch_signal[5]~10 , inst5|LPM_COUNTER_component|auto_generated|latch_signal[5]~10, PC_AR, 1
instance = comp, \D[4]~input , D[4]~input, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|latch_signal[4]~11 , inst5|LPM_COUNTER_component|auto_generated|latch_signal[4]~11, PC_AR, 1
instance = comp, \D[3]~input , D[3]~input, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|latch_signal[3]~12 , inst5|LPM_COUNTER_component|auto_generated|latch_signal[3]~12, PC_AR, 1
instance = comp, \D[2]~input , D[2]~input, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|latch_signal[2]~13 , inst5|LPM_COUNTER_component|auto_generated|latch_signal[2]~13, PC_AR, 1
instance = comp, \D[1]~input , D[1]~input, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|latch_signal[1]~14 , inst5|LPM_COUNTER_component|auto_generated|latch_signal[1]~14, PC_AR, 1
instance = comp, \D[0]~input , D[0]~input, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|latch_signal[0]~15 , inst5|LPM_COUNTER_component|auto_generated|latch_signal[0]~15, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita0 , inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita0, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[0]~7 , inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[0]~7, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|aclr_actual~0 , inst5|LPM_COUNTER_component|auto_generated|aclr_actual~0, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[0] , inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[0], PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|pre_hazard[0] , inst5|LPM_COUNTER_component|auto_generated|pre_hazard[0], PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita1 , inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita1, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[1]~6 , inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[1]~6, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[1] , inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[1], PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|pre_hazard[1] , inst5|LPM_COUNTER_component|auto_generated|pre_hazard[1], PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita2 , inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita2, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[2]~5 , inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[2]~5, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[2] , inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[2], PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|pre_hazard[2] , inst5|LPM_COUNTER_component|auto_generated|pre_hazard[2], PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita3 , inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita3, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[3]~4 , inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[3]~4, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[3] , inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[3], PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|pre_hazard[3] , inst5|LPM_COUNTER_component|auto_generated|pre_hazard[3], PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita4 , inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita4, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[4]~3 , inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[4]~3, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[4] , inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[4], PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|pre_hazard[4] , inst5|LPM_COUNTER_component|auto_generated|pre_hazard[4], PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita5 , inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita5, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[5]~2 , inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[5]~2, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[5] , inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[5], PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|pre_hazard[5] , inst5|LPM_COUNTER_component|auto_generated|pre_hazard[5], PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita6 , inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita6, PC_AR, 1
instance = comp, \D[6]~input , D[6]~input, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|latch_signal[6]~9 , inst5|LPM_COUNTER_component|auto_generated|latch_signal[6]~9, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[6]~1 , inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[6]~1, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[6] , inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[6], PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|pre_hazard[6] , inst5|LPM_COUNTER_component|auto_generated|pre_hazard[6], PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita7 , inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita7, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[7]~0 , inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[7]~0, PC_AR, 1
instance = comp, \inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[7] , inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[7], PC_AR, 1
instance = comp, \inst2|$00000|auto_generated|result_node[7]~15 , inst2|$00000|auto_generated|result_node[7]~15, PC_AR, 1
instance = comp, \inst|12 , inst|12, PC_AR, 1
instance = comp, \inst2|$00000|auto_generated|result_node[6]~16 , inst2|$00000|auto_generated|result_node[6]~16, PC_AR, 1
instance = comp, \inst2|$00000|auto_generated|result_node[6]~17 , inst2|$00000|auto_generated|result_node[6]~17, PC_AR, 1
instance = comp, \inst|13 , inst|13, PC_AR, 1
instance = comp, \inst2|$00000|auto_generated|result_node[5]~18 , inst2|$00000|auto_generated|result_node[5]~18, PC_AR, 1
instance = comp, \inst2|$00000|auto_generated|result_node[5]~19 , inst2|$00000|auto_generated|result_node[5]~19, PC_AR, 1
instance = comp, \inst|14 , inst|14, PC_AR, 1
instance = comp, \inst2|$00000|auto_generated|result_node[4]~20 , inst2|$00000|auto_generated|result_node[4]~20, PC_AR, 1
instance = comp, \inst2|$00000|auto_generated|result_node[4]~21 , inst2|$00000|auto_generated|result_node[4]~21, PC_AR, 1
instance = comp, \inst|15 , inst|15, PC_AR, 1
instance = comp, \inst2|$00000|auto_generated|result_node[3]~22 , inst2|$00000|auto_generated|result_node[3]~22, PC_AR, 1
instance = comp, \inst2|$00000|auto_generated|result_node[3]~23 , inst2|$00000|auto_generated|result_node[3]~23, PC_AR, 1
instance = comp, \inst|16 , inst|16, PC_AR, 1
instance = comp, \inst2|$00000|auto_generated|result_node[2]~24 , inst2|$00000|auto_generated|result_node[2]~24, PC_AR, 1
instance = comp, \inst2|$00000|auto_generated|result_node[2]~25 , inst2|$00000|auto_generated|result_node[2]~25, PC_AR, 1
instance = comp, \inst|17 , inst|17, PC_AR, 1
instance = comp, \inst2|$00000|auto_generated|result_node[1]~26 , inst2|$00000|auto_generated|result_node[1]~26, PC_AR, 1
instance = comp, \inst2|$00000|auto_generated|result_node[1]~27 , inst2|$00000|auto_generated|result_node[1]~27, PC_AR, 1
instance = comp, \inst|18 , inst|18, PC_AR, 1
instance = comp, \inst2|$00000|auto_generated|result_node[0]~28 , inst2|$00000|auto_generated|result_node[0]~28, PC_AR, 1
instance = comp, \inst2|$00000|auto_generated|result_node[0]~29 , inst2|$00000|auto_generated|result_node[0]~29, PC_AR, 1
instance = comp, \inst|19 , inst|19, PC_AR, 1
design_name = hard_block
instance = comp, \~ALTERA_ASDO_DATA1~~ibuf , ~ALTERA_ASDO_DATA1~~ibuf, hard_block, 1
instance = comp, \~ALTERA_FLASH_nCE_nCSO~~ibuf , ~ALTERA_FLASH_nCE_nCSO~~ibuf, hard_block, 1
instance = comp, \~ALTERA_DATA0~~ibuf , ~ALTERA_DATA0~~ibuf, hard_block, 1