// Copyright (C) 2017  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "10/24/2023 15:33:36"
                                                                                
// Verilog Test Bench (with test vectors) for design :                          PC_AR2627
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module PC_AR2627_vlg_vec_tst();
// constants                                           
// general purpose registers
reg CLR;
reg [7:0] D;
reg LOAD;
reg PC_B;
reg T2;
reg T4;
// wires                                               
wire [7:0] Q;

// assign statements (if any)                          
PC_AR2627 i1 (
// port map - connection between master ports and signals/registers   
	.CLR(CLR),
	.D(D),
	.LOAD(LOAD),
	.PC_B(PC_B),
	.Q(Q),
	.T2(T2),
	.T4(T4)
);
initial 
begin 
#140000 $finish;
end 

// T2
initial
begin
	T2 = 1'b0;
	T2 = #5000 1'b1;
	# 5000;
	repeat(2)
	begin
		T2 = 1'b0;
		T2 = #5000 1'b1;
		# 5000;
	end
	T2 = 1'b0;
	T2 = #15000 1'b1;
	T2 = #5000 1'b0;
	T2 = #5000 1'b1;
	T2 = #5000 1'b0;
	T2 = #15000 1'b1;
	T2 = #5000 1'b0;
	T2 = #5000 1'b1;
	T2 = #5000 1'b0;
	T2 = #15000 1'b1;
	# 5000;
	repeat(3)
	begin
		T2 = 1'b0;
		T2 = #5000 1'b1;
		# 5000;
	end
end 

// T4
initial
begin
	T4 = 1'b0;
	T4 = #10000 1'b1;
	# 5000;
	repeat(12)
	begin
		T4 = 1'b0;
		T4 = #5000 1'b1;
		# 5000;
	end
	T4 = 1'b0;
end 
// D[ 7 ]
initial
begin
	D[7] = 1'b0;
end 
// D[ 6 ]
initial
begin
	D[6] = 1'b0;
end 
// D[ 5 ]
initial
begin
	D[5] = 1'b0;
end 
// D[ 4 ]
initial
begin
	D[4] = 1'b0;
end 
// D[ 3 ]
initial
begin
	D[3] = 1'b0;
	D[3] = #35000 1'b1;
	D[3] = #10000 1'b0;
	D[3] = #20000 1'b1;
	D[3] = #10000 1'b0;
	D[3] = #20000 1'b1;
	D[3] = #10000 1'b0;
end 
// D[ 2 ]
initial
begin
	D[2] = 1'b0;
end 
// D[ 1 ]
initial
begin
	D[1] = 1'b0;
	D[1] = #35000 1'b1;
	D[1] = #10000 1'b0;
	D[1] = #20000 1'b1;
	D[1] = #10000 1'b0;
	D[1] = #20000 1'b1;
	D[1] = #10000 1'b0;
end 
// D[ 0 ]
initial
begin
	D[0] = 1'b0;
	D[0] = #65000 1'b1;
	D[0] = #10000 1'b0;
	D[0] = #20000 1'b1;
	D[0] = #10000 1'b0;
	D[0] = #15000 1'b1;
	D[0] = #10000 1'b0;
end 

// CLR
initial
begin
	CLR = 1'b1;
	CLR = #5000 1'b0;
end 

// LOAD
initial
begin
	LOAD = 1'b0;
	LOAD = #120000 1'b1;
	LOAD = #10000 1'b0;
end 

// PC_B
initial
begin
	PC_B = 1'b0;
	PC_B = #35000 1'b1;
	PC_B = #10000 1'b0;
	PC_B = #20000 1'b1;
	PC_B = #10000 1'b0;
	PC_B = #20000 1'b1;
	PC_B = #10000 1'b0;
end 
endmodule