vendor_name = ModelSim
source_file = 1, D:/Projects/quartus/ram/ram2627.bdf
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_ram_dq.tdf
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altram.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_mux.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_decode.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/aglobal171.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/cbx.lst
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altram.tdf
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/others/maxplus2/memmodes.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altsyncram.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altsyncram.tdf
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/stratix_ram_block.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/a_rdenreg.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altrom.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altdpram.inc
source_file = 1, D:/Projects/quartus/ram/db/altsyncram_ap71.tdf
design_name = ram2627
instance = comp, \q[7]~output , q[7]~output, ram2627, 1
instance = comp, \q[6]~output , q[6]~output, ram2627, 1
instance = comp, \q[5]~output , q[5]~output, ram2627, 1
instance = comp, \q[4]~output , q[4]~output, ram2627, 1
instance = comp, \q[3]~output , q[3]~output, ram2627, 1
instance = comp, \q[2]~output , q[2]~output, ram2627, 1
instance = comp, \q[1]~output , q[1]~output, ram2627, 1
instance = comp, \q[0]~output , q[0]~output, ram2627, 1
instance = comp, \we~input , we~input, ram2627, 1
instance = comp, \clock~input , clock~input, ram2627, 1
instance = comp, \clock~inputclkctrl , clock~inputclkctrl, ram2627, 1
instance = comp, \data[0]~input , data[0]~input, ram2627, 1
instance = comp, \address[0]~input , address[0]~input, ram2627, 1
instance = comp, \address[1]~input , address[1]~input, ram2627, 1
instance = comp, \address[2]~input , address[2]~input, ram2627, 1
instance = comp, \address[3]~input , address[3]~input, ram2627, 1
instance = comp, \address[4]~input , address[4]~input, ram2627, 1
instance = comp, \address[5]~input , address[5]~input, ram2627, 1
instance = comp, \address[6]~input , address[6]~input, ram2627, 1
instance = comp, \address[7]~input , address[7]~input, ram2627, 1
instance = comp, \data[1]~input , data[1]~input, ram2627, 1
instance = comp, \data[2]~input , data[2]~input, ram2627, 1
instance = comp, \data[3]~input , data[3]~input, ram2627, 1
instance = comp, \data[4]~input , data[4]~input, ram2627, 1
instance = comp, \data[5]~input , data[5]~input, ram2627, 1
instance = comp, \data[6]~input , data[6]~input, ram2627, 1
instance = comp, \data[7]~input , data[7]~input, ram2627, 1
instance = comp, \inst|sram|ram_block|auto_generated|ram_block1a0 , inst|sram|ram_block|auto_generated|ram_block1a0, ram2627, 1
design_name = hard_block
instance = comp, \~ALTERA_ASDO_DATA1~~ibuf , ~ALTERA_ASDO_DATA1~~ibuf, hard_block, 1
instance = comp, \~ALTERA_FLASH_nCE_nCSO~~ibuf , ~ALTERA_FLASH_nCE_nCSO~~ibuf, hard_block, 1
instance = comp, \~ALTERA_DATA0~~ibuf , ~ALTERA_DATA0~~ibuf, hard_block, 1