Determining the location of the ModelSim executable...

Using: d:/intelfpga_lite/17.1/modelsim_ase/win32aloem/

To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.

**** Generating the ModelSim Testbench ****

quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off ram2627 -c ram2627 --vector_source="D:/Projects/quartus/ram/Waveform.vwf" --testbench_file="D:/Projects/quartus/ram/simulation/qsim/Waveform.vwf.vt"

Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
    Info: Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
    Info: Copyright (C) 2017  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Tue Oct 10 00:12:05 2023
Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off ram2627 -c ram2627 --vector_source=D:/Projects/quartus/ram/Waveform.vwf --testbench_file=D:/Projects/quartus/ram/simulation/qsim/Waveform.vwf.vt
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

Completed successfully. 

Completed successfully. 

**** Generating the functional simulation netlist ****

quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="D:/Projects/quartus/ram/simulation/qsim/" ram2627 -c ram2627

Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
    Info: Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
    Info: Copyright (C) 2017  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Tue Oct 10 00:12:06 2023
Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=D:/Projects/quartus/ram/simulation/qsim/ ram2627 -c ram2627
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file ram2627.vo in folder "D:/Projects/quartus/ram/simulation/qsim//" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 4633 megabytes
    Info: Processing ended: Tue Oct 10 00:12:06 2023
    Info: Elapsed time: 00:00:00
    Info: Total CPU time (on all processors): 00:00:00

Completed successfully. 

**** Generating the ModelSim .do script ****

D:/Projects/quartus/ram/simulation/qsim/ram2627.do generated.

Completed successfully. 

**** Running the ModelSim simulation ****

d:/intelfpga_lite/17.1/modelsim_ase/win32aloem//vsim -c -do ram2627.do

Reading D:/intelFPGA_lite/17.1/modelsim_ase/tcl/vsim/pref.tcl


# 10.5b

# do ram2627.do
# ** Warning: (vlib-34) Library already exists at "work".

# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 00:12:07 on Oct 10,2023
# vlog -work work ram2627.vo 
# -- Compiling module ram2627
# -- Compiling module hard_block
# 
# Top level modules:
# 	ram2627
# End time: 00:12:07 on Oct 10,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0

# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 00:12:07 on Oct 10,2023
# vlog -work work Waveform.vwf.vt 
# -- Compiling module ram2627_vlg_vec_tst
# 
# Top level modules:
# 	ram2627_vlg_vec_tst
# End time: 00:12:07 on Oct 10,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0

# vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.ram2627_vlg_vec_tst 
# Start time: 00:12:07 on Oct 10,2023
# Loading work.ram2627_vlg_vec_tst
# Loading work.ram2627
# Loading work.hard_block
# Loading cycloneive_ver.cycloneive_io_obuf
# Loading cycloneive_ver.cycloneive_io_ibuf
# Loading cycloneive_ver.cycloneive_clkctrl
# Loading cycloneive_ver.cycloneive_mux41
# Loading cycloneive_ver.cycloneive_ena_reg
# Loading cycloneive_ver.cycloneive_ram_block
# Loading cycloneive_ver.cycloneive_ram_register
# Loading cycloneive_ver.cycloneive_ram_pulse_generator
# after#26
# ** Note: $finish    : Waveform.vwf.vt(50)
#    Time: 64 ns  Iteration: 0  Instance: /ram2627_vlg_vec_tst
# End time: 00:12:08 on Oct 10,2023, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0

Completed successfully. 

**** Converting ModelSim VCD to vector waveform ****

Reading D:/Projects/quartus/ram/Waveform.vwf...

Reading D:/Projects/quartus/ram/simulation/qsim/ram2627.msim.vcd...

Processing channel transitions... 

Writing the resulting VWF to D:/Projects/quartus/ram/simulation/qsim/ram2627_20231010001208.sim.vwf

Finished VCD to VWF conversion.

Completed successfully. 

All completed.