|rom2627 q[0] <= LPM_ROM:inst.q[0] q[1] <= LPM_ROM:inst.q[1] q[2] <= LPM_ROM:inst.q[2] q[3] <= LPM_ROM:inst.q[3] q[4] <= LPM_ROM:inst.q[4] q[5] <= LPM_ROM:inst.q[5] q[6] <= LPM_ROM:inst.q[6] q[7] <= LPM_ROM:inst.q[7] q[8] <= LPM_ROM:inst.q[8] q[9] <= LPM_ROM:inst.q[9] q[10] <= LPM_ROM:inst.q[10] q[11] <= LPM_ROM:inst.q[11] q[12] <= LPM_ROM:inst.q[12] q[13] <= LPM_ROM:inst.q[13] q[14] <= LPM_ROM:inst.q[14] q[15] <= LPM_ROM:inst.q[15] q[16] <= LPM_ROM:inst.q[16] q[17] <= LPM_ROM:inst.q[17] q[18] <= LPM_ROM:inst.q[18] q[19] <= LPM_ROM:inst.q[19] q[20] <= LPM_ROM:inst.q[20] q[21] <= LPM_ROM:inst.q[21] q[22] <= LPM_ROM:inst.q[22] q[23] <= LPM_ROM:inst.q[23] clock => LPM_ROM:inst.inclock address[0] => LPM_ROM:inst.address[0] address[1] => LPM_ROM:inst.address[1] address[2] => LPM_ROM:inst.address[2] address[3] => LPM_ROM:inst.address[3] address[4] => LPM_ROM:inst.address[4] address[5] => LPM_ROM:inst.address[5] |rom2627|LPM_ROM:inst address[0] => altrom:srom.address[0] address[1] => altrom:srom.address[1] address[2] => altrom:srom.address[2] address[3] => altrom:srom.address[3] address[4] => altrom:srom.address[4] address[5] => altrom:srom.address[5] inclock => altrom:srom.clocki outclock => ~NO_FANOUT~ memenab => otri[23].OE memenab => otri[22].OE memenab => otri[21].OE memenab => otri[20].OE memenab => otri[19].OE memenab => otri[18].OE memenab => otri[17].OE memenab => otri[16].OE memenab => otri[15].OE memenab => otri[14].OE memenab => otri[13].OE memenab => otri[12].OE memenab => otri[11].OE memenab => otri[10].OE memenab => otri[9].OE memenab => otri[8].OE memenab => otri[7].OE memenab => otri[6].OE memenab => otri[5].OE memenab => otri[4].OE memenab => otri[3].OE memenab => otri[2].OE memenab => otri[1].OE memenab => otri[0].OE q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE q[4] <= otri[4].DB_MAX_OUTPUT_PORT_TYPE q[5] <= otri[5].DB_MAX_OUTPUT_PORT_TYPE q[6] <= otri[6].DB_MAX_OUTPUT_PORT_TYPE q[7] <= otri[7].DB_MAX_OUTPUT_PORT_TYPE q[8] <= otri[8].DB_MAX_OUTPUT_PORT_TYPE q[9] <= otri[9].DB_MAX_OUTPUT_PORT_TYPE q[10] <= otri[10].DB_MAX_OUTPUT_PORT_TYPE q[11] <= otri[11].DB_MAX_OUTPUT_PORT_TYPE q[12] <= otri[12].DB_MAX_OUTPUT_PORT_TYPE q[13] <= otri[13].DB_MAX_OUTPUT_PORT_TYPE q[14] <= otri[14].DB_MAX_OUTPUT_PORT_TYPE q[15] <= otri[15].DB_MAX_OUTPUT_PORT_TYPE q[16] <= otri[16].DB_MAX_OUTPUT_PORT_TYPE q[17] <= otri[17].DB_MAX_OUTPUT_PORT_TYPE q[18] <= otri[18].DB_MAX_OUTPUT_PORT_TYPE q[19] <= otri[19].DB_MAX_OUTPUT_PORT_TYPE q[20] <= otri[20].DB_MAX_OUTPUT_PORT_TYPE q[21] <= otri[21].DB_MAX_OUTPUT_PORT_TYPE q[22] <= otri[22].DB_MAX_OUTPUT_PORT_TYPE q[23] <= otri[23].DB_MAX_OUTPUT_PORT_TYPE |rom2627|LPM_ROM:inst|altrom:srom address[0] => altsyncram:rom_block.address_a[0] address[1] => altsyncram:rom_block.address_a[1] address[2] => altsyncram:rom_block.address_a[2] address[3] => altsyncram:rom_block.address_a[3] address[4] => altsyncram:rom_block.address_a[4] address[5] => altsyncram:rom_block.address_a[5] clocki => altsyncram:rom_block.clock0 clocko => ~NO_FANOUT~ q[0] <= altsyncram:rom_block.q_a[0] q[1] <= altsyncram:rom_block.q_a[1] q[2] <= altsyncram:rom_block.q_a[2] q[3] <= altsyncram:rom_block.q_a[3] q[4] <= altsyncram:rom_block.q_a[4] q[5] <= altsyncram:rom_block.q_a[5] q[6] <= altsyncram:rom_block.q_a[6] q[7] <= altsyncram:rom_block.q_a[7] q[8] <= altsyncram:rom_block.q_a[8] q[9] <= altsyncram:rom_block.q_a[9] q[10] <= altsyncram:rom_block.q_a[10] q[11] <= altsyncram:rom_block.q_a[11] q[12] <= altsyncram:rom_block.q_a[12] q[13] <= altsyncram:rom_block.q_a[13] q[14] <= altsyncram:rom_block.q_a[14] q[15] <= altsyncram:rom_block.q_a[15] q[16] <= altsyncram:rom_block.q_a[16] q[17] <= altsyncram:rom_block.q_a[17] q[18] <= altsyncram:rom_block.q_a[18] q[19] <= altsyncram:rom_block.q_a[19] q[20] <= altsyncram:rom_block.q_a[20] q[21] <= altsyncram:rom_block.q_a[21] q[22] <= altsyncram:rom_block.q_a[22] q[23] <= altsyncram:rom_block.q_a[23] |rom2627|LPM_ROM:inst|altrom:srom|altsyncram:rom_block wren_a => ~NO_FANOUT~ rden_a => ~NO_FANOUT~ wren_b => ~NO_FANOUT~ rden_b => ~NO_FANOUT~ data_a[0] => ~NO_FANOUT~ data_a[1] => ~NO_FANOUT~ data_a[2] => ~NO_FANOUT~ data_a[3] => ~NO_FANOUT~ data_a[4] => ~NO_FANOUT~ data_a[5] => ~NO_FANOUT~ data_a[6] => ~NO_FANOUT~ data_a[7] => ~NO_FANOUT~ data_a[8] => ~NO_FANOUT~ data_a[9] => ~NO_FANOUT~ data_a[10] => ~NO_FANOUT~ data_a[11] => ~NO_FANOUT~ data_a[12] => ~NO_FANOUT~ data_a[13] => ~NO_FANOUT~ data_a[14] => ~NO_FANOUT~ data_a[15] => ~NO_FANOUT~ data_a[16] => ~NO_FANOUT~ data_a[17] => ~NO_FANOUT~ data_a[18] => ~NO_FANOUT~ data_a[19] => ~NO_FANOUT~ data_a[20] => ~NO_FANOUT~ data_a[21] => ~NO_FANOUT~ data_a[22] => ~NO_FANOUT~ data_a[23] => ~NO_FANOUT~ data_b[0] => ~NO_FANOUT~ address_a[0] => altsyncram_2501:auto_generated.address_a[0] address_a[1] => altsyncram_2501:auto_generated.address_a[1] address_a[2] => altsyncram_2501:auto_generated.address_a[2] address_a[3] => altsyncram_2501:auto_generated.address_a[3] address_a[4] => altsyncram_2501:auto_generated.address_a[4] address_a[5] => altsyncram_2501:auto_generated.address_a[5] address_b[0] => ~NO_FANOUT~ addressstall_a => ~NO_FANOUT~ addressstall_b => ~NO_FANOUT~ clock0 => altsyncram_2501:auto_generated.clock0 clock1 => ~NO_FANOUT~ clocken0 => ~NO_FANOUT~ clocken1 => ~NO_FANOUT~ clocken2 => ~NO_FANOUT~ clocken3 => ~NO_FANOUT~ aclr0 => ~NO_FANOUT~ aclr1 => ~NO_FANOUT~ byteena_a[0] => ~NO_FANOUT~ byteena_b[0] => ~NO_FANOUT~ q_a[0] <= altsyncram_2501:auto_generated.q_a[0] q_a[1] <= altsyncram_2501:auto_generated.q_a[1] q_a[2] <= altsyncram_2501:auto_generated.q_a[2] q_a[3] <= altsyncram_2501:auto_generated.q_a[3] q_a[4] <= altsyncram_2501:auto_generated.q_a[4] q_a[5] <= altsyncram_2501:auto_generated.q_a[5] q_a[6] <= altsyncram_2501:auto_generated.q_a[6] q_a[7] <= altsyncram_2501:auto_generated.q_a[7] q_a[8] <= altsyncram_2501:auto_generated.q_a[8] q_a[9] <= altsyncram_2501:auto_generated.q_a[9] q_a[10] <= altsyncram_2501:auto_generated.q_a[10] q_a[11] <= altsyncram_2501:auto_generated.q_a[11] q_a[12] <= altsyncram_2501:auto_generated.q_a[12] q_a[13] <= altsyncram_2501:auto_generated.q_a[13] q_a[14] <= altsyncram_2501:auto_generated.q_a[14] q_a[15] <= altsyncram_2501:auto_generated.q_a[15] q_a[16] <= altsyncram_2501:auto_generated.q_a[16] q_a[17] <= altsyncram_2501:auto_generated.q_a[17] q_a[18] <= altsyncram_2501:auto_generated.q_a[18] q_a[19] <= altsyncram_2501:auto_generated.q_a[19] q_a[20] <= altsyncram_2501:auto_generated.q_a[20] q_a[21] <= altsyncram_2501:auto_generated.q_a[21] q_a[22] <= altsyncram_2501:auto_generated.q_a[22] q_a[23] <= altsyncram_2501:auto_generated.q_a[23] q_b[0] <= eccstatus[0] <= eccstatus[1] <= eccstatus[2] <= |rom2627|LPM_ROM:inst|altrom:srom|altsyncram:rom_block|altsyncram_2501:auto_generated address_a[0] => ram_block1a0.PORTAADDR address_a[0] => ram_block1a1.PORTAADDR address_a[0] => ram_block1a2.PORTAADDR address_a[0] => ram_block1a3.PORTAADDR address_a[0] => ram_block1a4.PORTAADDR address_a[0] => ram_block1a5.PORTAADDR address_a[0] => ram_block1a6.PORTAADDR address_a[0] => ram_block1a7.PORTAADDR address_a[0] => ram_block1a8.PORTAADDR address_a[0] => ram_block1a9.PORTAADDR address_a[0] => ram_block1a10.PORTAADDR address_a[0] => ram_block1a11.PORTAADDR address_a[0] => ram_block1a12.PORTAADDR address_a[0] => ram_block1a13.PORTAADDR address_a[0] => ram_block1a14.PORTAADDR address_a[0] => ram_block1a15.PORTAADDR address_a[0] => ram_block1a16.PORTAADDR address_a[0] => ram_block1a17.PORTAADDR address_a[0] => ram_block1a18.PORTAADDR address_a[0] => ram_block1a19.PORTAADDR address_a[0] => ram_block1a20.PORTAADDR address_a[0] => ram_block1a21.PORTAADDR address_a[0] => ram_block1a22.PORTAADDR address_a[0] => ram_block1a23.PORTAADDR address_a[1] => ram_block1a0.PORTAADDR1 address_a[1] => ram_block1a1.PORTAADDR1 address_a[1] => ram_block1a2.PORTAADDR1 address_a[1] => ram_block1a3.PORTAADDR1 address_a[1] => ram_block1a4.PORTAADDR1 address_a[1] => ram_block1a5.PORTAADDR1 address_a[1] => ram_block1a6.PORTAADDR1 address_a[1] => ram_block1a7.PORTAADDR1 address_a[1] => ram_block1a8.PORTAADDR1 address_a[1] => ram_block1a9.PORTAADDR1 address_a[1] => ram_block1a10.PORTAADDR1 address_a[1] => ram_block1a11.PORTAADDR1 address_a[1] => ram_block1a12.PORTAADDR1 address_a[1] => ram_block1a13.PORTAADDR1 address_a[1] => ram_block1a14.PORTAADDR1 address_a[1] => ram_block1a15.PORTAADDR1 address_a[1] => ram_block1a16.PORTAADDR1 address_a[1] => ram_block1a17.PORTAADDR1 address_a[1] => ram_block1a18.PORTAADDR1 address_a[1] => ram_block1a19.PORTAADDR1 address_a[1] => ram_block1a20.PORTAADDR1 address_a[1] => ram_block1a21.PORTAADDR1 address_a[1] => ram_block1a22.PORTAADDR1 address_a[1] => ram_block1a23.PORTAADDR1 address_a[2] => ram_block1a0.PORTAADDR2 address_a[2] => ram_block1a1.PORTAADDR2 address_a[2] => ram_block1a2.PORTAADDR2 address_a[2] => ram_block1a3.PORTAADDR2 address_a[2] => ram_block1a4.PORTAADDR2 address_a[2] => ram_block1a5.PORTAADDR2 address_a[2] => ram_block1a6.PORTAADDR2 address_a[2] => ram_block1a7.PORTAADDR2 address_a[2] => ram_block1a8.PORTAADDR2 address_a[2] => ram_block1a9.PORTAADDR2 address_a[2] => ram_block1a10.PORTAADDR2 address_a[2] => ram_block1a11.PORTAADDR2 address_a[2] => ram_block1a12.PORTAADDR2 address_a[2] => ram_block1a13.PORTAADDR2 address_a[2] => ram_block1a14.PORTAADDR2 address_a[2] => ram_block1a15.PORTAADDR2 address_a[2] => ram_block1a16.PORTAADDR2 address_a[2] => ram_block1a17.PORTAADDR2 address_a[2] => ram_block1a18.PORTAADDR2 address_a[2] => ram_block1a19.PORTAADDR2 address_a[2] => ram_block1a20.PORTAADDR2 address_a[2] => ram_block1a21.PORTAADDR2 address_a[2] => ram_block1a22.PORTAADDR2 address_a[2] => ram_block1a23.PORTAADDR2 address_a[3] => ram_block1a0.PORTAADDR3 address_a[3] => ram_block1a1.PORTAADDR3 address_a[3] => ram_block1a2.PORTAADDR3 address_a[3] => ram_block1a3.PORTAADDR3 address_a[3] => ram_block1a4.PORTAADDR3 address_a[3] => ram_block1a5.PORTAADDR3 address_a[3] => ram_block1a6.PORTAADDR3 address_a[3] => ram_block1a7.PORTAADDR3 address_a[3] => ram_block1a8.PORTAADDR3 address_a[3] => ram_block1a9.PORTAADDR3 address_a[3] => ram_block1a10.PORTAADDR3 address_a[3] => ram_block1a11.PORTAADDR3 address_a[3] => ram_block1a12.PORTAADDR3 address_a[3] => ram_block1a13.PORTAADDR3 address_a[3] => ram_block1a14.PORTAADDR3 address_a[3] => ram_block1a15.PORTAADDR3 address_a[3] => ram_block1a16.PORTAADDR3 address_a[3] => ram_block1a17.PORTAADDR3 address_a[3] => ram_block1a18.PORTAADDR3 address_a[3] => ram_block1a19.PORTAADDR3 address_a[3] => ram_block1a20.PORTAADDR3 address_a[3] => ram_block1a21.PORTAADDR3 address_a[3] => ram_block1a22.PORTAADDR3 address_a[3] => ram_block1a23.PORTAADDR3 address_a[4] => ram_block1a0.PORTAADDR4 address_a[4] => ram_block1a1.PORTAADDR4 address_a[4] => ram_block1a2.PORTAADDR4 address_a[4] => ram_block1a3.PORTAADDR4 address_a[4] => ram_block1a4.PORTAADDR4 address_a[4] => ram_block1a5.PORTAADDR4 address_a[4] => ram_block1a6.PORTAADDR4 address_a[4] => ram_block1a7.PORTAADDR4 address_a[4] => ram_block1a8.PORTAADDR4 address_a[4] => ram_block1a9.PORTAADDR4 address_a[4] => ram_block1a10.PORTAADDR4 address_a[4] => ram_block1a11.PORTAADDR4 address_a[4] => ram_block1a12.PORTAADDR4 address_a[4] => ram_block1a13.PORTAADDR4 address_a[4] => ram_block1a14.PORTAADDR4 address_a[4] => ram_block1a15.PORTAADDR4 address_a[4] => ram_block1a16.PORTAADDR4 address_a[4] => ram_block1a17.PORTAADDR4 address_a[4] => ram_block1a18.PORTAADDR4 address_a[4] => ram_block1a19.PORTAADDR4 address_a[4] => ram_block1a20.PORTAADDR4 address_a[4] => ram_block1a21.PORTAADDR4 address_a[4] => ram_block1a22.PORTAADDR4 address_a[4] => ram_block1a23.PORTAADDR4 address_a[5] => ram_block1a0.PORTAADDR5 address_a[5] => ram_block1a1.PORTAADDR5 address_a[5] => ram_block1a2.PORTAADDR5 address_a[5] => ram_block1a3.PORTAADDR5 address_a[5] => ram_block1a4.PORTAADDR5 address_a[5] => ram_block1a5.PORTAADDR5 address_a[5] => ram_block1a6.PORTAADDR5 address_a[5] => ram_block1a7.PORTAADDR5 address_a[5] => ram_block1a8.PORTAADDR5 address_a[5] => ram_block1a9.PORTAADDR5 address_a[5] => ram_block1a10.PORTAADDR5 address_a[5] => ram_block1a11.PORTAADDR5 address_a[5] => ram_block1a12.PORTAADDR5 address_a[5] => ram_block1a13.PORTAADDR5 address_a[5] => ram_block1a14.PORTAADDR5 address_a[5] => ram_block1a15.PORTAADDR5 address_a[5] => ram_block1a16.PORTAADDR5 address_a[5] => ram_block1a17.PORTAADDR5 address_a[5] => ram_block1a18.PORTAADDR5 address_a[5] => ram_block1a19.PORTAADDR5 address_a[5] => ram_block1a20.PORTAADDR5 address_a[5] => ram_block1a21.PORTAADDR5 address_a[5] => ram_block1a22.PORTAADDR5 address_a[5] => ram_block1a23.PORTAADDR5 clock0 => ram_block1a0.CLK0 clock0 => ram_block1a1.CLK0 clock0 => ram_block1a2.CLK0 clock0 => ram_block1a3.CLK0 clock0 => ram_block1a4.CLK0 clock0 => ram_block1a5.CLK0 clock0 => ram_block1a6.CLK0 clock0 => ram_block1a7.CLK0 clock0 => ram_block1a8.CLK0 clock0 => ram_block1a9.CLK0 clock0 => ram_block1a10.CLK0 clock0 => ram_block1a11.CLK0 clock0 => ram_block1a12.CLK0 clock0 => ram_block1a13.CLK0 clock0 => ram_block1a14.CLK0 clock0 => ram_block1a15.CLK0 clock0 => ram_block1a16.CLK0 clock0 => ram_block1a17.CLK0 clock0 => ram_block1a18.CLK0 clock0 => ram_block1a19.CLK0 clock0 => ram_block1a20.CLK0 clock0 => ram_block1a21.CLK0 clock0 => ram_block1a22.CLK0 clock0 => ram_block1a23.CLK0 q_a[0] <= ram_block1a0.PORTADATAOUT q_a[1] <= ram_block1a1.PORTADATAOUT q_a[2] <= ram_block1a2.PORTADATAOUT q_a[3] <= ram_block1a3.PORTADATAOUT q_a[4] <= ram_block1a4.PORTADATAOUT q_a[5] <= ram_block1a5.PORTADATAOUT q_a[6] <= ram_block1a6.PORTADATAOUT q_a[7] <= ram_block1a7.PORTADATAOUT q_a[8] <= ram_block1a8.PORTADATAOUT q_a[9] <= ram_block1a9.PORTADATAOUT q_a[10] <= ram_block1a10.PORTADATAOUT q_a[11] <= ram_block1a11.PORTADATAOUT q_a[12] <= ram_block1a12.PORTADATAOUT q_a[13] <= ram_block1a13.PORTADATAOUT q_a[14] <= ram_block1a14.PORTADATAOUT q_a[15] <= ram_block1a15.PORTADATAOUT q_a[16] <= ram_block1a16.PORTADATAOUT q_a[17] <= ram_block1a17.PORTADATAOUT q_a[18] <= ram_block1a18.PORTADATAOUT q_a[19] <= ram_block1a19.PORTADATAOUT q_a[20] <= ram_block1a20.PORTADATAOUT q_a[21] <= ram_block1a21.PORTADATAOUT q_a[22] <= ram_block1a22.PORTADATAOUT q_a[23] <= ram_block1a23.PORTADATAOUT