// Copyright (C) 2017  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "10/09/2023 23:39:00"
                                                                                
// Verilog Test Bench (with test vectors) for design :                          rom2627
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module rom2627_vlg_vec_tst();
// constants                                           
// general purpose registers
reg [5:0] address;
reg clock;
// wires                                               
wire [23:0] q;

// assign statements (if any)                          
rom2627 i1 (
// port map - connection between master ports and signals/registers   
	.address(address),
	.clock(clock),
	.q(q)
);
initial 
begin 
#64000 $finish;
end 

// clock
always
begin
	clock = 1'b0;
	clock = #500 1'b1;
	#500;
end 
// address[ 5 ]
always
begin
	address[5] = 1'b0;
	address[5] = #32000 1'b1;
	#32000;
end 
// address[ 4 ]
always
begin
	address[4] = 1'b0;
	address[4] = #16000 1'b1;
	#16000;
end 
// address[ 3 ]
always
begin
	address[3] = 1'b0;
	address[3] = #8000 1'b1;
	#8000;
end 
// address[ 2 ]
always
begin
	address[2] = 1'b0;
	address[2] = #4000 1'b1;
	#4000;
end 
// address[ 1 ]
always
begin
	address[1] = 1'b0;
	address[1] = #2000 1'b1;
	#2000;
end 
// address[ 0 ]
always
begin
	address[0] = 1'b0;
	address[0] = #1000 1'b1;
	#1000;
end 
endmodule