// Copyright (C) 2017  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition"

// DATE "10/09/2023 23:39:01"

// 
// Device: Altera EP4CE55F23C8 Package FBGA484
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module rom2627 (
	q,
	clock,
	address);
output 	[23:0] q;
input 	clock;
input 	[5:0] address;

// Design Ports Information
// q[23]	=>  Location: PIN_V6,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[22]	=>  Location: PIN_V8,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[21]	=>  Location: PIN_Y7,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[20]	=>  Location: PIN_AA5,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[19]	=>  Location: PIN_U8,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[18]	=>  Location: PIN_V7,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[17]	=>  Location: PIN_V3,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[16]	=>  Location: PIN_AA7,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[15]	=>  Location: PIN_Y8,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[14]	=>  Location: PIN_AA6,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[13]	=>  Location: PIN_AB6,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[12]	=>  Location: PIN_AB3,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[11]	=>  Location: PIN_AA3,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[10]	=>  Location: PIN_W6,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[9]	=>  Location: PIN_Y6,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[8]	=>  Location: PIN_W7,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[7]	=>  Location: PIN_AB4,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[6]	=>  Location: PIN_AB7,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[5]	=>  Location: PIN_U7,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[4]	=>  Location: PIN_U9,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[3]	=>  Location: PIN_AB5,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[2]	=>  Location: PIN_AA4,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[1]	=>  Location: PIN_T10,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[0]	=>  Location: PIN_Y4,	 I/O Standard: 2.5 V,	 Current Strength: Default
// clock	=>  Location: PIN_G1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// address[0]	=>  Location: PIN_G22,	 I/O Standard: 2.5 V,	 Current Strength: Default
// address[1]	=>  Location: PIN_G21,	 I/O Standard: 2.5 V,	 Current Strength: Default
// address[2]	=>  Location: PIN_V5,	 I/O Standard: 2.5 V,	 Current Strength: Default
// address[3]	=>  Location: PIN_W8,	 I/O Standard: 2.5 V,	 Current Strength: Default
// address[4]	=>  Location: PIN_Y3,	 I/O Standard: 2.5 V,	 Current Strength: Default
// address[5]	=>  Location: PIN_T11,	 I/O Standard: 2.5 V,	 Current Strength: Default


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \q[23]~output_o ;
wire \q[22]~output_o ;
wire \q[21]~output_o ;
wire \q[20]~output_o ;
wire \q[19]~output_o ;
wire \q[18]~output_o ;
wire \q[17]~output_o ;
wire \q[16]~output_o ;
wire \q[15]~output_o ;
wire \q[14]~output_o ;
wire \q[13]~output_o ;
wire \q[12]~output_o ;
wire \q[11]~output_o ;
wire \q[10]~output_o ;
wire \q[9]~output_o ;
wire \q[8]~output_o ;
wire \q[7]~output_o ;
wire \q[6]~output_o ;
wire \q[5]~output_o ;
wire \q[4]~output_o ;
wire \q[3]~output_o ;
wire \q[2]~output_o ;
wire \q[1]~output_o ;
wire \q[0]~output_o ;
wire \clock~input_o ;
wire \clock~inputclkctrl_outclk ;
wire \address[0]~input_o ;
wire \address[1]~input_o ;
wire \address[2]~input_o ;
wire \address[3]~input_o ;
wire \address[4]~input_o ;
wire \address[5]~input_o ;
wire [23:0] \inst|srom|rom_block|auto_generated|q_a ;

wire [35:0] \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus ;

assign \inst|srom|rom_block|auto_generated|q_a [0] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [0];
assign \inst|srom|rom_block|auto_generated|q_a [1] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [1];
assign \inst|srom|rom_block|auto_generated|q_a [2] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [2];
assign \inst|srom|rom_block|auto_generated|q_a [3] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [3];
assign \inst|srom|rom_block|auto_generated|q_a [4] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [4];
assign \inst|srom|rom_block|auto_generated|q_a [5] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [5];
assign \inst|srom|rom_block|auto_generated|q_a [6] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [6];
assign \inst|srom|rom_block|auto_generated|q_a [7] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [7];
assign \inst|srom|rom_block|auto_generated|q_a [8] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [8];
assign \inst|srom|rom_block|auto_generated|q_a [9] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [9];
assign \inst|srom|rom_block|auto_generated|q_a [10] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [10];
assign \inst|srom|rom_block|auto_generated|q_a [11] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [11];
assign \inst|srom|rom_block|auto_generated|q_a [12] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [12];
assign \inst|srom|rom_block|auto_generated|q_a [13] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [13];
assign \inst|srom|rom_block|auto_generated|q_a [14] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [14];
assign \inst|srom|rom_block|auto_generated|q_a [15] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [15];
assign \inst|srom|rom_block|auto_generated|q_a [16] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [16];
assign \inst|srom|rom_block|auto_generated|q_a [17] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [17];
assign \inst|srom|rom_block|auto_generated|q_a [18] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [18];
assign \inst|srom|rom_block|auto_generated|q_a [19] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [19];
assign \inst|srom|rom_block|auto_generated|q_a [20] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [20];
assign \inst|srom|rom_block|auto_generated|q_a [21] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [21];
assign \inst|srom|rom_block|auto_generated|q_a [22] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [22];
assign \inst|srom|rom_block|auto_generated|q_a [23] = \inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [23];

hard_block auto_generated_inst(
	.devpor(devpor),
	.devclrn(devclrn),
	.devoe(devoe));

// Location: IOOBUF_X1_Y0_N23
cycloneive_io_obuf \q[23]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [23]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[23]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[23]~output .bus_hold = "false";
defparam \q[23]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X14_Y0_N16
cycloneive_io_obuf \q[22]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [22]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[22]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[22]~output .bus_hold = "false";
defparam \q[22]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X11_Y0_N2
cycloneive_io_obuf \q[21]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [21]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[21]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[21]~output .bus_hold = "false";
defparam \q[21]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X9_Y0_N9
cycloneive_io_obuf \q[20]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [20]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[20]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[20]~output .bus_hold = "false";
defparam \q[20]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X1_Y0_N2
cycloneive_io_obuf \q[19]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [19]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[19]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[19]~output .bus_hold = "false";
defparam \q[19]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X5_Y0_N9
cycloneive_io_obuf \q[18]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [18]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[18]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[18]~output .bus_hold = "false";
defparam \q[18]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y5_N16
cycloneive_io_obuf \q[17]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [17]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[17]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[17]~output .bus_hold = "false";
defparam \q[17]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X19_Y0_N2
cycloneive_io_obuf \q[16]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [16]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[16]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[16]~output .bus_hold = "false";
defparam \q[16]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X21_Y0_N16
cycloneive_io_obuf \q[15]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [15]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[15]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[15]~output .bus_hold = "false";
defparam \q[15]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X9_Y0_N2
cycloneive_io_obuf \q[14]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [14]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[14]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[14]~output .bus_hold = "false";
defparam \q[14]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X11_Y0_N23
cycloneive_io_obuf \q[13]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [13]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[13]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[13]~output .bus_hold = "false";
defparam \q[13]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X5_Y0_N23
cycloneive_io_obuf \q[12]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [12]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[12]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[12]~output .bus_hold = "false";
defparam \q[12]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X3_Y0_N2
cycloneive_io_obuf \q[11]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [11]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[11]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[11]~output .bus_hold = "false";
defparam \q[11]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X5_Y0_N16
cycloneive_io_obuf \q[10]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [10]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[10]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[10]~output .bus_hold = "false";
defparam \q[10]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X3_Y0_N9
cycloneive_io_obuf \q[9]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [9]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[9]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[9]~output .bus_hold = "false";
defparam \q[9]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X11_Y0_N9
cycloneive_io_obuf \q[8]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [8]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[8]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[8]~output .bus_hold = "false";
defparam \q[8]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X9_Y0_N23
cycloneive_io_obuf \q[7]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [7]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[7]~output .bus_hold = "false";
defparam \q[7]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X21_Y0_N23
cycloneive_io_obuf \q[6]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [6]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[6]~output .bus_hold = "false";
defparam \q[6]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X1_Y0_N9
cycloneive_io_obuf \q[5]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [5]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[5]~output .bus_hold = "false";
defparam \q[5]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X14_Y0_N23
cycloneive_io_obuf \q[4]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [4]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[4]~output .bus_hold = "false";
defparam \q[4]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X11_Y0_N16
cycloneive_io_obuf \q[3]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [3]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[3]~output .bus_hold = "false";
defparam \q[3]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X5_Y0_N2
cycloneive_io_obuf \q[2]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [2]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[2]~output .bus_hold = "false";
defparam \q[2]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X23_Y0_N16
cycloneive_io_obuf \q[1]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [1]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[1]~output .bus_hold = "false";
defparam \q[1]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X3_Y0_N23
cycloneive_io_obuf \q[0]~output (
	.i(\inst|srom|rom_block|auto_generated|q_a [0]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[0]~output .bus_hold = "false";
defparam \q[0]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOIBUF_X0_Y26_N8
cycloneive_io_ibuf \clock~input (
	.i(clock),
	.ibar(gnd),
	.o(\clock~input_o ));
// synopsys translate_off
defparam \clock~input .bus_hold = "false";
defparam \clock~input .simulate_z_as = "z";
// synopsys translate_on

// Location: CLKCTRL_G2
cycloneive_clkctrl \clock~inputclkctrl (
	.ena(vcc),
	.inclk({vcc,vcc,vcc,\clock~input_o }),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\clock~inputclkctrl_outclk ));
// synopsys translate_off
defparam \clock~inputclkctrl .clock_type = "global clock";
defparam \clock~inputclkctrl .ena_register_mode = "none";
// synopsys translate_on

// Location: IOIBUF_X77_Y27_N8
cycloneive_io_ibuf \address[0]~input (
	.i(address[0]),
	.ibar(gnd),
	.o(\address[0]~input_o ));
// synopsys translate_off
defparam \address[0]~input .bus_hold = "false";
defparam \address[0]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X77_Y27_N1
cycloneive_io_ibuf \address[1]~input (
	.i(address[1]),
	.ibar(gnd),
	.o(\address[1]~input_o ));
// synopsys translate_off
defparam \address[1]~input .bus_hold = "false";
defparam \address[1]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X1_Y0_N15
cycloneive_io_ibuf \address[2]~input (
	.i(address[2]),
	.ibar(gnd),
	.o(\address[2]~input_o ));
// synopsys translate_off
defparam \address[2]~input .bus_hold = "false";
defparam \address[2]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X14_Y0_N8
cycloneive_io_ibuf \address[3]~input (
	.i(address[3]),
	.ibar(gnd),
	.o(\address[3]~input_o ));
// synopsys translate_off
defparam \address[3]~input .bus_hold = "false";
defparam \address[3]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X3_Y0_N15
cycloneive_io_ibuf \address[4]~input (
	.i(address[4]),
	.ibar(gnd),
	.o(\address[4]~input_o ));
// synopsys translate_off
defparam \address[4]~input .bus_hold = "false";
defparam \address[4]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X23_Y0_N8
cycloneive_io_ibuf \address[5]~input (
	.i(address[5]),
	.ibar(gnd),
	.o(\address[5]~input_o ));
// synopsys translate_off
defparam \address[5]~input .bus_hold = "false";
defparam \address[5]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: M9K_X13_Y1_N0
cycloneive_ram_block \inst|srom|rom_block|auto_generated|ram_block1a0 (
	.portawe(vcc),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\clock~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(vcc),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain(36'b000000000000000000000000000000000000),
	.portaaddr({\address[5]~input_o ,\address[4]~input_o ,\address[3]~input_o ,\address[2]~input_o ,\address[1]~input_o ,\address[0]~input_o }),
	.portabyteenamasks(1'b1),
	.portbdatain(36'b000000000000000000000000000000000000),
	.portbaddr(6'b000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .init_file = "ucode.hex";
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .init_file_layout = "port_a";
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .logical_ram_name = "lpm_rom:inst|altrom:srom|altsyncram:rom_block|altsyncram_2501:auto_generated|ALTSYNCRAM";
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .operation_mode = "rom";
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .port_a_address_clear = "none";
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .port_a_address_width = 6;
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .port_a_data_width = 36;
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .port_a_first_address = 0;
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .port_a_last_address = 63;
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 64;
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .port_a_logical_ram_width = 24;
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none";
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .port_b_address_width = 6;
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .port_b_data_width = 36;
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .ram_block_type = "M9K";
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .mem_init1 = 256'h000047ACC0000468980000456640000444300000431FC000041FC8000040D940;
defparam \inst|srom|rom_block|auto_generated|ram_block1a0 .mem_init0 = 2048'h0003FB6000003E92C00003D6F800003C4C400003B29000003A05C000038E28000037BF40000369C000003578C0000345580000333240000320F0000030EBC00002FC8800002EA5400002D82000002C5EC00002B3B800002A184000028F50000027D1C000026AE80000258B400002468000002344C000022218000020FE400001FDB000001EB7C00001D94800001C71400001B4E000001A2AC000019078000017E44000016C100000159DC0000147A800001357400001234000001110C00000FED800000ECA400000DA7000000C83C00000B60800000A3D40000091A0000007F6C000006D38000005B040000048D000000369C000002468000001234000000000;
// synopsys translate_on

assign q[23] = \q[23]~output_o ;

assign q[22] = \q[22]~output_o ;

assign q[21] = \q[21]~output_o ;

assign q[20] = \q[20]~output_o ;

assign q[19] = \q[19]~output_o ;

assign q[18] = \q[18]~output_o ;

assign q[17] = \q[17]~output_o ;

assign q[16] = \q[16]~output_o ;

assign q[15] = \q[15]~output_o ;

assign q[14] = \q[14]~output_o ;

assign q[13] = \q[13]~output_o ;

assign q[12] = \q[12]~output_o ;

assign q[11] = \q[11]~output_o ;

assign q[10] = \q[10]~output_o ;

assign q[9] = \q[9]~output_o ;

assign q[8] = \q[8]~output_o ;

assign q[7] = \q[7]~output_o ;

assign q[6] = \q[6]~output_o ;

assign q[5] = \q[5]~output_o ;

assign q[4] = \q[4]~output_o ;

assign q[3] = \q[3]~output_o ;

assign q[2] = \q[2]~output_o ;

assign q[1] = \q[1]~output_o ;

assign q[0] = \q[0]~output_o ;

endmodule

module hard_block (

	devpor,
	devclrn,
	devoe);

// Design Ports Information
// ~ALTERA_ASDO_DATA1~	=>  Location: PIN_D1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_FLASH_nCE_nCSO~	=>  Location: PIN_E2,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_DCLK~	=>  Location: PIN_K2,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_DATA0~	=>  Location: PIN_K1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_nCEO~	=>  Location: PIN_K22,	 I/O Standard: 2.5 V,	 Current Strength: 8mA

input 	devpor;
input 	devclrn;
input 	devoe;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

wire \~ALTERA_ASDO_DATA1~~padout ;
wire \~ALTERA_FLASH_nCE_nCSO~~padout ;
wire \~ALTERA_DATA0~~padout ;
wire \~ALTERA_ASDO_DATA1~~ibuf_o ;
wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ;
wire \~ALTERA_DATA0~~ibuf_o ;


endmodule