{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1698132240855 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1698132240863 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 24 15:24:00 2023 " "Processing started: Tue Oct 24 15:24:00 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1698132240863 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1698132240863 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off timing2627 -c timing2627 " "Command: quartus_map --read_settings_files=on --write_settings_files=off timing2627 -c timing2627" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1698132240863 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1698132241197 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1698132241198 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dff2627.bdf 1 1 " "Found 1 design units, including 1 entities, in source file dff2627.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 dff2627 " "Found entity 1: dff2627" { } { { "dff2627.bdf" "" { Schematic "D:/Projects/quartus/timing/dff2627.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1698132249592 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1698132249592 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "timing2627.bdf 1 1 " "Found 1 design units, including 1 entities, in source file timing2627.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 timing2627 " "Found entity 1: timing2627" { } { { "timing2627.bdf" "" { Schematic "D:/Projects/quartus/timing/timing2627.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1698132249593 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1698132249593 ""} { "Info" "ISGN_START_ELABORATION_TOP" "timing2627 " "Elaborating entity \"timing2627\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1698132249617 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "21mux 21mux:inst9 " "Elaborating entity \"21mux\" for hierarchy \"21mux:inst9\"" { } { { "timing2627.bdf" "inst9" { Schematic "D:/Projects/quartus/timing/timing2627.bdf" { { 296 288 408 376 "inst9" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698132249639 ""} { "Info" "ISGN_ELABORATION_HEADER" "21mux:inst9 " "Elaborated megafunction instantiation \"21mux:inst9\"" { } { { "timing2627.bdf" "" { Schematic "D:/Projects/quartus/timing/timing2627.bdf" { { 296 288 408 376 "inst9" "" } } } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698132249639 ""} { "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1698132250000 ""} { "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1698132250363 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698132250363 ""} { "Info" "ICUT_CUT_TM_SUMMARY" "17 " "Implemented 17 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1698132250383 ""} { "Info" "ICUT_CUT_TM_OPINS" "6 " "Implemented 6 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1698132250383 ""} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Implemented 8 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1698132250383 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1698132250383 ""} { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4835 " "Peak virtual memory: 4835 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1698132250392 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 24 15:24:10 2023 " "Processing ended: Tue Oct 24 15:24:10 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1698132250392 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1698132250392 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:19 " "Total CPU time (on all processors): 00:00:19" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1698132250392 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1698132250392 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1698132251543 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1698132251551 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 24 15:24:11 2023 " "Processing started: Tue Oct 24 15:24:11 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1698132251551 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1698132251551 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off timing2627 -c timing2627 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off timing2627 -c timing2627" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1698132251551 ""} { "Info" "0" "" "qfit2_default_script.tcl version: #3" { } { } 0 0 "qfit2_default_script.tcl version: #3" 0 0 "Fitter" 0 0 1698132251659 ""} { "Info" "0" "" "Project = timing2627" { } { } 0 0 "Project = timing2627" 0 0 "Fitter" 0 0 1698132251659 ""} { "Info" "0" "" "Revision = timing2627" { } { } 0 0 "Revision = timing2627" 0 0 "Fitter" 0 0 1698132251659 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1698132251707 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1698132251707 ""} { "Info" "IMPP_MPP_USER_DEVICE" "timing2627 EP4CE55F23C8 " "Selected device EP4CE55F23C8 for design \"timing2627\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1698132251711 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1698132251753 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1698132251753 ""} { "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1698132251910 ""} { "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1698132251914 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F23C8 " "Device EP4CE15F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1698132252024 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F23C8 " "Device EP4CE40F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1698132252024 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F23C8 " "Device EP4CE30F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1698132252024 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F23C8 " "Device EP4CE75F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1698132252024 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F23C8 " "Device EP4CE115F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1698132252024 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1698132252024 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" { } { { "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/timing/" { { 0 { 0 ""} 0 36 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1698132252026 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/timing/" { { 0 { 0 ""} 0 38 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1698132252026 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" { } { { "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/timing/" { { 0 { 0 ""} 0 40 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1698132252026 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" { } { { "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/timing/" { { 0 { 0 ""} 0 42 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1698132252026 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" { } { { "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/timing/" { { 0 { 0 ""} 0 44 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1698132252026 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1698132252026 ""} { "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1698132252027 ""} { "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "2 9 " "No exact pin location assignment(s) for 2 pins of 9 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1698132252402 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "timing2627.sdc " "Synopsys Design Constraints File file not found: 'timing2627.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1698132252521 ""} { "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1698132252521 ""} { "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1698132252522 ""} { "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1698132252522 ""} { "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1698132252523 ""} { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ins10t " "Automatically promoted node ins10t " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1698132252525 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "debug_clk~output " "Destination node debug_clk~output" { } { { "timing2627.bdf" "" { Schematic "D:/Projects/quartus/timing/timing2627.bdf" { { 312 1112 1288 328 "debug_clk" "" } } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/timing/" { { 0 { 0 ""} 0 27 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1698132252525 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1698132252525 ""} } { { "timing2627.bdf" "" { Schematic "D:/Projects/quartus/timing/timing2627.bdf" { { 296 520 584 344 "ins10t" "" } } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/timing/" { { 0 { 0 ""} 0 15 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1698132252525 ""} { "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1698132252667 ""} { "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1698132252667 ""} { "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1698132252667 ""} { "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1698132252668 ""} { "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1698132252668 ""} { "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1698132252668 ""} { "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1698132252668 ""} { "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1698132252668 ""} { "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1698132252674 ""} { "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1698132252674 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1698132252674 ""} { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "2 unused 2.5V 0 2 0 " "Number of I/O pins in group: 2 (unused VREF, 2.5V VCCIO, 0 input, 2 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1698132252675 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1698132252675 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1698132252675 ""} { "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 29 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 29 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1698132252675 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 2.5V 5 36 " "I/O bank number 2 does not use VREF pins and has 2.5V VCCIO pins. 5 total pin(s) used -- 36 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1698132252675 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 2.5V 2 40 " "I/O bank number 3 does not use VREF pins and has 2.5V VCCIO pins. 2 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1698132252675 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 43 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1698132252675 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 41 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 41 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1698132252675 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 38 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 38 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1698132252675 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 43 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1698132252675 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1698132252675 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1698132252675 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1698132252675 ""} { "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1698132252682 ""} { "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1698132252684 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1698132253765 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1698132253805 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1698132253821 ""} { "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1698132256248 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1698132256248 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1698132256382 ""} { "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y10 X10_Y20 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X10_Y20" { } { { "loc" "" { Generic "D:/Projects/quartus/timing/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X10_Y20"} { { 12 { 0 ""} 0 10 11 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1698132257425 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1698132257425 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1698132257682 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1698132257682 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1698132257684 ""} { "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1698132257768 ""} { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1698132257773 ""} { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1698132257895 ""} { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1698132257895 ""} { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1698132258016 ""} { "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1698132258276 ""} { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/Projects/quartus/timing/output_files/timing2627.fit.smsg " "Generated suppressed messages file D:/Projects/quartus/timing/output_files/timing2627.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1698132258515 ""} { "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "6553 " "Peak virtual memory: 6553 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1698132258735 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 24 15:24:18 2023 " "Processing ended: Tue Oct 24 15:24:18 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1698132258735 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1698132258735 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1698132258735 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1698132258735 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1698132259720 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1698132259729 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 24 15:24:19 2023 " "Processing started: Tue Oct 24 15:24:19 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1698132259729 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1698132259729 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off timing2627 -c timing2627 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off timing2627 -c timing2627" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1698132259729 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1698132259961 ""} { "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1698132260916 ""} { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1698132260950 ""} { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4672 " "Peak virtual memory: 4672 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1698132261083 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 24 15:24:21 2023 " "Processing ended: Tue Oct 24 15:24:21 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1698132261083 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1698132261083 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1698132261083 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1698132261083 ""} { "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1698132261672 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1698132262177 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1698132262186 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 24 15:24:21 2023 " "Processing started: Tue Oct 24 15:24:21 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1698132262186 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262186 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta timing2627 -c timing2627 " "Command: quartus_sta timing2627 -c timing2627" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262186 ""} { "Info" "0" "" "qsta_default_script.tcl version: #3" { } { } 0 0 "qsta_default_script.tcl version: #3" 0 0 "TimeQuest Timing Analyzer" 0 0 1698132262296 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262434 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262434 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262480 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262480 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "timing2627.sdc " "Synopsys Design Constraints File file not found: 'timing2627.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262688 ""} { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262688 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLK1 CLK1 " "create_clock -period 1.000 -name CLK1 CLK1" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1698132262688 ""} } { } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262688 ""} { "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262688 ""} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262689 ""} { "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1698132262689 ""} { "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1698132262694 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1698132262700 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262700 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -1.015 " "Worst-case setup slack is -1.015" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132262701 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132262701 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.015 -2.419 CLK1 " " -1.015 -2.419 CLK1 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132262701 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262701 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.672 " "Worst-case hold slack is 0.672" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132262703 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132262703 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.672 0.000 CLK1 " " 0.672 0.000 CLK1 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132262703 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262703 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262704 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262706 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132262707 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132262707 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -10.435 CLK1 " " -3.000 -10.435 CLK1 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132262707 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262707 ""} { "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1698132262720 ""} { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262736 ""} { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262895 ""} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262926 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1698132262929 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262929 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -0.867 " "Worst-case setup slack is -0.867" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132262931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132262931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.867 -1.860 CLK1 " " -0.867 -1.860 CLK1 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132262931 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262931 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.626 " "Worst-case hold slack is 0.626" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132262933 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132262933 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.626 0.000 CLK1 " " 0.626 0.000 CLK1 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132262933 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262933 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262935 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262937 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132262938 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132262938 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -10.741 CLK1 " " -3.000 -10.741 CLK1 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132262938 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132262938 ""} { "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1698132262951 ""} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132263028 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup 0.175 " "Worst-case setup slack is 0.175" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132263031 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132263031 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.175 0.000 CLK1 " " 0.175 0.000 CLK1 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132263031 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132263031 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.269 " "Worst-case hold slack is 0.269" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132263033 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132263033 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.269 0.000 CLK1 " " 0.269 0.000 CLK1 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132263033 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132263033 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132263035 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132263036 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1698132263037 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132263037 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132263038 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132263038 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -8.854 CLK1 " " -3.000 -8.854 CLK1 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1698132263038 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132263038 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132263308 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132263308 ""} { "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4914 " "Peak virtual memory: 4914 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1698132263334 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 24 15:24:23 2023 " "Processing ended: Tue Oct 24 15:24:23 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1698132263334 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1698132263334 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1698132263334 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132263334 ""} { "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 12 s " "Quartus Prime Full Compilation was successful. 0 errors, 12 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1698132263965 ""}