// Copyright (C) 2017  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "10/24/2023 15:00:21"
                                                                                
// Verilog Test Bench (with test vectors) for design :                          dff2627
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module dff2627_vlg_vec_tst();
// constants                                           
// general purpose registers
reg clk;
reg clrn;
reg d;
// wires                                               
wire q;

// assign statements (if any)                          
dff2627 i1 (
// port map - connection between master ports and signals/registers   
	.clk(clk),
	.clrn(clrn),
	.d(d),
	.q(q)
);
initial 
begin 
#100000 $finish;
end 

// clk
always
begin
	clk = 1'b0;
	clk = #5000 1'b1;
	#5000;
end 

// d
initial
begin
	d = 1'b0;
	d = #10000 1'b1;
	d = #10000 1'b0;
	d = #10000 1'b1;
	d = #10000 1'b0;
end 

// clrn
initial
begin
	clrn = 1'b1;
end 
endmodule