$comment
	File created using the following command:
		vcd file timing2627.msim.vcd -direction
$end
$date
	Tue Oct 24 15:45:22 2023
$end
$version
	ModelSim Version 10.5b
$end
$timescale
	1ps
$end

$scope module timing2627_vlg_vec_tst $end
$var reg 1 ! CLK1 $end
$var reg 1 " RST1 $end
$var reg 1 # s0 $end
$var wire 1 $ debug_clk $end
$var wire 1 % debug_D $end
$var wire 1 & T1 $end
$var wire 1 ' T2 $end
$var wire 1 ( T3 $end
$var wire 1 ) T4 $end

$scope module i1 $end
$var wire 1 * gnd $end
$var wire 1 + vcc $end
$var wire 1 , unknown $end
$var tri1 1 - devclrn $end
$var tri1 1 . devpor $end
$var tri1 1 / devoe $end
$var wire 1 0 T1~output_o $end
$var wire 1 1 T4~output_o $end
$var wire 1 2 T3~output_o $end
$var wire 1 3 T2~output_o $end
$var wire 1 4 debug_clk~output_o $end
$var wire 1 5 debug_D~output_o $end
$var wire 1 6 inst5~feeder_combout $end
$var wire 1 7 RST1~input_o $end
$var wire 1 8 inst5~q $end
$var wire 1 9 inst6~feeder_combout $end
$var wire 1 : inst6~q $end
$var wire 1 ; inst7~feeder_combout $end
$var wire 1 < inst7~q $end
$var wire 1 = inst8~q $end
$var wire 1 > s0~input_o $end
$var wire 1 ? CLK1~input_o $end
$var wire 1 @ ins10t~combout $end
$var wire 1 A ins10t~clkctrl_outclk $end
$var wire 1 B inst3|5~0_combout $end
$var wire 1 C inst3|5~1_combout $end
$var wire 1 D inst4~feeder_combout $end
$var wire 1 E inst4~q $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
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