vendor_name = ModelSim
source_file = 1, D:/Projects/quartus/timing/Waveform.vwf
source_file = 1, D:/Projects/quartus/timing/dff2627.bdf
source_file = 1, D:/Projects/quartus/timing/dfftest.vwf
source_file = 1, D:/Projects/quartus/timing/timing2627.bdf
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/others/maxplus2/21mux.bdf
design_name = timing2627
instance = comp, \T1~output , T1~output, timing2627, 1
instance = comp, \T4~output , T4~output, timing2627, 1
instance = comp, \T3~output , T3~output, timing2627, 1
instance = comp, \T2~output , T2~output, timing2627, 1
instance = comp, \debug_clk~output , debug_clk~output, timing2627, 1
instance = comp, \debug_D~output , debug_D~output, timing2627, 1
instance = comp, \inst5~feeder , inst5~feeder, timing2627, 1
instance = comp, \RST1~input , RST1~input, timing2627, 1
instance = comp, \inst6~feeder , inst6~feeder, timing2627, 1
instance = comp, \inst7~feeder , inst7~feeder, timing2627, 1
instance = comp, \s0~input , s0~input, timing2627, 1
instance = comp, \CLK1~input , CLK1~input, timing2627, 1
instance = comp, \ins10t~clkctrl , ins10t~clkctrl, timing2627, 1
instance = comp, \inst3|5~0 , inst3|5~0, timing2627, 1
instance = comp, \inst3|5~1 , inst3|5~1, timing2627, 1
instance = comp, \inst4~feeder , inst4~feeder, timing2627, 1
design_name = hard_block
instance = comp, \~ALTERA_ASDO_DATA1~~ibuf , ~ALTERA_ASDO_DATA1~~ibuf, hard_block, 1
instance = comp, \~ALTERA_FLASH_nCE_nCSO~~ibuf , ~ALTERA_FLASH_nCE_nCSO~~ibuf, hard_block, 1
instance = comp, \~ALTERA_DATA0~~ibuf , ~ALTERA_DATA0~~ibuf, hard_block, 1