# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.0 Build 156 04/24/2013 SJ Full Version
# Date created = 15:17:55  November 22, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		eda11_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C16Q240C8
set_global_assignment -name TOP_LEVEL_ENTITY eda1
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:17:55  NOVEMBER 22, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION 13.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name VERILOG_FILE eda11.v
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_160 -to a[3]
set_location_assignment PIN_161 -to a[2]
set_location_assignment PIN_166 -to a[1]
set_location_assignment PIN_164 -to a[0]
set_location_assignment PIN_174 -to b[3]
set_location_assignment PIN_175 -to b[2]
set_location_assignment PIN_177 -to b[1]
set_location_assignment PIN_176 -to b[0]
set_location_assignment PIN_152 -to clk
set_location_assignment PIN_128 -to operator[1]
set_location_assignment PIN_131 -to operator[0]
set_location_assignment PIN_63 -to wordout[6]
set_location_assignment PIN_52 -to wordout[5]
set_location_assignment PIN_70 -to wordout[4]
set_location_assignment PIN_55 -to wordout[3]
set_location_assignment PIN_65 -to wordout[2]
set_location_assignment PIN_68 -to wordout[1]
set_location_assignment PIN_56 -to wordout[0]
set_location_assignment PIN_51 -to segout[3]
set_location_assignment PIN_57 -to segout[2]
set_location_assignment PIN_64 -to segout[1]
set_location_assignment PIN_69 -to segout[0]
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_location_assignment PIN_49 -to segout[5]
set_location_assignment PIN_50 -to segout[4]
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "C:/Users/Xsu1023/Desktop/eda1/Waveform.vwf"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top