{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1638646309528 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1638646309528 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 05 03:31:49 2021 " "Processing started: Sun Dec 05 03:31:49 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1638646309528 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1638646309528 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off eda1 -c eda1 " "Command: quartus_map --read_settings_files=on --write_settings_files=off eda1 -c eda1" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1638646309529 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "6 6 12 " "Parallel Compilation has detected 12 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 6 of the 6 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1638646309894 ""}
{ "Warning" "WSGN_FILE_IS_MISSING" "eda11.v " "Can't analyze file -- file eda11.v is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1638646309948 ""}
{ "Warning" "WSGN_SEARCH_FILE" "eda1.v 11 11 " "Using design file eda1.v, which is not specified as a design file for the current project, but contains definitions for 11 design units and 11 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 add32 " "Found entity 1: add32" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 2 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1638646309988 ""} { "Info" "ISGN_ENTITY_NAME" "2 div32 " "Found entity 2: div32" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1638646309988 ""} { "Info" "ISGN_ENTITY_NAME" "3 sub32 " "Found entity 3: sub32" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1638646309988 ""} { "Info" "ISGN_ENTITY_NAME" "4 mul16 " "Found entity 4: mul16" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 36 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1638646309988 ""} { "Info" "ISGN_ENTITY_NAME" "5 selector " "Found entity 5: selector" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1638646309988 ""} { "Info" "ISGN_ENTITY_NAME" "6 clock " "Found entity 6: clock" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 61 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1638646309988 ""} { "Info" "ISGN_ENTITY_NAME" "7 counter " "Found entity 7: counter" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 73 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1638646309988 ""} { "Info" "ISGN_ENTITY_NAME" "8 segtranslator " "Found entity 8: segtranslator" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 83 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1638646309988 ""} { "Info" "ISGN_ENTITY_NAME" "9 gettempnumber " "Found entity 9: gettempnumber" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 101 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1638646309988 ""} { "Info" "ISGN_ENTITY_NAME" "10 numbertranslator " "Found entity 10: numbertranslator" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 123 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1638646309988 ""} { "Info" "ISGN_ENTITY_NAME" "11 eda1 " "Found entity 11: eda1" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 151 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1638646309988 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1638646309988 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "eda1 " "Elaborating entity \"eda1\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1638646309992 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add32 add32:my_add32 " "Elaborating entity \"add32\" for hierarchy \"add32:my_add32\"" {  } { { "eda1.v" "my_add32" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 166 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1638646310008 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sub32 sub32:my_sub32 " "Elaborating entity \"sub32\" for hierarchy \"sub32:my_sub32\"" {  } { { "eda1.v" "my_sub32" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 167 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1638646310015 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mul16 mul16:my_mul16 " "Elaborating entity \"mul16\" for hierarchy \"mul16:my_mul16\"" {  } { { "eda1.v" "my_mul16" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 168 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1638646310023 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div32 div32:my_div32 " "Elaborating entity \"div32\" for hierarchy \"div32:my_div32\"" {  } { { "eda1.v" "my_div32" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 169 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1638646310030 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "selector selector:my_selector " "Elaborating entity \"selector\" for hierarchy \"selector:my_selector\"" {  } { { "eda1.v" "my_selector" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 171 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1638646310037 ""}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "in0 eda1.v(50) " "Verilog HDL Always Construct warning at eda1.v(50): variable \"in0\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 50 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "Quartus II" 0 -1 1638646310037 "|eda1|selector:my_selector"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock clock:my_clock " "Elaborating entity \"clock\" for hierarchy \"clock:my_clock\"" {  } { { "eda1.v" "my_clock" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 172 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1638646310045 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 31 eda1.v(67) " "Verilog HDL assignment warning at eda1.v(67): truncated value with size 32 to match size of target (31)" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 67 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1638646310046 "|eda1|clock:my_clock"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:my_counter " "Elaborating entity \"counter\" for hierarchy \"counter:my_counter\"" {  } { { "eda1.v" "my_counter" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 173 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1638646310053 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 eda1.v(78) " "Verilog HDL assignment warning at eda1.v(78): truncated value with size 32 to match size of target (3)" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 78 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1638646310053 "|eda1|counter:my_counter"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segtranslator segtranslator:my_segtranslator " "Elaborating entity \"segtranslator\" for hierarchy \"segtranslator:my_segtranslator\"" {  } { { "eda1.v" "my_segtranslator" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 174 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1638646310059 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "gettempnumber gettempnumber:my_gettempnumber " "Elaborating entity \"gettempnumber\" for hierarchy \"gettempnumber:my_gettempnumber\"" {  } { { "eda1.v" "my_gettempnumber" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 176 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1638646310065 ""}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "a eda1.v(110) " "Verilog HDL Always Construct warning at eda1.v(110): variable \"a\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 110 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "Quartus II" 0 -1 1638646310065 "|eda1|gettempnumber:my_gettempnumber"}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "b eda1.v(111) " "Verilog HDL Always Construct warning at eda1.v(111): variable \"b\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 111 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "Quartus II" 0 -1 1638646310065 "|eda1|gettempnumber:my_gettempnumber"}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "sign eda1.v(112) " "Verilog HDL Always Construct warning at eda1.v(112): variable \"sign\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 112 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "Quartus II" 0 -1 1638646310066 "|eda1|gettempnumber:my_gettempnumber"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 eda1.v(112) " "Verilog HDL assignment warning at eda1.v(112): truncated value with size 32 to match size of target (5)" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 112 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1638646310066 "|eda1|gettempnumber:my_gettempnumber"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 eda1.v(113) " "Verilog HDL assignment warning at eda1.v(113): truncated value with size 32 to match size of target (5)" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 113 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1638646310066 "|eda1|gettempnumber:my_gettempnumber"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 eda1.v(114) " "Verilog HDL assignment warning at eda1.v(114): truncated value with size 32 to match size of target (5)" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 114 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1638646310066 "|eda1|gettempnumber:my_gettempnumber"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 eda1.v(115) " "Verilog HDL assignment warning at eda1.v(115): truncated value with size 32 to match size of target (5)" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 115 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1638646310066 "|eda1|gettempnumber:my_gettempnumber"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 eda1.v(116) " "Verilog HDL assignment warning at eda1.v(116): truncated value with size 32 to match size of target (5)" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 116 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1638646310066 "|eda1|gettempnumber:my_gettempnumber"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "numbertranslator numbertranslator:my_numbertranslator " "Elaborating entity \"numbertranslator\" for hierarchy \"numbertranslator:my_numbertranslator\"" {  } { { "eda1.v" "my_numbertranslator" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 177 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1638646310073 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "2 " "Inferred 2 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "div32:my_div32\|Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"div32:my_div32\|Div0\"" {  } { { "eda1.v" "Div0" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 12 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1638646310349 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "gettempnumber:my_gettempnumber\|Mod2 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"gettempnumber:my_gettempnumber\|Mod2\"" {  } { { "eda1.v" "Mod2" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 115 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1638646310349 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1638646310349 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "div32:my_div32\|lpm_divide:Div0 " "Elaborated megafunction instantiation \"div32:my_div32\|lpm_divide:Div0\"" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 12 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1638646310407 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "div32:my_div32\|lpm_divide:Div0 " "Instantiated megafunction \"div32:my_div32\|lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Parameter \"LPM_WIDTHN\" = \"32\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1638646310407 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 32 " "Parameter \"LPM_WIDTHD\" = \"32\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1638646310407 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1638646310407 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1638646310407 ""}  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 12 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1638646310407 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_8jm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_8jm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_8jm " "Found entity 1: lpm_divide_8jm" {  } { { "db/lpm_divide_8jm.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda13/db/lpm_divide_8jm.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1638646310479 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1638646310479 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_9nh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_9nh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_9nh " "Found entity 1: sign_div_unsign_9nh" {  } { { "db/sign_div_unsign_9nh.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda13/db/sign_div_unsign_9nh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1638646310504 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1638646310504 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_t8f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_t8f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_t8f " "Found entity 1: alt_u_div_t8f" {  } { { "db/alt_u_div_t8f.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda13/db/alt_u_div_t8f.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1638646310610 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1638646310610 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_unc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_unc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_unc " "Found entity 1: add_sub_unc" {  } { { "db/add_sub_unc.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda13/db/add_sub_unc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1638646311631 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1638646311631 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_vnc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_vnc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_vnc " "Found entity 1: add_sub_vnc" {  } { { "db/add_sub_vnc.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda13/db/add_sub_vnc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1638646311697 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1638646311697 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "gettempnumber:my_gettempnumber\|lpm_divide:Mod2 " "Elaborated megafunction instantiation \"gettempnumber:my_gettempnumber\|lpm_divide:Mod2\"" {  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 115 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1638646311715 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "gettempnumber:my_gettempnumber\|lpm_divide:Mod2 " "Instantiated megafunction \"gettempnumber:my_gettempnumber\|lpm_divide:Mod2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 8 " "Parameter \"LPM_WIDTHN\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1638646311715 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1638646311715 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1638646311715 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1638646311715 ""}  } { { "eda1.v" "" { Text "C:/Users/Xsu1023/Desktop/eda13/eda1.v" 115 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1638646311715 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_d8m.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_d8m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_d8m " "Found entity 1: lpm_divide_d8m" {  } { { "db/lpm_divide_d8m.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda13/db/lpm_divide_d8m.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1638646311778 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1638646311778 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_bkh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_bkh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_bkh " "Found entity 1: sign_div_unsign_bkh" {  } { { "db/sign_div_unsign_bkh.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda13/db/sign_div_unsign_bkh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1638646311797 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1638646311797 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_13f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_13f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_13f " "Found entity 1: alt_u_div_13f" {  } { { "db/alt_u_div_13f.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda13/db/alt_u_div_13f.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1638646311821 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1638646311821 ""}
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "6 " "6 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1638646312224 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1638646316088 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "15 " "15 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1638646316508 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1638646316695 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1638646316695 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "1535 " "Implemented 1535 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1638646316800 ""} { "Info" "ICUT_CUT_TM_OPINS" "13 " "Implemented 13 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1638646316800 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1511 " "Implemented 1511 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1638646316800 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1638646316800 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4646 " "Peak virtual memory: 4646 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1638646316821 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 05 03:31:56 2021 " "Processing ended: Sun Dec 05 03:31:56 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1638646316821 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1638646316821 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1638646316821 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1638646316821 ""}