{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1637588999006 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1637588999007 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 22 21:49:58 2021 " "Processing started: Mon Nov 22 21:49:58 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1637588999007 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1637588999007 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off eda12 -c eda12 " "Command: quartus_map --read_settings_files=on --write_settings_files=off eda12 -c eda12" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1637588999007 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "6 6 12 " "Parallel Compilation has detected 12 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 6 of the 6 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1637588999258 ""}
{ "Warning" "WSGN_FILE_IS_MISSING" "eda11.v " "Can't analyze file -- file eda11.v is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1637588999297 ""}
{ "Warning" "WSGN_SEARCH_FILE" "eda12.v 10 10 " "Using design file eda12.v, which is not specified as a design file for the current project, but contains definitions for 10 design units and 10 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 add32 " "Found entity 1: add32" {  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1637588999352 ""} { "Info" "ISGN_ENTITY_NAME" "2 sub32 " "Found entity 2: sub32" {  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 7 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1637588999352 ""} { "Info" "ISGN_ENTITY_NAME" "3 mul16 " "Found entity 3: mul16" {  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 26 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1637588999352 ""} { "Info" "ISGN_ENTITY_NAME" "4 operateselector " "Found entity 4: operateselector" {  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 32 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1637588999352 ""} { "Info" "ISGN_ENTITY_NAME" "5 wordtranslator " "Found entity 5: wordtranslator" {  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 47 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1637588999352 ""} { "Info" "ISGN_ENTITY_NAME" "6 clock " "Found entity 6: clock" {  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 74 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1637588999352 ""} { "Info" "ISGN_ENTITY_NAME" "7 counter " "Found entity 7: counter" {  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 85 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1637588999352 ""} { "Info" "ISGN_ENTITY_NAME" "8 gettempword " "Found entity 8: gettempword" {  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 94 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1637588999352 ""} { "Info" "ISGN_ENTITY_NAME" "9 segselector " "Found entity 9: segselector" {  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 112 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1637588999352 ""} { "Info" "ISGN_ENTITY_NAME" "10 eda12 " "Found entity 10: eda12" {  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 127 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1637588999352 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1637588999352 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "sign eda12.v(142) " "Verilog HDL Implicit Net warning at eda12.v(142): created implicit net for \"sign\"" {  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 142 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1637588999352 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "eda12 " "Elaborating entity \"eda12\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1637588999355 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add32 add32:my_add32 " "Elaborating entity \"add32\" for hierarchy \"add32:my_add32\"" {  } { { "eda12.v" "my_add32" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 141 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999364 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sub32 sub32:my_sub32 " "Elaborating entity \"sub32\" for hierarchy \"sub32:my_sub32\"" {  } { { "eda12.v" "my_sub32" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 142 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999369 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mul16 mul16:my_mul16 " "Elaborating entity \"mul16\" for hierarchy \"mul16:my_mul16\"" {  } { { "eda12.v" "my_mul16" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 143 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999374 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "operateselector operateselector:my_operateselector " "Elaborating entity \"operateselector\" for hierarchy \"operateselector:my_operateselector\"" {  } { { "eda12.v" "my_operateselector" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 145 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999379 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock clock:my_clock " "Elaborating entity \"clock\" for hierarchy \"clock:my_clock\"" {  } { { "eda12.v" "my_clock" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 146 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999386 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 31 eda12.v(80) " "Verilog HDL assignment warning at eda12.v(80): truncated value with size 32 to match size of target (31)" {  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 80 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1637588999386 "|eda12|clock:my_clock"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:my_counter " "Elaborating entity \"counter\" for hierarchy \"counter:my_counter\"" {  } { { "eda12.v" "my_counter" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 147 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999393 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 eda12.v(90) " "Verilog HDL assignment warning at eda12.v(90): truncated value with size 32 to match size of target (3)" {  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 90 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1637588999393 "|eda12|counter:my_counter"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "gettempword gettempword:my_gettempword " "Elaborating entity \"gettempword\" for hierarchy \"gettempword:my_gettempword\"" {  } { { "eda12.v" "my_gettempword" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 149 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999398 ""}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "a eda12.v(103) " "Verilog HDL Always Construct warning at eda12.v(103): variable \"a\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 103 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "Quartus II" 0 -1 1637588999398 "|eda12|gettempword:my_gettempword"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 eda12.v(104) " "Verilog HDL assignment warning at eda12.v(104): truncated value with size 32 to match size of target (4)" {  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 104 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1637588999398 "|eda12|gettempword:my_gettempword"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 eda12.v(105) " "Verilog HDL assignment warning at eda12.v(105): truncated value with size 32 to match size of target (4)" {  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 105 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1637588999398 "|eda12|gettempword:my_gettempword"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 eda12.v(106) " "Verilog HDL assignment warning at eda12.v(106): truncated value with size 32 to match size of target (4)" {  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 106 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1637588999398 "|eda12|gettempword:my_gettempword"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "wordtranslator wordtranslator:my_wordtranslator " "Elaborating entity \"wordtranslator\" for hierarchy \"wordtranslator:my_wordtranslator\"" {  } { { "eda12.v" "my_wordtranslator" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 150 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999405 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segselector segselector:my_segselector " "Elaborating entity \"segselector\" for hierarchy \"segselector:my_segselector\"" {  } { { "eda12.v" "my_segselector" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 152 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999411 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "6 " "Inferred 6 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "mul16:my_mul16\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"mul16:my_mul16\|Mult0\"" {  } { { "eda12.v" "Mult0" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 29 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1637588999575 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "gettempword:my_gettempword\|Div1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"gettempword:my_gettempword\|Div1\"" {  } { { "eda12.v" "Div1" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 105 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1637588999575 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "gettempword:my_gettempword\|Mod1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"gettempword:my_gettempword\|Mod1\"" {  } { { "eda12.v" "Mod1" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 105 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1637588999575 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "gettempword:my_gettempword\|Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"gettempword:my_gettempword\|Div0\"" {  } { { "eda12.v" "Div0" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 104 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1637588999575 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "gettempword:my_gettempword\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"gettempword:my_gettempword\|Mod0\"" {  } { { "eda12.v" "Mod0" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 104 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1637588999575 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "gettempword:my_gettempword\|Mod2 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"gettempword:my_gettempword\|Mod2\"" {  } { { "eda12.v" "Mod2" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 106 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1637588999575 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1637588999575 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "mul16:my_mul16\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"mul16:my_mul16\|lpm_mult:Mult0\"" {  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 29 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1637588999607 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mul16:my_mul16\|lpm_mult:Mult0 " "Instantiated megafunction \"mul16:my_mul16\|lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 4 " "Parameter \"LPM_WIDTHA\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999607 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 4 " "Parameter \"LPM_WIDTHB\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999607 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 8 " "Parameter \"LPM_WIDTHP\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999607 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 8 " "Parameter \"LPM_WIDTHR\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999607 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999607 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999607 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999607 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999607 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999607 ""}  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 29 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1637588999607 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_a7t.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_a7t.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_a7t " "Found entity 1: mult_a7t" {  } { { "db/mult_a7t.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda12/db/mult_a7t.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1637588999650 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1637588999650 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "gettempword:my_gettempword\|lpm_divide:Div1 " "Elaborated megafunction instantiation \"gettempword:my_gettempword\|lpm_divide:Div1\"" {  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 105 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1637588999672 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "gettempword:my_gettempword\|lpm_divide:Div1 " "Instantiated megafunction \"gettempword:my_gettempword\|lpm_divide:Div1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 8 " "Parameter \"LPM_WIDTHN\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999672 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999672 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999672 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999672 ""}  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 105 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1637588999672 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_agm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_agm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_agm " "Found entity 1: lpm_divide_agm" {  } { { "db/lpm_divide_agm.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda12/db/lpm_divide_agm.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1637588999714 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1637588999714 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_bkh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_bkh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_bkh " "Found entity 1: sign_div_unsign_bkh" {  } { { "db/sign_div_unsign_bkh.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda12/db/sign_div_unsign_bkh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1637588999727 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1637588999727 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_13f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_13f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_13f " "Found entity 1: alt_u_div_13f" {  } { { "db/alt_u_div_13f.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda12/db/alt_u_div_13f.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1637588999740 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1637588999740 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_unc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_unc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_unc " "Found entity 1: add_sub_unc" {  } { { "db/add_sub_unc.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda12/db/add_sub_unc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1637588999783 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1637588999783 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_vnc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_vnc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_vnc " "Found entity 1: add_sub_vnc" {  } { { "db/add_sub_vnc.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda12/db/add_sub_vnc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1637588999828 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1637588999828 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "gettempword:my_gettempword\|lpm_divide:Mod1 " "Elaborated megafunction instantiation \"gettempword:my_gettempword\|lpm_divide:Mod1\"" {  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 105 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1637588999834 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "gettempword:my_gettempword\|lpm_divide:Mod1 " "Instantiated megafunction \"gettempword:my_gettempword\|lpm_divide:Mod1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 8 " "Parameter \"LPM_WIDTHN\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999834 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999834 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999834 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999834 ""}  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 105 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1637588999834 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_d8m.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_d8m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_d8m " "Found entity 1: lpm_divide_d8m" {  } { { "db/lpm_divide_d8m.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda12/db/lpm_divide_d8m.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1637588999875 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1637588999875 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "gettempword:my_gettempword\|lpm_divide:Div0 " "Elaborated megafunction instantiation \"gettempword:my_gettempword\|lpm_divide:Div0\"" {  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 104 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1637588999885 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "gettempword:my_gettempword\|lpm_divide:Div0 " "Instantiated megafunction \"gettempword:my_gettempword\|lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 8 " "Parameter \"LPM_WIDTHN\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999885 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 7 " "Parameter \"LPM_WIDTHD\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999885 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999885 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1637588999885 ""}  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 104 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1637588999885 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_dgm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_dgm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_dgm " "Found entity 1: lpm_divide_dgm" {  } { { "db/lpm_divide_dgm.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda12/db/lpm_divide_dgm.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1637588999927 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1637588999927 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_ekh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_ekh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_ekh " "Found entity 1: sign_div_unsign_ekh" {  } { { "db/sign_div_unsign_ekh.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda12/db/sign_div_unsign_ekh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1637588999937 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1637588999937 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_73f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_73f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_73f " "Found entity 1: alt_u_div_73f" {  } { { "db/alt_u_div_73f.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda12/db/alt_u_div_73f.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1637588999951 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1637588999951 ""}
{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "LCELL buffer " "Synthesized away the following LCELL buffer node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mul16:my_mul16\|lpm_mult:Mult0\|mult_a7t:auto_generated\|le5a\[4\] " "Synthesized away node \"mul16:my_mul16\|lpm_mult:Mult0\|mult_a7t:auto_generated\|le5a\[4\]\"" {  } { { "db/mult_a7t.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda12/db/mult_a7t.tdf" 42 6 0 } } { "lpm_mult.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } } { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 29 -1 0 } } { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 143 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1637588999999 "|eda12|mul16:my_mul16|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[4]"}  } {  } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Quartus II" 0 -1 1637588999999 ""}  } {  } 0 14284 "Synthesized away the following node(s):" 0 0 "Quartus II" 0 -1 1637588999999 ""}
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "4 " "4 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1637589000115 ""}
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "48 " "Ignored 48 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_CARRY_SUM" "4 " "Ignored 4 CARRY_SUM buffer(s)" {  } {  } 0 13016 "Ignored %1!d! CARRY_SUM buffer(s)" 0 0 "Quartus II" 0 -1 1637589000120 ""} { "Info" "IMLS_MLS_IGNORED_SOFT" "44 " "Ignored 44 SOFT buffer(s)" {  } {  } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1637589000120 ""}  } {  } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1637589000120 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1637589000248 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "15 " "15 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1637589000414 ""}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "gettempword:my_gettempword\|lpm_divide:Mod1\|lpm_divide_d8m:auto_generated\|sign_div_unsign_bkh:divider\|alt_u_div_13f:divider\|add_sub_7_result_int\[0\]~0 " "Logic cell \"gettempword:my_gettempword\|lpm_divide:Mod1\|lpm_divide_d8m:auto_generated\|sign_div_unsign_bkh:divider\|alt_u_div_13f:divider\|add_sub_7_result_int\[0\]~0\"" {  } { { "db/alt_u_div_13f.tdf" "add_sub_7_result_int\[0\]~0" { Text "C:/Users/Xsu1023/Desktop/eda12/db/alt_u_div_13f.tdf" 61 22 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 -1 1637589000417 ""} { "Info" "ISCL_SCL_CELL_NAME" "gettempword:my_gettempword\|lpm_divide:Mod1\|lpm_divide_d8m:auto_generated\|sign_div_unsign_bkh:divider\|alt_u_div_13f:divider\|add_sub_6_result_int\[0\]~10 " "Logic cell \"gettempword:my_gettempword\|lpm_divide:Mod1\|lpm_divide_d8m:auto_generated\|sign_div_unsign_bkh:divider\|alt_u_div_13f:divider\|add_sub_6_result_int\[0\]~10\"" {  } { { "db/alt_u_div_13f.tdf" "add_sub_6_result_int\[0\]~10" { Text "C:/Users/Xsu1023/Desktop/eda12/db/alt_u_div_13f.tdf" 56 22 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 -1 1637589000417 ""}  } {  } 0 17016 "Found the following redundant logic cells in design" 0 0 "Quartus II" 0 -1 1637589000417 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1637589000528 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1637589000528 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "296 " "Implemented 296 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1637589000560 ""} { "Info" "ICUT_CUT_TM_OPINS" "12 " "Implemented 12 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1637589000560 ""} { "Info" "ICUT_CUT_TM_LCELLS" "273 " "Implemented 273 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1637589000560 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1637589000560 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4632 " "Peak virtual memory: 4632 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1637589000574 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 22 21:50:00 2021 " "Processing ended: Mon Nov 22 21:50:00 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1637589000574 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1637589000574 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1637589000574 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1637589000574 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1637589001485 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1637589001486 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 22 21:50:01 2021 " "Processing started: Mon Nov 22 21:50:01 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1637589001486 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1637589001486 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off eda12 -c eda12 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off eda12 -c eda12" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1637589001486 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #3" {  } {  } 0 0 "qfit2_default_script.tcl version: #3" 0 0 "Fitter" 0 0 1637589001562 ""}
{ "Info" "0" "" "Project  = eda12" {  } {  } 0 0 "Project  = eda12" 0 0 "Fitter" 0 0 1637589001562 ""}
{ "Info" "0" "" "Revision = eda12" {  } {  } 0 0 "Revision = eda12" 0 0 "Fitter" 0 0 1637589001562 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "6 6 12 " "Parallel Compilation has detected 12 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 6 of the 6 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1637589001602 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "eda12 EP3C16Q240C8 " "Selected device EP3C16Q240C8 for design \"eda12\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1637589001613 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1637589001640 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1637589001640 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1637589001687 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C25Q240C8 " "Device EP3C25Q240C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1637589001871 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40Q240C8 " "Device EP3C40Q240C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1637589001871 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1637589001871 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ 12 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location 12" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda12/" { { 0 { 0 ""} 0 685 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1637589001873 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ 14 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 14" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda12/" { { 0 { 0 ""} 0 687 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1637589001873 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ 23 " "Pin ~ALTERA_DCLK~ is reserved at location 23" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda12/" { { 0 { 0 ""} 0 689 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1637589001873 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ 24 " "Pin ~ALTERA_DATA0~ is reserved at location 24" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda12/" { { 0 { 0 ""} 0 691 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1637589001873 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ 162 " "Pin ~ALTERA_nCEO~ is reserved at location 162" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda12/" { { 0 { 0 ""} 0 693 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1637589001873 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1637589001873 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1637589001874 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "eda12.sdc " "Synopsys Design Constraints File file not found: 'eda12.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1637589002274 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1637589002275 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1637589002276 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1637589002277 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1637589002277 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN 152 (CLK4, DIFFCLK_2p)) " "Automatically promoted node clk~input (placed in PIN 152 (CLK4, DIFFCLK_2p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G9 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1637589002288 ""}  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 130 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda12/" { { 0 { 0 ""} 0 680 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1637589002288 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clock:my_clock\|count\[15\]  " "Automatically promoted node clock:my_clock\|count\[15\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1637589002289 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clock:my_clock\|count\[15\]~43 " "Destination node clock:my_clock\|count\[15\]~43" {  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 78 -1 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clock:my_clock|count[15]~43 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda12/" { { 0 { 0 ""} 0 637 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1637589002289 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1637589002289 ""}  } { { "eda12.v" "" { Text "C:/Users/Xsu1023/Desktop/eda12/eda12.v" 78 -1 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clock:my_clock|count[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda12/" { { 0 { 0 ""} 0 107 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1637589002289 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1637589002404 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1637589002404 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1637589002404 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1637589002405 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1637589002405 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1637589002405 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1637589002405 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1637589002406 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1637589002406 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1637589002406 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1637589002406 ""}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "wordselector\[0\] " "Node \"wordselector\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "wordselector\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1637589002417 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "wordselector\[1\] " "Node \"wordselector\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "wordselector\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1637589002417 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1637589002417 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1637589002417 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1637589002751 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1637589002822 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1637589002829 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1637589003108 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1637589003108 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1637589003261 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X31_Y10 X41_Y19 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X31_Y10 to location X41_Y19" {  } { { "loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda12/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X31_Y10 to location X41_Y19"} { { 11 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X31_Y10 to location X41_Y19"} 31 10 11 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1637589003922 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1637589003922 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1637589004334 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1637589004335 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1637589004335 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.25 " "Total time spent on timing analysis during the Fitter is 0.25 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1637589004341 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1637589004365 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1637589004557 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1637589004580 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1637589004649 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1637589004902 ""}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1637589005144 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Xsu1023/Desktop/eda12/output_files/eda12.fit.smsg " "Generated suppressed messages file C:/Users/Xsu1023/Desktop/eda12/output_files/eda12.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1637589005197 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5433 " "Peak virtual memory: 5433 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1637589005371 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 22 21:50:05 2021 " "Processing ended: Mon Nov 22 21:50:05 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1637589005371 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1637589005371 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1637589005371 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1637589005371 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1637589006142 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1637589006142 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 22 21:50:06 2021 " "Processing started: Mon Nov 22 21:50:06 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1637589006142 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1637589006142 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off eda12 -c eda12 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off eda12 -c eda12" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1637589006142 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1637589006706 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1637589006722 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4552 " "Peak virtual memory: 4552 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1637589006967 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 22 21:50:06 2021 " "Processing ended: Mon Nov 22 21:50:06 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1637589006967 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1637589006967 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1637589006967 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1637589006967 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1637589007526 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1637589007867 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1637589007868 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 22 21:50:07 2021 " "Processing started: Mon Nov 22 21:50:07 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1637589007868 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1637589007868 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta eda12 -c eda12 " "Command: quartus_sta eda12 -c eda12" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1637589007868 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1637589007946 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "6 6 12 " "Parallel Compilation has detected 12 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 6 of the 6 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1637589008058 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1637589008089 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1637589008090 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "eda12.sdc " "Synopsys Design Constraints File file not found: 'eda12.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1637589008196 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1637589008196 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008197 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clock:my_clock\|count\[15\] clock:my_clock\|count\[15\] " "create_clock -period 1.000 -name clock:my_clock\|count\[15\] clock:my_clock\|count\[15\]" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008197 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008197 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1637589008280 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008280 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1637589008281 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1637589008287 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1637589008294 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1637589008294 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.894 " "Worst-case setup slack is -1.894" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008295 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008295 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.894       -18.520 clk  " "   -1.894       -18.520 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008295 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.310        -0.324 clock:my_clock\|count\[15\]  " "   -0.310        -0.324 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008295 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1637589008295 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.230 " "Worst-case hold slack is 0.230" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008298 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008298 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.230         0.000 clk  " "    0.230         0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008298 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.455         0.000 clock:my_clock\|count\[15\]  " "    0.455         0.000 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008298 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1637589008298 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1637589008300 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1637589008301 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008302 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008302 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000       -26.792 clk  " "   -3.000       -26.792 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008302 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.487        -4.461 clock:my_clock\|count\[15\]  " "   -1.487        -4.461 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008302 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1637589008302 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1637589008331 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1637589008345 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1637589008619 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008645 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1637589008649 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1637589008649 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.571 " "Worst-case setup slack is -1.571" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008651 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008651 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.571       -15.020 clk  " "   -1.571       -15.020 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008651 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.180        -0.180 clock:my_clock\|count\[15\]  " "   -0.180        -0.180 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008651 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1637589008651 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.340 " "Worst-case hold slack is 0.340" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008654 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008654 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.340         0.000 clk  " "    0.340         0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008654 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.403         0.000 clock:my_clock\|count\[15\]  " "    0.403         0.000 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008654 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1637589008654 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1637589008657 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1637589008659 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008661 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008661 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000       -26.792 clk  " "   -3.000       -26.792 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008661 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.487        -4.461 clock:my_clock\|count\[15\]  " "   -1.487        -4.461 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008661 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1637589008661 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1637589008694 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008751 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1637589008752 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1637589008752 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.280 " "Worst-case setup slack is -0.280" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008755 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008755 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.280        -0.694 clk  " "   -0.280        -0.694 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008755 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.429         0.000 clock:my_clock\|count\[15\]  " "    0.429         0.000 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008755 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1637589008755 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.085 " "Worst-case hold slack is -0.085" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008759 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008759 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.085        -0.085 clk  " "   -0.085        -0.085 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008759 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.188         0.000 clock:my_clock\|count\[15\]  " "    0.188         0.000 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008759 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1637589008759 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1637589008763 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1637589008768 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008771 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008771 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000       -19.970 clk  " "   -3.000       -19.970 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008771 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -3.000 clock:my_clock\|count\[15\]  " "   -1.000        -3.000 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1637589008771 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1637589008771 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1637589008910 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1637589008910 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4639 " "Peak virtual memory: 4639 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1637589008959 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 22 21:50:08 2021 " "Processing ended: Mon Nov 22 21:50:08 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1637589008959 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1637589008959 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1637589008959 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1637589008959 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1637589009787 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1637589009787 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 22 21:50:09 2021 " "Processing started: Mon Nov 22 21:50:09 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1637589009787 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1637589009787 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off eda12 -c eda12 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off eda12 -c eda12" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1637589009787 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "eda12_8_1200mv_85c_slow.vo C:/Users/Xsu1023/Desktop/eda12/simulation/modelsim/ simulation " "Generated file eda12_8_1200mv_85c_slow.vo in folder \"C:/Users/Xsu1023/Desktop/eda12/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1637589010134 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "eda12_8_1200mv_0c_slow.vo C:/Users/Xsu1023/Desktop/eda12/simulation/modelsim/ simulation " "Generated file eda12_8_1200mv_0c_slow.vo in folder \"C:/Users/Xsu1023/Desktop/eda12/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1637589010178 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "eda12_min_1200mv_0c_fast.vo C:/Users/Xsu1023/Desktop/eda12/simulation/modelsim/ simulation " "Generated file eda12_min_1200mv_0c_fast.vo in folder \"C:/Users/Xsu1023/Desktop/eda12/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1637589010221 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "eda12.vo C:/Users/Xsu1023/Desktop/eda12/simulation/modelsim/ simulation " "Generated file eda12.vo in folder \"C:/Users/Xsu1023/Desktop/eda12/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1637589010262 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "eda12_8_1200mv_85c_v_slow.sdo C:/Users/Xsu1023/Desktop/eda12/simulation/modelsim/ simulation " "Generated file eda12_8_1200mv_85c_v_slow.sdo in folder \"C:/Users/Xsu1023/Desktop/eda12/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1637589010290 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "eda12_8_1200mv_0c_v_slow.sdo C:/Users/Xsu1023/Desktop/eda12/simulation/modelsim/ simulation " "Generated file eda12_8_1200mv_0c_v_slow.sdo in folder \"C:/Users/Xsu1023/Desktop/eda12/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1637589010317 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "eda12_min_1200mv_0c_v_fast.sdo C:/Users/Xsu1023/Desktop/eda12/simulation/modelsim/ simulation " "Generated file eda12_min_1200mv_0c_v_fast.sdo in folder \"C:/Users/Xsu1023/Desktop/eda12/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1637589010346 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "eda12_v.sdo C:/Users/Xsu1023/Desktop/eda12/simulation/modelsim/ simulation " "Generated file eda12_v.sdo in folder \"C:/Users/Xsu1023/Desktop/eda12/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1637589010375 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4526 " "Peak virtual memory: 4526 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1637589010403 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 22 21:50:10 2021 " "Processing ended: Mon Nov 22 21:50:10 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1637589010403 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1637589010403 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1637589010403 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1637589010403 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 23 s " "Quartus II Full Compilation was successful. 0 errors, 23 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1637589010985 ""}