{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1639713118062 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1639713118062 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 17 11:51:57 2021 " "Processing started: Fri Dec 17 11:51:57 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1639713118062 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1639713118062 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off eda2 -c eda2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off eda2 -c eda2" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1639713118062 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "6 6 12 " "Parallel Compilation has detected 12 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 6 of the 6 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1639713118325 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "IN_5c in_5c eda2.v(362) " "Verilog HDL Declaration information at eda2.v(362): object \"IN_5c\" differs only in case from object \"in_5c\" in the same scope" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 362 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1639713118357 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "IN_10c in_10c eda2.v(362) " "Verilog HDL Declaration information at eda2.v(362): object \"IN_10c\" differs only in case from object \"in_10c\" in the same scope" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 362 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1639713118357 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "IN_50c in_50c eda2.v(362) " "Verilog HDL Declaration information at eda2.v(362): object \"IN_50c\" differs only in case from object \"in_50c\" in the same scope" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 362 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1639713118357 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "OUT_15c out_15c eda2.v(362) " "Verilog HDL Declaration information at eda2.v(362): object \"OUT_15c\" differs only in case from object \"out_15c\" in the same scope" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 362 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1639713118357 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "OUT_25c out_25c eda2.v(362) " "Verilog HDL Declaration information at eda2.v(362): object \"OUT_25c\" differs only in case from object \"out_25c\" in the same scope" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 362 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1639713118357 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "eda2.v 9 9 " "Found 9 design units, including 9 entities, in source file eda2.v" { { "Info" "ISGN_ENTITY_NAME" "1 debounce " "Found entity 1: debounce" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 14 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713118358 ""} { "Info" "ISGN_ENTITY_NAME" "2 clock " "Found entity 2: clock" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 52 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713118358 ""} { "Info" "ISGN_ENTITY_NAME" "3 numbertranslator " "Found entity 3: numbertranslator" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 72 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713118358 ""} { "Info" "ISGN_ENTITY_NAME" "4 gettempnumber " "Found entity 4: gettempnumber" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 101 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713118358 ""} { "Info" "ISGN_ENTITY_NAME" "5 segtranslator " "Found entity 5: segtranslator" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 123 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713118358 ""} { "Info" "ISGN_ENTITY_NAME" "6 counter " "Found entity 6: counter" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 145 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713118358 ""} { "Info" "ISGN_ENTITY_NAME" "7 FSM " "Found entity 7: FSM" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 172 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713118358 ""} { "Info" "ISGN_ENTITY_NAME" "8 calculator " "Found entity 8: calculator" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 266 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713118358 ""} { "Info" "ISGN_ENTITY_NAME" "9 eda2 " "Found entity 9: eda2" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 350 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713118358 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1639713118358 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "eda2 " "Elaborating entity \"eda2\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1639713118416 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "debounce debounce:in_5c " "Elaborating entity \"debounce\" for hierarchy \"debounce:in_5c\"" {  } { { "eda2.v" "in_5c" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 365 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713118424 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 eda2.v(40) " "Verilog HDL assignment warning at eda2.v(40): truncated value with size 32 to match size of target (8)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 40 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713118425 "|eda2|debounce:in_5c"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock clock:my_clock " "Elaborating entity \"clock\" for hierarchy \"clock:my_clock\"" {  } { { "eda2.v" "my_clock" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 372 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713118434 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 31 eda2.v(58) " "Verilog HDL assignment warning at eda2.v(58): truncated value with size 32 to match size of target (31)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 58 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713118434 "|eda2|clock:my_clock"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FSM FSM:my_FSM " "Elaborating entity \"FSM\" for hierarchy \"FSM:my_FSM\"" {  } { { "eda2.v" "my_FSM" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 375 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713118441 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "calculator calculator:my_calculator " "Elaborating entity \"calculator\" for hierarchy \"calculator:my_calculator\"" {  } { { "eda2.v" "my_calculator" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 376 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713118448 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 eda2.v(301) " "Verilog HDL assignment warning at eda2.v(301): truncated value with size 32 to match size of target (10)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 301 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713118449 "|eda2|calculator:my_calculator"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 eda2.v(306) " "Verilog HDL assignment warning at eda2.v(306): truncated value with size 32 to match size of target (10)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 306 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713118449 "|eda2|calculator:my_calculator"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 eda2.v(311) " "Verilog HDL assignment warning at eda2.v(311): truncated value with size 32 to match size of target (10)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 311 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713118449 "|eda2|calculator:my_calculator"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 eda2.v(317) " "Verilog HDL assignment warning at eda2.v(317): truncated value with size 32 to match size of target (10)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 317 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713118449 "|eda2|calculator:my_calculator"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 eda2.v(326) " "Verilog HDL assignment warning at eda2.v(326): truncated value with size 32 to match size of target (10)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 326 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713118450 "|eda2|calculator:my_calculator"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 eda2.v(333) " "Verilog HDL assignment warning at eda2.v(333): truncated value with size 32 to match size of target (9)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 333 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713118450 "|eda2|calculator:my_calculator"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:my_counter " "Elaborating entity \"counter\" for hierarchy \"counter:my_counter\"" {  } { { "eda2.v" "my_counter" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 379 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713118460 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 eda2.v(150) " "Verilog HDL assignment warning at eda2.v(150): truncated value with size 32 to match size of target (2)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 150 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713118460 "|eda2|counter:my_counter"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segtranslator segtranslator:my_segtranslator " "Elaborating entity \"segtranslator\" for hierarchy \"segtranslator:my_segtranslator\"" {  } { { "eda2.v" "my_segtranslator" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 380 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713118465 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "gettempnumber gettempnumber:my_gettempnumber " "Elaborating entity \"gettempnumber\" for hierarchy \"gettempnumber:my_gettempnumber\"" {  } { { "eda2.v" "my_gettempnumber" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 381 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713118470 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 eda2.v(108) " "Verilog HDL assignment warning at eda2.v(108): truncated value with size 32 to match size of target (5)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 108 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713118470 "|eda2|gettempnumber:my_gettempnumber"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 eda2.v(109) " "Verilog HDL assignment warning at eda2.v(109): truncated value with size 32 to match size of target (5)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 109 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713118470 "|eda2|gettempnumber:my_gettempnumber"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 eda2.v(110) " "Verilog HDL assignment warning at eda2.v(110): truncated value with size 32 to match size of target (5)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 110 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713118470 "|eda2|gettempnumber:my_gettempnumber"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "numbertranslator numbertranslator:my_numbertranslator " "Elaborating entity \"numbertranslator\" for hierarchy \"numbertranslator:my_numbertranslator\"" {  } { { "eda2.v" "my_numbertranslator" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 382 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713118475 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "5 " "Inferred 5 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "gettempnumber:my_gettempnumber\|Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"gettempnumber:my_gettempnumber\|Div0\"" {  } { { "eda2.v" "Div0" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 108 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713118706 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "gettempnumber:my_gettempnumber\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"gettempnumber:my_gettempnumber\|Mod0\"" {  } { { "eda2.v" "Mod0" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 108 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713118706 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "gettempnumber:my_gettempnumber\|Div1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"gettempnumber:my_gettempnumber\|Div1\"" {  } { { "eda2.v" "Div1" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 109 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713118706 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "gettempnumber:my_gettempnumber\|Mod1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"gettempnumber:my_gettempnumber\|Mod1\"" {  } { { "eda2.v" "Mod1" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 109 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713118706 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "gettempnumber:my_gettempnumber\|Mod2 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"gettempnumber:my_gettempnumber\|Mod2\"" {  } { { "eda2.v" "Mod2" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 110 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713118706 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1639713118706 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "gettempnumber:my_gettempnumber\|lpm_divide:Div0 " "Elaborated megafunction instantiation \"gettempnumber:my_gettempnumber\|lpm_divide:Div0\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 108 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713118739 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "gettempnumber:my_gettempnumber\|lpm_divide:Div0 " "Instantiated megafunction \"gettempnumber:my_gettempnumber\|lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 10 " "Parameter \"LPM_WIDTHN\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713118739 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 7 " "Parameter \"LPM_WIDTHD\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713118739 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713118739 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713118739 ""}  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 108 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1639713118739 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_mhm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_mhm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_mhm " "Found entity 1: lpm_divide_mhm" {  } { { "db/lpm_divide_mhm.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/lpm_divide_mhm.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713118787 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1639713118787 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_nlh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_nlh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_nlh " "Found entity 1: sign_div_unsign_nlh" {  } { { "db/sign_div_unsign_nlh.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/sign_div_unsign_nlh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713118801 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1639713118801 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_p5f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_p5f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_p5f " "Found entity 1: alt_u_div_p5f" {  } { { "db/alt_u_div_p5f.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/alt_u_div_p5f.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713118820 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1639713118820 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_unc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_unc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_unc " "Found entity 1: add_sub_unc" {  } { { "db/add_sub_unc.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/add_sub_unc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713118884 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1639713118884 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_vnc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_vnc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_vnc " "Found entity 1: add_sub_vnc" {  } { { "db/add_sub_vnc.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/add_sub_vnc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713118938 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1639713118938 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "gettempnumber:my_gettempnumber\|lpm_divide:Mod0 " "Elaborated megafunction instantiation \"gettempnumber:my_gettempnumber\|lpm_divide:Mod0\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 108 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713118946 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "gettempnumber:my_gettempnumber\|lpm_divide:Mod0 " "Instantiated megafunction \"gettempnumber:my_gettempnumber\|lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 10 " "Parameter \"LPM_WIDTHN\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713118946 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713118946 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713118946 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713118946 ""}  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 108 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1639713118946 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_m9m.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_m9m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_m9m " "Found entity 1: lpm_divide_m9m" {  } { { "db/lpm_divide_m9m.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/lpm_divide_m9m.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713118997 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1639713118997 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_klh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_klh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_klh " "Found entity 1: sign_div_unsign_klh" {  } { { "db/sign_div_unsign_klh.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/sign_div_unsign_klh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713119010 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1639713119010 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_j5f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_j5f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_j5f " "Found entity 1: alt_u_div_j5f" {  } { { "db/alt_u_div_j5f.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/alt_u_div_j5f.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713119024 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1639713119024 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "gettempnumber:my_gettempnumber\|lpm_divide:Div1 " "Elaborated megafunction instantiation \"gettempnumber:my_gettempnumber\|lpm_divide:Div1\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 109 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713119034 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "gettempnumber:my_gettempnumber\|lpm_divide:Div1 " "Instantiated megafunction \"gettempnumber:my_gettempnumber\|lpm_divide:Div1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 10 " "Parameter \"LPM_WIDTHN\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713119034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713119034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713119034 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713119034 ""}  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 109 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1639713119034 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_jhm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_jhm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_jhm " "Found entity 1: lpm_divide_jhm" {  } { { "db/lpm_divide_jhm.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/lpm_divide_jhm.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713119087 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1639713119087 ""}
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1639713119274 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 282 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1639713119291 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1639713119291 ""}
{ "Warning" "WMLS_MLS_CREATED_ALOAD_CCT" "" "Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state." { { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "debounce:in_10c\|out debounce:in_10c\|out~_emulated debounce:in_10c\|out~1 " "Register \"debounce:in_10c\|out\" is converted into an equivalent circuit using register \"debounce:in_10c\|out~_emulated\" and latch \"debounce:in_10c\|out~1\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 17 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Quartus II" 0 -1 1639713119292 "|eda2|debounce:in_10c|out"} { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "debounce:in_5c\|out debounce:in_5c\|out~_emulated debounce:in_5c\|out~1 " "Register \"debounce:in_5c\|out\" is converted into an equivalent circuit using register \"debounce:in_5c\|out~_emulated\" and latch \"debounce:in_5c\|out~1\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 17 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Quartus II" 0 -1 1639713119292 "|eda2|debounce:in_5c|out"} { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "debounce:in_50c\|out debounce:in_50c\|out~_emulated debounce:in_50c\|out~1 " "Register \"debounce:in_50c\|out\" is converted into an equivalent circuit using register \"debounce:in_50c\|out~_emulated\" and latch \"debounce:in_50c\|out~1\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 17 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Quartus II" 0 -1 1639713119292 "|eda2|debounce:in_50c|out"} { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "debounce:out_15c\|out debounce:out_15c\|out~_emulated debounce:out_15c\|out~1 " "Register \"debounce:out_15c\|out\" is converted into an equivalent circuit using register \"debounce:out_15c\|out~_emulated\" and latch \"debounce:out_15c\|out~1\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 17 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Quartus II" 0 -1 1639713119292 "|eda2|debounce:out_15c|out"} { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "debounce:out_25c\|out debounce:out_25c\|out~_emulated debounce:out_25c\|out~1 " "Register \"debounce:out_25c\|out\" is converted into an equivalent circuit using register \"debounce:out_25c\|out~_emulated\" and latch \"debounce:out_25c\|out~1\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 17 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Quartus II" 0 -1 1639713119292 "|eda2|debounce:out_25c|out"} { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "debounce:in_10c\|last debounce:in_10c\|last~_emulated debounce:in_10c\|out~1 " "Register \"debounce:in_10c\|last\" is converted into an equivalent circuit using register \"debounce:in_10c\|last~_emulated\" and latch \"debounce:in_10c\|out~1\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 21 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Quartus II" 0 -1 1639713119292 "|eda2|debounce:in_10c|last"} { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "debounce:in_5c\|last debounce:in_5c\|last~_emulated debounce:in_5c\|out~1 " "Register \"debounce:in_5c\|last\" is converted into an equivalent circuit using register \"debounce:in_5c\|last~_emulated\" and latch \"debounce:in_5c\|out~1\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 21 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Quartus II" 0 -1 1639713119292 "|eda2|debounce:in_5c|last"} { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "debounce:in_50c\|last debounce:in_50c\|last~_emulated debounce:in_50c\|out~1 " "Register \"debounce:in_50c\|last\" is converted into an equivalent circuit using register \"debounce:in_50c\|last~_emulated\" and latch \"debounce:in_50c\|out~1\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 21 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Quartus II" 0 -1 1639713119292 "|eda2|debounce:in_50c|last"} { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "debounce:out_15c\|last debounce:out_15c\|last~_emulated debounce:out_15c\|out~1 " "Register \"debounce:out_15c\|last\" is converted into an equivalent circuit using register \"debounce:out_15c\|last~_emulated\" and latch \"debounce:out_15c\|out~1\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 21 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Quartus II" 0 -1 1639713119292 "|eda2|debounce:out_15c|last"} { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "debounce:out_25c\|last debounce:out_25c\|last~_emulated debounce:out_25c\|out~1 " "Register \"debounce:out_25c\|last\" is converted into an equivalent circuit using register \"debounce:out_25c\|last~_emulated\" and latch \"debounce:out_25c\|out~1\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 21 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Quartus II" 0 -1 1639713119292 "|eda2|debounce:out_25c|last"}  } {  } 0 13004 "Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state." 0 0 "Quartus II" 0 -1 1639713119292 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "segout\[0\] VCC " "Pin \"segout\[0\]\" is stuck at VCC" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 353 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1639713119429 "|eda2|segout[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "segout\[1\] VCC " "Pin \"segout\[1\]\" is stuck at VCC" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 353 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1639713119429 "|eda2|segout[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "segout\[2\] VCC " "Pin \"segout\[2\]\" is stuck at VCC" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 353 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1639713119429 "|eda2|segout[2]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1639713119429 ""}
{ "Critical Warning" "WFTM_FTM_POWER_UP_HIGH_IGNORED_GROUP" "" "Ignored Power-Up Level option on the following registers" { { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "calculator:my_calculator\|clear High " "Register calculator:my_calculator\|clear will power up to High" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 282 -1 0 } }  } 1 18010 "Register %1!s! will power up to %2!s!" 0 0 "Quartus II" 0 -1 1639713119433 ""}  } {  } 1 18061 "Ignored Power-Up Level option on the following registers" 0 0 "Quartus II" 0 -1 1639713119433 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1639713119518 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "18 " "18 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1639713119823 ""}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "gettempnumber:my_gettempnumber\|lpm_divide:Mod1\|lpm_divide_m9m:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_j5f:divider\|add_sub_6_result_int\[0\]~10 " "Logic cell \"gettempnumber:my_gettempnumber\|lpm_divide:Mod1\|lpm_divide_m9m:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_j5f:divider\|add_sub_6_result_int\[0\]~10\"" {  } { { "db/alt_u_div_j5f.tdf" "add_sub_6_result_int\[0\]~10" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/alt_u_div_j5f.tdf" 56 22 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713119828 ""} { "Info" "ISCL_SCL_CELL_NAME" "gettempnumber:my_gettempnumber\|lpm_divide:Mod1\|lpm_divide_m9m:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_j5f:divider\|add_sub_7_result_int\[0\]~10 " "Logic cell \"gettempnumber:my_gettempnumber\|lpm_divide:Mod1\|lpm_divide_m9m:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_j5f:divider\|add_sub_7_result_int\[0\]~10\"" {  } { { "db/alt_u_div_j5f.tdf" "add_sub_7_result_int\[0\]~10" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/alt_u_div_j5f.tdf" 61 22 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713119828 ""} { "Info" "ISCL_SCL_CELL_NAME" "gettempnumber:my_gettempnumber\|lpm_divide:Mod1\|lpm_divide_m9m:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_j5f:divider\|add_sub_8_result_int\[0\]~10 " "Logic cell \"gettempnumber:my_gettempnumber\|lpm_divide:Mod1\|lpm_divide_m9m:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_j5f:divider\|add_sub_8_result_int\[0\]~10\"" {  } { { "db/alt_u_div_j5f.tdf" "add_sub_8_result_int\[0\]~10" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/alt_u_div_j5f.tdf" 66 22 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713119828 ""} { "Info" "ISCL_SCL_CELL_NAME" "gettempnumber:my_gettempnumber\|lpm_divide:Mod0\|lpm_divide_m9m:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_j5f:divider\|add_sub_9_result_int\[0\]~0 " "Logic cell \"gettempnumber:my_gettempnumber\|lpm_divide:Mod0\|lpm_divide_m9m:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_j5f:divider\|add_sub_9_result_int\[0\]~0\"" {  } { { "db/alt_u_div_j5f.tdf" "add_sub_9_result_int\[0\]~0" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/alt_u_div_j5f.tdf" 71 22 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713119828 ""} { "Info" "ISCL_SCL_CELL_NAME" "gettempnumber:my_gettempnumber\|lpm_divide:Mod1\|lpm_divide_m9m:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_j5f:divider\|add_sub_9_result_int\[0\]~10 " "Logic cell \"gettempnumber:my_gettempnumber\|lpm_divide:Mod1\|lpm_divide_m9m:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_j5f:divider\|add_sub_9_result_int\[0\]~10\"" {  } { { "db/alt_u_div_j5f.tdf" "add_sub_9_result_int\[0\]~10" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/alt_u_div_j5f.tdf" 71 22 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713119828 ""}  } {  } 0 17016 "Found the following redundant logic cells in design" 0 0 "Quartus II" 0 -1 1639713119828 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Xsu1023/Desktop/eda2_/output_files/eda2.map.smsg " "Generated suppressed messages file C:/Users/Xsu1023/Desktop/eda2_/output_files/eda2.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1639713119886 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1639713119975 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713119975 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "600 " "Implemented 600 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "7 " "Implemented 7 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1639713120025 ""} { "Info" "ICUT_CUT_TM_OPINS" "16 " "Implemented 16 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1639713120025 ""} { "Info" "ICUT_CUT_TM_LCELLS" "577 " "Implemented 577 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1639713120025 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1639713120025 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 30 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4630 " "Peak virtual memory: 4630 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1639713120041 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 17 11:52:00 2021 " "Processing ended: Fri Dec 17 11:52:00 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1639713120041 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1639713120041 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1639713120041 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1639713120041 ""}